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style: refactor error handling in rib modules and improve RTL naming conventions

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- Renamed error signals in rib2ribp, rib_error_slave, ribp2axi4, and ribp2rib modules for consistency.
- Updated state machine logic to use new error signal names.
- Enhanced RTL style checking scripts to enforce naming conventions and positional parameter connections.
- Introduced migration scripts to convert positional instances to named connections and shorten local identifiers.
- Added tests to validate migration scripts and ensure correct functionality.
This commit is contained in:
maksyuki committed 2026-08-12 22:18:19 +08:00
1 parent 1b22480ba5
commit 4e311b1a51
80 files changed
+4062 -2615
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Makefile
+9 -1
View File
@@ -258,7 +258,7 @@ endif
.PHONY: help config doctor setup setup-regression setup-mpw setup-clusterip setup-ip setup-pdk setup-app \ .PHONY: help config doctor setup setup-regression setup-mpw setup-clusterip setup-ip setup-pdk setup-app \
clean-all purge-cache manifest check-warnings metrics check-metrics package \ clean-all purge-cache manifest check-warnings metrics check-metrics package \
regress-smoke regress-pr regress-nightly sim-asm format format-check sw-format sw-format-check mk-format \ regress-smoke regress-pr regress-nightly sim-asm format format-check sw-format sw-format-check mk-format \
mk-format-check rtl-format rtl-format-check rtl-style-check sw-policy-check sw-host-test \ mk-format-check rtl-format rtl-format-check rtl-style-check rtl-migrate-connections rtl-migrate-names sw-policy-check sw-host-test \
benchmark-report coremark-report \ benchmark-report coremark-report \
pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \ pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \
check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \ check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \
@@ -303,6 +303,8 @@ help:
' sw-format-check check embedded C whitespace and line-ending policy' \ ' sw-format-check check embedded C whitespace and line-ending policy' \
' mk-format | mk-format-check apply/check tracked Makefile formatting' \ ' mk-format | mk-format-check apply/check tracked Makefile formatting' \
' rtl-format | rtl-format-check apply/check self-owned RTL formatting' \ ' rtl-format | rtl-format-check apply/check self-owned RTL formatting' \
' rtl-migrate-connections convert provably positional RTL instances to named ports' \
' rtl-migrate-names shorten local RTL identifier names' \
' rtl-style-check check changed self-owned RTL naming and connections' \ ' rtl-style-check check changed self-owned RTL naming and connections' \
' sw-policy-check check embedded C API and naming policy' \ ' sw-policy-check check embedded C API and naming policy' \
' sw-host-test run host tests for deterministic SDK utilities' \ ' sw-host-test run host tests for deterministic SDK utilities' \
@@ -427,6 +429,12 @@ rtl-format-check:
python3 $(ROOT_PATH)/scripts/check_format.py --root $(ROOT_PATH) --kind rtl \ python3 $(ROOT_PATH)/scripts/check_format.py --root $(ROOT_PATH) --kind rtl \
--verible-verilog-format $(VERIBLE_FORMAT) --verible-verilog-format $(VERIBLE_FORMAT)
rtl-migrate-connections:
python3 $(ROOT_PATH)/scripts/migrate_rtl_connections.py --root $(ROOT_PATH) --apply
rtl-migrate-names:
python3 $(ROOT_PATH)/scripts/migrate_rtl_names.py --root $(ROOT_PATH) --apply
rtl-style-check: rtl-style-check:
python3 $(ROOT_PATH)/scripts/check_rtl_style.py --root $(ROOT_PATH) \ python3 $(ROOT_PATH)/scripts/check_rtl_style.py --root $(ROOT_PATH) \
--profile owned --changed-only --verible-verilog-lint $(VERIBLE_LINT) --profile owned --changed-only --verible-verilog-lint $(VERIBLE_LINT)
docs/rtl-coding-style.md
+10
View File
@@ -32,6 +32,10 @@ New local signals use concise industry-standard abbreviations:
Do not change an external protocol field only to shorten its name. Use a local Do not change an external protocol field only to shorten its name. Use a local
alias at the boundary when a legacy or third-party interface uses a long name. alias at the boundary when a legacy or third-party interface uses a long name.
The checked-in [`scripts/migrate_rtl_names.py`](../scripts/migrate_rtl_names.py)
helper applies this rule mechanically: it shortens only `s_`/`r_` locals and
known automatic variables, never a public port or interface member.
## Structure ## Structure
Keep each module in this order: module header, parameters, ports, localparams, Keep each module in this order: module header, parameters, ports, localparams,
@@ -50,6 +54,12 @@ Every module instance in self-owned RTL must use named parameter and port
connections. Empty connections are permitted only for intentionally unused connections. Empty connections are permitted only for intentionally unused
technology pins or interface fields and must be documented. technology pins or interface fields and must be documented.
For existing positional instances, use the conservative
[`scripts/migrate_rtl_connections.py`](../scripts/migrate_rtl_connections.py)
helper. It only changes an instance when the declaration and argument counts
are unambiguous. Instances it reports as ambiguous require manual conversion;
the helper never guesses across duplicate or non-ANSI module declarations.
## Formatting ## Formatting
Run: Run:
rtl/ip/ribp/interconnect/axi4l2ribp.sv
+62 -46
View File
@@ -70,11 +70,13 @@ module axi4l2ribp (
default: s_rd_fsm_d = RD_IDLE; default: s_rd_fsm_d = RD_IDLE;
endcase endcase
end end
dffr #(2) u_rd_fsm_dffr ( dffr #(
aclk_i, .DATA_WIDTH(2)
aresetn_i, ) u_rd_fsm_dffr (
s_rd_fsm_d, .clk_i (aclk_i),
s_rd_fsm_q .rst_n_i(aresetn_i),
.dat_i (s_rd_fsm_d),
.dat_o (s_rd_fsm_q)
); );
always_comb begin always_comb begin
@@ -95,11 +97,13 @@ module axi4l2ribp (
default: s_wr_fsm_d = WR_IDLE; default: s_wr_fsm_d = WR_IDLE;
endcase endcase
end end
dffr #(2) u_wr_fsm_dffr ( dffr #(
aclk_i, .DATA_WIDTH(2)
aresetn_i, ) u_wr_fsm_dffr (
s_wr_fsm_d, .clk_i (aclk_i),
s_wr_fsm_q .rst_n_i(aresetn_i),
.dat_i (s_wr_fsm_d),
.dat_o (s_wr_fsm_q)
); );
always_comb begin always_comb begin
@@ -112,57 +116,69 @@ module axi4l2ribp (
s_addr_d = awaddr_i; s_addr_d = awaddr_i;
end end
end end
dffer #(32) u_addr_dffer ( dffer #(
aclk_i, .DATA_WIDTH(32)
aresetn_i, ) u_addr_dffer (
(s_rd_fsm_q == RD_IDLE && arvalid_i) || (s_wr_fsm_q == WR_IDLE && awvalid_i), .clk_i (aclk_i),
s_addr_d, .rst_n_i(aresetn_i),
s_addr_q .en_i ((s_rd_fsm_q == RD_IDLE && arvalid_i) || (s_wr_fsm_q == WR_IDLE && awvalid_i)),
.dat_i (s_addr_d),
.dat_o (s_addr_q)
); );
assign s_rdata_d = ribp.rdata; assign s_rdata_d = ribp.rdata;
dffer #(32) u_rdata_dffer ( dffer #(
aclk_i, .DATA_WIDTH(32)
aresetn_i, ) u_rdata_dffer (
s_rd_fsm_q == RD_DATA && ribp.ready, .clk_i (aclk_i),
s_rdata_d, .rst_n_i(aresetn_i),
s_rdata_q .en_i (s_rd_fsm_q == RD_DATA && ribp.ready),
.dat_i (s_rdata_d),
.dat_o (s_rdata_q)
); );
assign s_rresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY; assign s_rresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY;
dffer #(2) u_rresp_dffer ( dffer #(
aclk_i, .DATA_WIDTH(2)
aresetn_i, ) u_rresp_dffer (
s_rd_fsm_q == RD_DATA && ribp.ready, .clk_i (aclk_i),
s_rresp_d, .rst_n_i(aresetn_i),
s_rresp_q .en_i (s_rd_fsm_q == RD_DATA && ribp.ready),
.dat_i (s_rresp_d),
.dat_o (s_rresp_q)
); );
assign s_wdata_d = wdata_i; assign s_wdata_d = wdata_i;
dffer #(32) u_wdata_dffer ( dffer #(
aclk_i, .DATA_WIDTH(32)
aresetn_i, ) u_wdata_dffer (
s_wr_fsm_q == WR_DATA && wvalid_i, .clk_i (aclk_i),
s_wdata_d, .rst_n_i(aresetn_i),
s_wdata_q .en_i (s_wr_fsm_q == WR_DATA && wvalid_i),
.dat_i (s_wdata_d),
.dat_o (s_wdata_q)
); );
assign s_wstrb_d = wstrb_i; assign s_wstrb_d = wstrb_i;
dffer #(4) u_wstrb_dffer ( dffer #(
aclk_i, .DATA_WIDTH(4)
aresetn_i, ) u_wstrb_dffer (
s_wr_fsm_q == WR_DATA && wvalid_i, .clk_i (aclk_i),
s_wstrb_d, .rst_n_i(aresetn_i),
s_wstrb_q .en_i (s_wr_fsm_q == WR_DATA && wvalid_i),
.dat_i (s_wstrb_d),
.dat_o (s_wstrb_q)
); );
assign s_bresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY; assign s_bresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY;
dffer #(2) u_bresp_dffer ( dffer #(
aclk_i, .DATA_WIDTH(2)
aresetn_i, ) u_bresp_dffer (
s_wr_fsm_q == WR_WAIT && ribp.ready, .clk_i (aclk_i),
s_bresp_d, .rst_n_i(aresetn_i),
s_bresp_q .en_i (s_wr_fsm_q == WR_WAIT && ribp.ready),
.dat_i (s_bresp_d),
.dat_o (s_bresp_q)
); );
// axil // axil
rtl/ip/ribp/interconnect/ribp2ribp.sv
+28 -20
View File
@@ -47,35 +47,43 @@ module ribp2ribp (
assign slvr_wdata_o = ~s_req_empty_q ? s_req_rdata_q[35:4] : '0; assign slvr_wdata_o = ~s_req_empty_q ? s_req_rdata_q[35:4] : '0;
assign slvr_wstrb_o = ~s_req_empty_q ? s_req_rdata_q[3:0] : '0; assign slvr_wstrb_o = ~s_req_empty_q ? s_req_rdata_q[3:0] : '0;
edge_det_sync_re #(1) u_mstr_valid_det_sync_re ( edge_det_sync_re #(
mstr_clk_i, .DATA_WIDTH(1)
mstr_rst_n_i, ) u_mstr_valid_det_sync_re (
mstr_valid_i, .clk_i (mstr_clk_i),
s_mstr_valid_re .rst_n_i(mstr_rst_n_i),
.dat_i (mstr_valid_i),
.re_o (s_mstr_valid_re)
); );
assign s_req_rdata_d = s_req_rdata; assign s_req_rdata_d = s_req_rdata;
dffr #(69) u_req_rdata_dffr ( dffr #(
slvr_clk_i, .DATA_WIDTH(69)
slvr_rst_n_i, ) u_req_rdata_dffr (
s_req_rdata_d, .clk_i (slvr_clk_i),
s_req_rdata_q .rst_n_i(slvr_rst_n_i),
.dat_i (s_req_rdata_d),
.dat_o (s_req_rdata_q)
); );
assign s_req_empty_d = s_req_empty; assign s_req_empty_d = s_req_empty;
dffr #(1) u_req_empty_dffr ( dffr #(
slvr_clk_i, .DATA_WIDTH(1)
slvr_rst_n_i, ) u_req_empty_dffr (
s_req_empty_d, .clk_i (slvr_clk_i),
s_req_empty_q .rst_n_i(slvr_rst_n_i),
.dat_i (s_req_empty_d),
.dat_o (s_req_empty_q)
); );
assign s_resp_empty_d = s_resp_empty; assign s_resp_empty_d = s_resp_empty;
dffr #(1) u_resp_empty_dffr ( dffr #(
mstr_clk_i, .DATA_WIDTH(1)
mstr_rst_n_i, ) u_resp_empty_dffr (
s_resp_empty_d, .clk_i (mstr_clk_i),
s_resp_empty_q .rst_n_i(mstr_rst_n_i),
.dat_i (s_resp_empty_d),
.dat_o (s_resp_empty_q)
); );
// req frame: valid[1] addr[32], wdata[32], wstrb[4] // req frame: valid[1] addr[32], wdata[32], wstrb[4]
rtl/ip/ribp/interconnect/ribp_regslice.sv
+56 -40
View File
@@ -88,63 +88,79 @@ module ribp_regslice (
end end
endcase endcase
end end
dffr #(2) u_fsm_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_fsm_dffr (
s_fsm_d, .clk_i (clk_i),
s_fsm_q .rst_n_i(rst_n_i),
.dat_i (s_fsm_d),
.dat_o (s_fsm_q)
); );
dffr #(1) u_ribp_mstr_valid_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_mstr_valid_dffr (
s_ribp_mst_valid_d, .clk_i (clk_i),
s_ribp_mst_valid_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_valid_d),
.dat_o (s_ribp_mst_valid_q)
); );
dffr #(32) u_ribp_mst_addr_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_mst_addr_dffr (
s_ribp_mst_addr_d, .clk_i (clk_i),
s_ribp_mst_addr_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_addr_d),
.dat_o (s_ribp_mst_addr_q)
); );
dffr #(32) u_ribp_mst_wdata_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_mst_wdata_dffr (
s_ribp_mst_wdata_d, .clk_i (clk_i),
s_ribp_mst_wdata_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_wdata_d),
.dat_o (s_ribp_mst_wdata_q)
); );
dffr #(4) u_ribp_mst_wstrb_dffr ( dffr #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_ribp_mst_wstrb_dffr (
s_ribp_mst_wstrb_d, .clk_i (clk_i),
s_ribp_mst_wstrb_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_wstrb_d),
.dat_o (s_ribp_mst_wstrb_q)
); );
dffr #(32) u_ribp_mst_rdata_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_mst_rdata_dffr (
s_ribp_mst_rdata_d, .clk_i (clk_i),
s_ribp_mst_rdata_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_rdata_d),
.dat_o (s_ribp_mst_rdata_q)
); );
dffr #(1) u_ribp_mst_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_mst_ready_dffr (
s_ribp_mst_ready_d, .clk_i (clk_i),
s_ribp_mst_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_ready_d),
.dat_o (s_ribp_mst_ready_q)
); );
dffr #(1) u_ribp_mst_resp_err_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_mst_resp_err_dffr (
s_ribp_mst_resp_err_d, .clk_i (clk_i),
s_ribp_mst_resp_err_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_mst_resp_err_d),
.dat_o (s_ribp_mst_resp_err_q)
); );
endmodule endmodule
rtl/ip/ribp/memory/opipsram.sv
+5 -2
View File
@@ -41,8 +41,11 @@ module ribp_opipsram (
// verilog_format: on // verilog_format: on
); );
wire dummy0 = clk_i; logic dummy0;
wire dummy1 = rst_n_i; logic dummy1;
assign dummy0 = clk_i;
assign dummy1 = rst_n_i;
// ribp // ribp
assign ribp.rdata = '0; assign ribp.rdata = '0;
rtl/ip/ribp/memory/psram.sv
+12 -5
View File
@@ -164,11 +164,13 @@ module ribp_psram (
end end
end end
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re ( edge_det_sync_re #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_mem_valid_edge_det_sync_re (
ribp.valid, .clk_i (clk_i),
s_mem_valid_re .rst_n_i(rst_n_i),
.dat_i (ribp.valid),
.re_o (s_mem_valid_re)
); );
always_ff @(posedge clk_i, negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
@@ -216,6 +218,11 @@ module ribp_psram (
r_rd_st <= 1'b0; r_rd_st <= 1'b0;
if (s_mem_ready) r_fsm_state <= FSM_IDLE; if (s_mem_ready) r_fsm_state <= FSM_IDLE;
end end
default: begin
r_fsm_state <= FSM_IDLE;
r_rd_st <= 1'b0;
r_wr_st <= 1'b0;
end
endcase endcase
end end
end end
rtl/ip/ribp/memory/psram_core.sv
+5
View File
@@ -309,6 +309,11 @@ module psram_core (
r_cfg_chd <= r_cfg_chd + 1'b1; r_cfg_chd <= r_cfg_chd + 1'b1;
end end
end end
default: begin
r_fsm_state <= FSM_INIT;
psram_sclk_o <= 1'b0;
psram_ce_o <= 1'b1;
end
endcase endcase
end end
end end
rtl/ip/ribp/memory/sdram_clkgen.sv
+14 -10
View File
@@ -26,20 +26,24 @@ module sdram_clkgen (
assign sec_edge_o = s_div_clk_q & (s_div_cnt_q == div_i); assign sec_edge_o = s_div_clk_q & (s_div_cnt_q == div_i);
assign s_div_cnt_d = s_div_cnt_q == div_i ? '0 : s_div_cnt_q + 2'd1; assign s_div_cnt_d = s_div_cnt_q == div_i ? '0 : s_div_cnt_q + 2'd1;
dffr #(2) u_div_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_div_cnt_dffr (
s_div_cnt_d, .clk_i (clk_i),
s_div_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_div_cnt_d),
.dat_o (s_div_cnt_q)
); );
assign s_div_clk_d = s_div_cnt_q == div_i ? ~s_div_clk_q : s_div_clk_q; assign s_div_clk_d = s_div_cnt_q == div_i ? ~s_div_clk_q : s_div_clk_q;
dffr #(1) u_div_clk_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_div_clk_dffr (
s_div_clk_d, .clk_i (clk_i),
s_div_clk_q .rst_n_i(rst_n_i),
.dat_i (s_div_clk_d),
.dat_o (s_div_clk_q)
); );
endmodule endmodule
rtl/ip/ribp/memory/sdram_reg.sv
+23 -17
View File
@@ -47,22 +47,26 @@ module sdram_reg (
assign s_sdram_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SDRAM_CLKDIV; assign s_sdram_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = ribp.wdata[1:0]; assign s_sdram_clkdiv_d = ribp.wdata[1:0];
dffer #(2) u_sdram_clkdiv_dffer ( dffer #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_sdram_clkdiv_dffer (
s_sdram_clkdiv_en, .clk_i (clk_i),
s_sdram_clkdiv_d, .rst_n_i(rst_n_i),
s_sdram_clkdiv_q .en_i (s_sdram_clkdiv_en),
.dat_i (s_sdram_clkdiv_d),
.dat_o (s_sdram_clkdiv_q)
); );
// ribp resp // ribp resp
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
@@ -74,12 +78,14 @@ module sdram_reg (
default: s_ribp_rdata_d = s_ribp_rdata_q; default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase endcase
end end
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
endmodule endmodule
rtl/ip/ribp/multimedia/dvp.sv
+36 -26
View File
@@ -46,7 +46,7 @@ module ribp_dvp (
// register // register
logic s_dvp_recven_en; logic s_dvp_recven_en;
logic s_dvp_recven_d, s_dvp_recven_q; logic s_dvp_recven_d, s_dvp_recven_q;
logic s_dvp_status_d, s_dvp_status_q; logic s_dvp_stat_d, s_dvp_stat_q;
logic s_dvp_stream_en; logic s_dvp_stream_en;
logic s_dvp_stream_d, s_dvp_stream_q; logic s_dvp_stream_d, s_dvp_stream_q;
// dvp clk // dvp clk
@@ -69,17 +69,21 @@ module ribp_dvp (
assign s_dvp_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DVP_RECVEN; assign s_dvp_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DVP_RECVEN;
assign s_dvp_recven_d = ribp.wdata[0]; assign s_dvp_recven_d = ribp.wdata[0];
dffer #(1) u_dvp_recven_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_dvp_recven_dffer (
s_dvp_recven_en, .clk_i (clk_i),
s_dvp_recven_d, .rst_n_i(rst_n_i),
s_dvp_recven_q .en_i (s_dvp_recven_en),
.dat_i (s_dvp_recven_d),
.dat_o (s_dvp_recven_q)
); );
assign s_dvp_stream_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DVP_STREAM_CTRL; assign s_dvp_stream_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DVP_STREAM_CTRL;
assign s_dvp_stream_d = ribp.wdata[0]; assign s_dvp_stream_d = ribp.wdata[0];
dffer #(1) u_dvp_stream_dffer ( dffer #(
.DATA_WIDTH(1)
) u_dvp_stream_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dvp_stream_en), .en_i (s_dvp_stream_en),
@@ -87,20 +91,24 @@ module ribp_dvp (
.dat_o (s_dvp_stream_q) .dat_o (s_dvp_stream_q)
); );
assign s_dvp_status_d = s_rx_empty; assign s_dvp_stat_d = s_rx_empty;
dffr #(1) u_dvp_status_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_dvp_status_dffr (
s_dvp_status_d, .clk_i (clk_i),
s_dvp_status_q .rst_n_i(rst_n_i),
.dat_i (s_dvp_stat_d),
.dat_o (s_dvp_stat_q)
); );
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
assign s_ribp_rdata_en = s_ribp_rd_hdshk; assign s_ribp_rdata_en = s_ribp_rd_hdshk;
@@ -116,17 +124,19 @@ module ribp_dvp (
else s_ribp_rdata_d = '0; else s_ribp_rdata_d = '0;
end end
end end
`RIBP_DVP_STATUS: s_ribp_rdata_d = {31'd0, s_dvp_status_q}; `RIBP_DVP_STATUS: s_ribp_rdata_d = {31'd0, s_dvp_stat_q};
`RIBP_DVP_STREAM_CTRL: s_ribp_rdata_d = {31'd0, s_dvp_stream_q}; `RIBP_DVP_STREAM_CTRL: s_ribp_rdata_d = {31'd0, s_dvp_stream_q};
default: s_ribp_rdata_d = s_ribp_rdata_q; default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase endcase
end end
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
assign rx_axis.tdata = s_rx_pop_data; assign rx_axis.tdata = s_rx_pop_data;
rtl/ip/ribp/multimedia/dvp_core.sv
+45 -33
View File
@@ -39,51 +39,61 @@ module dvp_core (
assign rgb_dat_o = s_rgb_data_q; assign rgb_dat_o = s_rgb_data_q;
edge_det_sync_re #(1) u_dvp_vsync_edge_det_sync_re ( edge_det_sync_re #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_dvp_vsync_edge_det_sync_re (
dvp_vsync_i, .clk_i (clk_i),
s_dvp_vsync_re .rst_n_i(rst_n_i),
.dat_i (dvp_vsync_i),
.re_o (s_dvp_vsync_re)
); );
assign s_frame_cnt_en = (s_frame_cnt_q < FRAME_WAIT) && s_dvp_vsync_re; assign s_frame_cnt_en = (s_frame_cnt_q < FRAME_WAIT) && s_dvp_vsync_re;
assign s_frame_cnt_d = s_frame_cnt_q + 4'd1; assign s_frame_cnt_d = s_frame_cnt_q + 4'd1;
dffer #(4) u_frame_cnt_dffer ( dffer #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_frame_cnt_dffer (
s_frame_cnt_en, .clk_i (clk_i),
s_frame_cnt_d, .rst_n_i(rst_n_i),
s_frame_cnt_q .en_i (s_frame_cnt_en),
.dat_i (s_frame_cnt_d),
.dat_o (s_frame_cnt_q)
); );
assign s_frame_valid_en = (s_frame_cnt_q == FRAME_WAIT) && s_dvp_vsync_re; assign s_frame_valid_en = (s_frame_cnt_q == FRAME_WAIT) && s_dvp_vsync_re;
assign s_frame_valid_d = 1'b1; assign s_frame_valid_d = 1'b1;
dffer #(1) u_frame_valid_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_frame_valid_dffer (
s_frame_valid_en, .clk_i (clk_i),
s_frame_valid_d, .rst_n_i(rst_n_i),
s_frame_valid_q .en_i (s_frame_valid_en),
.dat_i (s_frame_valid_d),
.dat_o (s_frame_valid_q)
); );
assign s_pix_cnt_d = dvp_href_i ? s_pix_cnt_q + 2'd1 : '0; assign s_pix_cnt_d = dvp_href_i ? s_pix_cnt_q + 2'd1 : '0;
dffr #(2) u_pix_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_pix_cnt_dffr (
s_pix_cnt_d, .clk_i (clk_i),
s_pix_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_pix_cnt_d),
.dat_o (s_pix_cnt_q)
); );
assign s_rgb_flag_d = s_pix_cnt_q == 2'd3; assign s_rgb_flag_d = s_pix_cnt_q == 2'd3;
dffr #(1) u_rgb_flag_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_rgb_flag_dffr (
s_rgb_flag_d, .clk_i (clk_i),
s_rgb_flag_q .rst_n_i(rst_n_i),
.dat_i (s_rgb_flag_d),
.dat_o (s_rgb_flag_q)
); );
@@ -95,12 +105,14 @@ module dvp_core (
else if (s_pix_cnt_q == 2'd2) s_rgb_data_d[31:24] = dvp_dat_i; else if (s_pix_cnt_q == 2'd2) s_rgb_data_d[31:24] = dvp_dat_i;
else if (s_pix_cnt_q == 2'd3) s_rgb_data_d[23:16] = dvp_dat_i; else if (s_pix_cnt_q == 2'd3) s_rgb_data_d[23:16] = dvp_dat_i;
end end
dffer #(32) u_rgb_data_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_rgb_data_dffer (
s_rgb_data_en, .clk_i (clk_i),
s_rgb_data_d, .rst_n_i(rst_n_i),
s_rgb_data_q .en_i (s_rgb_data_en),
.dat_i (s_rgb_data_d),
.dat_o (s_rgb_data_q)
); );
rtl/ip/ribp/peripheral/clint_core.sv
+3 -1
View File
@@ -46,7 +46,9 @@ module clint_core #(
s_timer_irq_d[hart] = mtime_o >= mtimecmp_i[hart]; s_timer_irq_d[hart] = mtime_o >= mtimecmp_i[hart];
end end
end end
dffr #(HART_NUM) u_timer_irq_dffr ( dffr #(
.DATA_WIDTH(HART_NUM)
) u_timer_irq_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_timer_irq_d), .dat_i (s_timer_irq_d),
rtl/ip/ribp/peripheral/clint_reg.sv
+30 -20
View File
@@ -26,11 +26,11 @@ module clint_reg #(
logic s_req_accept; logic s_req_accept;
logic [15:0] s_offset; logic [15:0] s_offset;
logic s_aligned; logic s_aligned;
logic s_access_error; logic s_access_err;
logic s_msip_select; logic s_msip_sel;
logic s_mtimecmp_select; logic s_mtimecmp_sel;
logic s_mtimecmp_high; logic s_mtimecmp_high;
logic s_mtime_select; logic s_mtime_sel;
logic s_mtime_high; logic s_mtime_high;
logic [11:0] s_msip_hart; logic [11:0] s_msip_hart;
logic [11:0] s_mtimecmp_hart; logic [11:0] s_mtimecmp_hart;
@@ -74,12 +74,12 @@ module clint_reg #(
assign s_msip_hart = s_offset[13:2]; assign s_msip_hart = s_offset[13:2];
assign s_mtimecmp_hart = s_offset[14:3] - 12'h800; assign s_mtimecmp_hart = s_offset[14:3] - 12'h800;
assign s_msip_select = (s_offset < `RIBP_CLINT_MTIMECMP) && (s_msip_hart < HART_COUNT); assign s_msip_sel = (s_offset < `RIBP_CLINT_MTIMECMP) && (s_msip_hart < HART_COUNT);
assign s_mtimecmp_select = (s_offset >= `RIBP_CLINT_MTIMECMP) && assign s_mtimecmp_sel = (s_offset >= `RIBP_CLINT_MTIMECMP) &&
(s_offset < `RIBP_CLINT_MTIME) && (s_offset < `RIBP_CLINT_MTIME) &&
(s_mtimecmp_hart < HART_COUNT); (s_mtimecmp_hart < HART_COUNT);
assign s_mtimecmp_high = s_offset[2]; assign s_mtimecmp_high = s_offset[2];
assign s_mtime_select = (s_offset == `RIBP_CLINT_MTIME) || (s_offset == `RIBP_CLINT_MTIMEH); assign s_mtime_sel = (s_offset == `RIBP_CLINT_MTIME) || (s_offset == `RIBP_CLINT_MTIMEH);
assign s_mtime_high = s_offset == `RIBP_CLINT_MTIMEH; assign s_mtime_high = s_offset == `RIBP_CLINT_MTIMEH;
assign ribp.ready = s_ribp_ready_q; assign ribp.ready = s_ribp_ready_q;
@@ -87,18 +87,18 @@ module clint_reg #(
assign ribp.resp_err = s_ribp_resp_err_q; assign ribp.resp_err = s_ribp_resp_err_q;
always_comb begin always_comb begin
s_access_error = !s_aligned || !(s_msip_select || s_mtimecmp_select || s_mtime_select); s_access_err = !s_aligned || !(s_msip_sel || s_mtimecmp_sel || s_mtime_sel);
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
if (s_aligned) begin if (s_aligned) begin
if (s_msip_select) begin if (s_msip_sel) begin
s_ribp_rdata_d = {31'd0, s_msip_q[s_msip_hart[HART_INDEX_WIDTH-1:0]]}; s_ribp_rdata_d = {31'd0, s_msip_q[s_msip_hart[HART_INDEX_WIDTH-1:0]]};
end else if (s_mtimecmp_select) begin end else if (s_mtimecmp_sel) begin
if (s_mtimecmp_high) begin if (s_mtimecmp_high) begin
s_ribp_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32]; s_ribp_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32];
end else begin end else begin
s_ribp_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0]; s_ribp_rdata_d = s_mtimecmp_q[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][31:0];
end end
end else if (s_mtime_select) begin end else if (s_mtime_sel) begin
s_ribp_rdata_d = s_mtime_high ? mtime_i[63:32] : mtime_i[31:0]; s_ribp_rdata_d = s_mtime_high ? mtime_i[63:32] : mtime_i[31:0];
end end
end end
@@ -107,13 +107,15 @@ module clint_reg #(
always_comb begin always_comb begin
s_msip_en = '0; s_msip_en = '0;
s_msip_d = s_msip_q; s_msip_d = s_msip_q;
if (s_req_accept && s_write && !s_access_error && s_msip_select && ribp.wstrb[0]) begin if (s_req_accept && s_write && !s_access_err && s_msip_sel && ribp.wstrb[0]) begin
s_msip_en[s_msip_hart[HART_INDEX_WIDTH-1:0]] = 1'b1; s_msip_en[s_msip_hart[HART_INDEX_WIDTH-1:0]] = 1'b1;
s_msip_d[s_msip_hart[HART_INDEX_WIDTH-1:0]] = ribp.wdata[0]; s_msip_d[s_msip_hart[HART_INDEX_WIDTH-1:0]] = ribp.wdata[0];
end end
end end
for (genvar hart = 0; hart < HART_NUM; hart++) begin : gen_msip for (genvar hart = 0; hart < HART_NUM; hart++) begin : gen_msip
dffer #(1) u_msip_dffer ( dffer #(
.DATA_WIDTH(1)
) u_msip_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_msip_en[hart]), .en_i (s_msip_en[hart]),
@@ -127,7 +129,7 @@ module clint_reg #(
for (int hart = 0; hart < HART_NUM; hart++) begin for (int hart = 0; hart < HART_NUM; hart++) begin
s_mtimecmp_d[hart] = s_mtimecmp_q[hart]; s_mtimecmp_d[hart] = s_mtimecmp_q[hart];
end end
if (s_req_accept && s_write && !s_access_error && s_mtimecmp_select) begin if (s_req_accept && s_write && !s_access_err && s_mtimecmp_sel) begin
s_mtimecmp_en[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]] = 1'b1; s_mtimecmp_en[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]] = 1'b1;
if (s_mtimecmp_high) begin if (s_mtimecmp_high) begin
s_mtimecmp_d[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32] = merge_wstrb( s_mtimecmp_d[s_mtimecmp_hart[HART_INDEX_WIDTH-1:0]][63:32] = merge_wstrb(
@@ -139,7 +141,9 @@ module clint_reg #(
end end
end end
for (genvar hart = 0; hart < HART_NUM; hart++) begin : gen_mtimecmp for (genvar hart = 0; hart < HART_NUM; hart++) begin : gen_mtimecmp
dfferh #(64) u_mtimecmp_dfferh ( dfferh #(
.DATA_WIDTH(64)
) u_mtimecmp_dfferh (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_mtimecmp_en[hart]), .en_i (s_mtimecmp_en[hart]),
@@ -151,7 +155,7 @@ module clint_reg #(
always_comb begin always_comb begin
mtime_load_o = 1'b0; mtime_load_o = 1'b0;
mtime_load_value_o = mtime_i; mtime_load_value_o = mtime_i;
if (s_req_accept && s_write && !s_access_error && s_mtime_select) begin if (s_req_accept && s_write && !s_access_err && s_mtime_sel) begin
mtime_load_o = 1'b1; mtime_load_o = 1'b1;
if (s_mtime_high) begin if (s_mtime_high) begin
mtime_load_value_o[63:32] = merge_wstrb(mtime_i[63:32], ribp.wdata, ribp.wstrb); mtime_load_value_o[63:32] = merge_wstrb(mtime_i[63:32], ribp.wdata, ribp.wstrb);
@@ -165,22 +169,28 @@ module clint_reg #(
assign mtimecmp_o = s_mtimecmp_q; assign mtimecmp_o = s_mtimecmp_q;
assign s_ribp_ready_d = s_req_accept; assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_error; assign s_ribp_resp_err_d = s_access_err;
dffr #(1) u_ribp_ready_dffr ( dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d), .dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q) .dat_o (s_ribp_ready_q)
); );
dffer #(1) u_ribp_resp_err_dffer ( dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d), .dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q) .dat_o (s_ribp_resp_err_q)
); );
dffer #(32) u_ribp_rdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
rtl/ip/ribp/peripheral/clint_timebase.sv
+3 -1
View File
@@ -51,7 +51,9 @@ module clint_timebase #(
/* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_on PINCONNECTEMPTY */
assign s_tick_toggle_d = s_div_terminal ? ~s_tick_toggle_q : s_tick_toggle_q; assign s_tick_toggle_d = s_div_terminal ? ~s_tick_toggle_q : s_tick_toggle_q;
dffr #(1) u_tick_toggle_dffr ( dffr #(
.DATA_WIDTH(1)
) u_tick_toggle_dffr (
.clk_i (ref_clk_i), .clk_i (ref_clk_i),
.rst_n_i(ref_rst_n_i), .rst_n_i(ref_rst_n_i),
.dat_i (s_tick_toggle_d), .dat_i (s_tick_toggle_d),
rtl/ip/ribp/peripheral/dma.sv
+69 -45
View File
@@ -86,16 +86,16 @@ module ribp_dma (
logic s_dma_dstincr_d, s_dma_dstincr_q; logic s_dma_dstincr_d, s_dma_dstincr_q;
logic s_dma_xferlen_en; logic s_dma_xferlen_en;
logic [31:0] s_dma_xferlen_d, s_dma_xferlen_q; logic [31:0] s_dma_xferlen_d, s_dma_xferlen_q;
logic s_dma_status_d, s_dma_status_q; logic s_dma_stat_d, s_dma_stat_q;
logic s_dma_error_status_d, s_dma_error_status_q; logic s_dma_err_stat_d, s_dma_err_stat_q;
logic [2:0] s_dma_error_code_d, s_dma_error_code_q; logic [2:0] s_dma_err_code_d, s_dma_err_code_q;
logic [31:0] s_dma_error_addr_d, s_dma_error_addr_q; logic [31:0] s_dma_err_addr_d, s_dma_err_addr_q;
// common // common
logic s_xfer_start, s_xfer_stop, s_xfer_reset, s_xfer_done; logic s_xfer_start, s_xfer_stop, s_xfer_reset, s_xfer_done;
logic [ 1:0] s_xfer_fsm; logic [ 1:0] s_xfer_fsm;
logic s_xfer_error; logic s_xfer_err;
logic [ 2:0] s_xfer_error_code; logic [ 2:0] s_xfer_err_code;
logic [31:0] s_xfer_error_addr; logic [31:0] s_xfer_err_addr;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb); assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
@@ -104,12 +104,14 @@ module ribp_dma (
assign ribp.resp_err = 1'b0; assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q; assign ribp.rdata = s_ribp_rdata_q;
assign dma_xfer_done_o = s_dma_status_q; assign dma_xfer_done_o = s_dma_stat_q;
assign s_dma_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_MODE; assign s_dma_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_MODE;
assign s_dma_mode_d = ribp.wdata[3:0]; assign s_dma_mode_d = ribp.wdata[3:0];
dffer #(4) u_dma_mode_dffer ( dffer #(
.DATA_WIDTH(4)
) u_dma_mode_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_mode_en), .en_i (s_dma_mode_en),
@@ -126,7 +128,9 @@ module ribp_dma (
if (ribp.wstrb[2]) s_dma_srcaddr_d[23:16] = ribp.wdata[23:16]; if (ribp.wstrb[2]) s_dma_srcaddr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_srcaddr_d[31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_dma_srcaddr_d[31:24] = ribp.wdata[31:24];
end end
dffer #(32) u_dma_srcaddr_dffer ( dffer #(
.DATA_WIDTH(32)
) u_dma_srcaddr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_srcaddr_en), .en_i (s_dma_srcaddr_en),
@@ -137,7 +141,9 @@ module ribp_dma (
assign s_dma_srcincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_SRCINCR; assign s_dma_srcincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_SRCINCR;
assign s_dma_srcincr_d = ribp.wdata[0]; assign s_dma_srcincr_d = ribp.wdata[0];
dffer #(1) u_dma_srcincr_dffer ( dffer #(
.DATA_WIDTH(1)
) u_dma_srcincr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_srcincr_en), .en_i (s_dma_srcincr_en),
@@ -154,7 +160,9 @@ module ribp_dma (
if (ribp.wstrb[2]) s_dma_dstaddr_d[23:16] = ribp.wdata[23:16]; if (ribp.wstrb[2]) s_dma_dstaddr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_dstaddr_d[31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_dma_dstaddr_d[31:24] = ribp.wdata[31:24];
end end
dffer #(32) u_dma_dstaddr_dffer ( dffer #(
.DATA_WIDTH(32)
) u_dma_dstaddr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_dstaddr_en), .en_i (s_dma_dstaddr_en),
@@ -164,7 +172,9 @@ module ribp_dma (
assign s_dma_dstincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_DSTINCR; assign s_dma_dstincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_DSTINCR;
assign s_dma_dstincr_d = ribp.wdata[0]; assign s_dma_dstincr_d = ribp.wdata[0];
dffer #(1) u_dma_dstincr_dffer ( dffer #(
.DATA_WIDTH(1)
) u_dma_dstincr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_dstincr_en), .en_i (s_dma_dstincr_en),
@@ -180,7 +190,9 @@ module ribp_dma (
if (ribp.wstrb[2]) s_dma_xferlen_d[23:16] = ribp.wdata[23:16]; if (ribp.wstrb[2]) s_dma_xferlen_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_xferlen_d[31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_dma_xferlen_d[31:24] = ribp.wdata[31:24];
end end
dffer #(32) u_dma_xferlen_dffer ( dffer #(
.DATA_WIDTH(32)
) u_dma_xferlen_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_xferlen_en), .en_i (s_dma_xferlen_en),
@@ -195,55 +207,65 @@ module ribp_dma (
always_comb begin always_comb begin
s_dma_status_d = s_dma_status_q; s_dma_stat_d = s_dma_stat_q;
if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_DMA_STATUS) begin if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_DMA_STATUS) begin
s_dma_status_d = '0; s_dma_stat_d = '0;
end else if (s_xfer_done) begin end else if (s_xfer_done) begin
s_dma_status_d = 1'b1; s_dma_stat_d = 1'b1;
end end
end end
dffr #(1) u_dma_status_dffr ( dffr #(
.DATA_WIDTH(1)
) u_dma_status_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_dma_status_d), .dat_i (s_dma_stat_d),
.dat_o (s_dma_status_q) .dat_o (s_dma_stat_q)
); );
always_comb begin always_comb begin
s_dma_error_status_d = s_dma_error_status_q; s_dma_err_stat_d = s_dma_err_stat_q;
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_ERROR_STATUS && ribp.wstrb[0] && if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_ERROR_STATUS && ribp.wstrb[0] &&
ribp.wdata[0]) begin ribp.wdata[0]) begin
s_dma_error_status_d = 1'b0; s_dma_err_stat_d = 1'b0;
end else if (s_xfer_error) begin end else if (s_xfer_err) begin
s_dma_error_status_d = 1'b1; s_dma_err_stat_d = 1'b1;
end end
end end
dffr #(1) u_dma_error_status_dffr ( dffr #(
.DATA_WIDTH(1)
) u_dma_error_status_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_dma_error_status_d), .dat_i (s_dma_err_stat_d),
.dat_o (s_dma_error_status_q) .dat_o (s_dma_err_stat_q)
); );
assign s_dma_error_code_d = s_xfer_error_code; assign s_dma_err_code_d = s_xfer_err_code;
dffer #(3) u_dma_error_code_dffer ( dffer #(
.DATA_WIDTH(3)
) u_dma_error_code_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_xfer_error), .en_i (s_xfer_err),
.dat_i (s_dma_error_code_d), .dat_i (s_dma_err_code_d),
.dat_o (s_dma_error_code_q) .dat_o (s_dma_err_code_q)
); );
assign s_dma_error_addr_d = s_xfer_error_addr; assign s_dma_err_addr_d = s_xfer_err_addr;
dffer #(32) u_dma_error_addr_dffer ( dffer #(
.DATA_WIDTH(32)
) u_dma_error_addr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_xfer_error), .en_i (s_xfer_err),
.dat_i (s_dma_error_addr_d), .dat_i (s_dma_err_addr_d),
.dat_o (s_dma_error_addr_q) .dat_o (s_dma_err_addr_q)
); );
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d), .dat_i (s_ribp_ready_d),
@@ -260,14 +282,16 @@ module ribp_dma (
`RIBP_DMA_DSTADDR: s_ribp_rdata_d = s_dma_dstaddr_q; `RIBP_DMA_DSTADDR: s_ribp_rdata_d = s_dma_dstaddr_q;
`RIBP_DMA_DSTINCR: s_ribp_rdata_d = {31'd0, s_dma_dstincr_q}; `RIBP_DMA_DSTINCR: s_ribp_rdata_d = {31'd0, s_dma_dstincr_q};
`RIBP_DMA_XFERLEN: s_ribp_rdata_d = s_dma_xferlen_q; `RIBP_DMA_XFERLEN: s_ribp_rdata_d = s_dma_xferlen_q;
`RIBP_DMA_STATUS: s_ribp_rdata_d = {31'd0, s_dma_status_q}; `RIBP_DMA_STATUS: s_ribp_rdata_d = {31'd0, s_dma_stat_q};
`RIBP_DMA_FSM: s_ribp_rdata_d = {30'd0, s_xfer_fsm}; `RIBP_DMA_FSM: s_ribp_rdata_d = {30'd0, s_xfer_fsm};
`RIBP_DMA_ERROR_STATUS: s_ribp_rdata_d = {28'd0, s_dma_error_code_q, s_dma_error_status_q}; `RIBP_DMA_ERROR_STATUS: s_ribp_rdata_d = {28'd0, s_dma_err_code_q, s_dma_err_stat_q};
`RIBP_DMA_ERROR_ADDR: s_ribp_rdata_d = s_dma_error_addr_q; `RIBP_DMA_ERROR_ADDR: s_ribp_rdata_d = s_dma_err_addr_q;
default: s_ribp_rdata_d = s_ribp_rdata_q; default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase endcase
end end
dffer #(32) u_ribp_rdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_ribp_rdata_en), .en_i (s_ribp_rdata_en),
@@ -289,9 +313,9 @@ module ribp_dma (
.stop_i (s_xfer_stop), .stop_i (s_xfer_stop),
.reset_i (s_xfer_reset), .reset_i (s_xfer_reset),
.done_o (s_xfer_done), .done_o (s_xfer_done),
.error_o (s_xfer_error), .error_o (s_xfer_err),
.error_code_o(s_xfer_error_code), .error_code_o(s_xfer_err_code),
.error_addr_o(s_xfer_error_addr), .error_addr_o(s_xfer_err_addr),
.fsm_o (s_xfer_fsm), .fsm_o (s_xfer_fsm),
.hw_trg (hw_trg), .hw_trg (hw_trg),
.rib (rib), .rib (rib),
rtl/ip/ribp/peripheral/dma_core.sv
+21 -9
View File
@@ -75,7 +75,7 @@ module dma_core (
logic s_fifo_full, s_fifo_empty; logic s_fifo_full, s_fifo_empty;
logic [ 2:0] s_fifo_count; logic [ 2:0] s_fifo_count;
logic [31:0] s_fifo_rdata; logic [31:0] s_fifo_rdata;
logic s_rsp_error; logic s_rsp_err;
logic s_i2s_tx_stream; logic s_i2s_tx_stream;
logic s_i2s_rx_stream; logic s_i2s_rx_stream;
logic s_dvp_rx_stream; logic s_dvp_rx_stream;
@@ -158,9 +158,9 @@ module dma_core (
assign s_cmd_hdshk = rib.cmd_valid && rib.cmd_ready; assign s_cmd_hdshk = rib.cmd_valid && rib.cmd_ready;
assign s_rsp_hdshk = rib.rsp_valid && rib.rsp_ready; assign s_rsp_hdshk = rib.rsp_valid && rib.rsp_ready;
assign s_w_hdshk = rib.w_valid && rib.w_ready; assign s_w_hdshk = rib.w_valid && rib.w_ready;
assign s_rsp_error = s_rsp_hdshk && rib.resp_err; assign s_rsp_err = s_rsp_hdshk && rib.resp_err;
assign s_fifo_flush = reset_i || start_i || s_rsp_error; assign s_fifo_flush = reset_i || start_i || s_rsp_err;
assign s_fifo_push = (s_i2s_rx_stream || s_dvp_rx_stream) ? s_stream_rx_hdshk : assign s_fifo_push = (s_i2s_rx_stream || s_dvp_rx_stream) ? s_stream_rx_hdshk :
((s_fsm_q == FSM_RD_RESP) && s_rsp_hdshk && ~rib.resp_err); ((s_fsm_q == FSM_RD_RESP) && s_rsp_hdshk && ~rib.resp_err);
assign s_fifo_pop = s_i2s_tx_stream ? s_stream_tx_hdshk : ((s_fsm_q == FSM_WR_DATA) && s_w_hdshk); assign s_fifo_pop = s_i2s_tx_stream ? s_stream_tx_hdshk : ((s_fsm_q == FSM_WR_DATA) && s_w_hdshk);
@@ -281,31 +281,41 @@ module dma_core (
end end
end end
dffr #(3) u_fsm_dffr ( dffr #(
.DATA_WIDTH(3)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_xfer_cnt_dffr ( dffr #(
.DATA_WIDTH(32)
) u_xfer_cnt_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_xfer_cnt_d), .dat_i (s_xfer_cnt_d),
.dat_o (s_xfer_cnt_q) .dat_o (s_xfer_cnt_q)
); );
dffr #(32) u_src_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_src_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_src_addr_d), .dat_i (s_src_addr_d),
.dat_o (s_src_addr_q) .dat_o (s_src_addr_q)
); );
dffr #(32) u_dst_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_dst_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_dst_addr_d), .dat_i (s_dst_addr_d),
.dat_o (s_dst_addr_q) .dat_o (s_dst_addr_q)
); );
dffr #(2) u_wr_beat_dffr ( dffr #(
.DATA_WIDTH(2)
) u_wr_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wr_beat_d), .dat_i (s_wr_beat_d),
@@ -317,7 +327,9 @@ module dma_core (
if (stop_i) s_ctrl_stop_d = ~s_ctrl_stop_q; if (stop_i) s_ctrl_stop_d = ~s_ctrl_stop_q;
if (reset_i) s_ctrl_stop_d = 1'b0; if (reset_i) s_ctrl_stop_d = 1'b0;
end end
dffr #(1) u_ctrl_stop_dffr ( dffr #(
.DATA_WIDTH(1)
) u_ctrl_stop_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_ctrl_stop_d), .dat_i (s_ctrl_stop_d),
rtl/ip/ribp/peripheral/gpio_core.sv
+6 -2
View File
@@ -95,14 +95,18 @@ module gpio_core #(
end end
end end
dffr #(PIN_NUM) u_input_filtered_dffr ( dffr #(
.DATA_WIDTH(PIN_NUM)
) u_input_filtered_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_input_filtered_d), .dat_i (s_input_filtered_d),
.dat_o (s_input_filtered_q) .dat_o (s_input_filtered_q)
); );
for (genvar pin = 0; pin < PIN_NUM; pin++) begin : gen_stable_count for (genvar pin = 0; pin < PIN_NUM; pin++) begin : gen_stable_count
dffr #(4) u_stable_count_dffr ( dffr #(
.DATA_WIDTH(4)
) u_stable_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_stable_count_d[pin]), .dat_i (s_stable_count_d[pin]),
rtl/ip/ribp/peripheral/gpio_reg.sv
+213 -164
View File
@@ -49,20 +49,20 @@ module gpio_reg #(
logic [ 31:0] s_byte_mask; logic [ 31:0] s_byte_mask;
logic [ 31:0] s_write_word; logic [ 31:0] s_write_word;
logic [PIN_NUM-1:0] s_write_bits; logic [PIN_NUM-1:0] s_write_bits;
logic s_access_error; logic s_access_err;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q; logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_ribp_ready_q; logic s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q; logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [PIN_NUM-1:0] s_data_out_d, s_data_out_q; logic [PIN_NUM-1:0] s_data_out_d, s_data_out_q;
logic [PIN_NUM-1:0] s_output_enable_d, s_output_enable_q; logic [PIN_NUM-1:0] s_output_en_d, s_output_en_q;
logic [PIN_NUM-1:0] s_open_drain_d, s_open_drain_q; logic [PIN_NUM-1:0] s_open_drain_d, s_open_drain_q;
logic [PIN_NUM-1:0] s_input_cmos_d, s_input_cmos_q; logic [PIN_NUM-1:0] s_input_cmos_d, s_input_cmos_q;
logic [PIN_NUM-1:0] s_pull_up_d, s_pull_up_q; logic [PIN_NUM-1:0] s_pull_up_d, s_pull_up_q;
logic [PIN_NUM-1:0] s_pull_down_d, s_pull_down_q; logic [PIN_NUM-1:0] s_pull_down_d, s_pull_down_q;
logic [PIN_NUM-1:0] s_alt_enable_d, s_alt_enable_q; logic [PIN_NUM-1:0] s_alt_en_d, s_alt_en_q;
logic [PIN_NUM-1:0] s_alt_select_d, s_alt_select_q; logic [PIN_NUM-1:0] s_alt_sel_d, s_alt_sel_q;
logic [PIN_NUM-1:0] s_user_select_d, s_user_select_q; logic [PIN_NUM-1:0] s_user_sel_d, s_user_sel_q;
logic [PIN_NUM-1:0] s_user_lock_d, s_user_lock_q; logic [PIN_NUM-1:0] s_user_lock_d, s_user_lock_q;
logic [PIN_NUM-1:0] s_user_handoff_d, s_user_handoff_q; logic [PIN_NUM-1:0] s_user_handoff_d, s_user_handoff_q;
logic [PIN_NUM-1:0] s_user_access_d, s_user_access_q; logic [PIN_NUM-1:0] s_user_access_d, s_user_access_q;
@@ -70,18 +70,18 @@ module gpio_reg #(
logic [PIN_NUM-1:0] s_intr_fall_d, s_intr_fall_q; logic [PIN_NUM-1:0] s_intr_fall_d, s_intr_fall_q;
logic [PIN_NUM-1:0] s_intr_high_d, s_intr_high_q; logic [PIN_NUM-1:0] s_intr_high_d, s_intr_high_q;
logic [PIN_NUM-1:0] s_intr_low_d, s_intr_low_q; logic [PIN_NUM-1:0] s_intr_low_d, s_intr_low_q;
logic [PIN_NUM-1:0] s_intr_enable_d, s_intr_enable_q; logic [PIN_NUM-1:0] s_intr_en_d, s_intr_en_q;
logic [PIN_NUM-1:0] s_intr_state_d, s_intr_state_q; logic [PIN_NUM-1:0] s_intr_state_d, s_intr_state_q;
logic [PIN_NUM-1:0] s_filter_enable_d, s_filter_enable_q; logic [PIN_NUM-1:0] s_filter_en_d, s_filter_en_q;
logic [PIN_NUM-1:0] s_config_lock_d, s_config_lock_q; logic [PIN_NUM-1:0] s_config_lock_d, s_config_lock_q;
logic [15:0] s_filter_div_d, s_filter_div_q; logic [15:0] s_filter_div_d, s_filter_div_q;
logic [3:0] s_filter_count_d, s_filter_count_q; logic [3:0] s_filter_count_d, s_filter_count_q;
logic s_data_out_en, s_output_enable_en, s_open_drain_en, s_input_cmos_en; logic s_data_out_en, s_output_en_en, s_open_drain_en, s_input_cmos_en;
logic s_pull_up_en, s_pull_down_en, s_alt_enable_en, s_alt_select_en; logic s_pull_up_en, s_pull_down_en, s_alt_en_en, s_alt_sel_en;
logic s_user_select_en, s_user_lock_en, s_user_access_en; logic s_user_sel_en, s_user_lock_en, s_user_access_en;
logic s_intr_rise_en, s_intr_fall_en, s_intr_high_en, s_intr_low_en; logic s_intr_rise_en, s_intr_fall_en, s_intr_high_en, s_intr_low_en;
logic s_intr_enable_en, s_intr_state_en, s_filter_enable_en, s_config_lock_en; logic s_intr_en_en, s_intr_state_en, s_filter_en_en, s_config_lock_en;
logic s_filter_div_en, s_filter_count_en; logic s_filter_div_en, s_filter_count_en;
logic [PIN_NUM-1:0] s_intr_clear, s_intr_test; logic [PIN_NUM-1:0] s_intr_clear, s_intr_test;
@@ -153,56 +153,56 @@ module gpio_reg #(
assign ribp.ready = s_ribp_ready_q; assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q; assign ribp.rdata = s_ribp_rdata_q;
assign ribp.resp_err = s_ribp_resp_err_q; assign ribp.resp_err = s_ribp_resp_err_q;
assign irq_o = |(s_intr_state_q & s_intr_enable_q); assign irq_o = |(s_intr_state_q & s_intr_en_q);
always_comb begin always_comb begin
s_access_error = !s_aligned || !(s_public_window || s_admin_window); s_access_err = !s_aligned || !(s_public_window || s_admin_window);
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
s_data_out_en = 1'b0; s_data_out_en = 1'b0;
s_output_enable_en = 1'b0; s_output_en_en = 1'b0;
s_open_drain_en = 1'b0; s_open_drain_en = 1'b0;
s_input_cmos_en = 1'b0; s_input_cmos_en = 1'b0;
s_pull_up_en = 1'b0; s_pull_up_en = 1'b0;
s_pull_down_en = 1'b0; s_pull_down_en = 1'b0;
s_alt_enable_en = 1'b0; s_alt_en_en = 1'b0;
s_alt_select_en = 1'b0; s_alt_sel_en = 1'b0;
s_user_select_en = 1'b0; s_user_sel_en = 1'b0;
s_user_lock_en = 1'b0; s_user_lock_en = 1'b0;
s_user_access_en = 1'b0; s_user_access_en = 1'b0;
s_intr_rise_en = 1'b0; s_intr_rise_en = 1'b0;
s_intr_fall_en = 1'b0; s_intr_fall_en = 1'b0;
s_intr_high_en = 1'b0; s_intr_high_en = 1'b0;
s_intr_low_en = 1'b0; s_intr_low_en = 1'b0;
s_intr_enable_en = 1'b0; s_intr_en_en = 1'b0;
s_filter_enable_en = 1'b0; s_filter_en_en = 1'b0;
s_config_lock_en = 1'b0; s_config_lock_en = 1'b0;
s_filter_div_en = 1'b0; s_filter_div_en = 1'b0;
s_filter_count_en = 1'b0; s_filter_count_en = 1'b0;
s_intr_clear = '0; s_intr_clear = '0;
s_intr_test = '0; s_intr_test = '0;
s_data_out_d = s_data_out_q; s_data_out_d = s_data_out_q;
s_output_enable_d = s_output_enable_q; s_output_en_d = s_output_en_q;
s_open_drain_d = s_open_drain_q; s_open_drain_d = s_open_drain_q;
s_input_cmos_d = s_input_cmos_q; s_input_cmos_d = s_input_cmos_q;
s_pull_up_d = s_pull_up_q; s_pull_up_d = s_pull_up_q;
s_pull_down_d = s_pull_down_q; s_pull_down_d = s_pull_down_q;
s_alt_enable_d = s_alt_enable_q; s_alt_en_d = s_alt_en_q;
s_alt_select_d = s_alt_select_q; s_alt_sel_d = s_alt_sel_q;
s_user_select_d = s_user_select_q; s_user_sel_d = s_user_sel_q;
s_user_lock_d = s_user_lock_q; s_user_lock_d = s_user_lock_q;
s_user_access_d = s_user_access_q; s_user_access_d = s_user_access_q;
s_intr_rise_d = s_intr_rise_q; s_intr_rise_d = s_intr_rise_q;
s_intr_fall_d = s_intr_fall_q; s_intr_fall_d = s_intr_fall_q;
s_intr_high_d = s_intr_high_q; s_intr_high_d = s_intr_high_q;
s_intr_low_d = s_intr_low_q; s_intr_low_d = s_intr_low_q;
s_intr_enable_d = s_intr_enable_q; s_intr_en_d = s_intr_en_q;
s_filter_enable_d = s_filter_enable_q; s_filter_en_d = s_filter_en_q;
s_config_lock_d = s_config_lock_q; s_config_lock_d = s_config_lock_q;
s_filter_div_d = s_filter_div_q; s_filter_div_d = s_filter_div_q;
s_filter_count_d = s_filter_count_q; s_filter_count_d = s_filter_count_q;
if (s_req && !s_access_error) begin if (s_req && !s_access_err) begin
if (s_public_window) begin if (s_public_window) begin
if (s_write) begin if (s_write) begin
unique case (s_offset) unique case (s_offset)
@@ -227,19 +227,19 @@ module gpio_reg #(
s_intr_clear = s_write_bits & s_user_access_q; s_intr_clear = s_write_bits & s_user_access_q;
end end
`RIBP_GPIO_USER_INTR_ENABLE: begin `RIBP_GPIO_USER_INTR_ENABLE: begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = (s_intr_enable_q & ~s_user_access_q) | s_intr_en_d = (s_intr_en_q & ~s_user_access_q) |
(merge_pins(s_intr_enable_q, ribp.wdata, ribp.wstrb) & s_user_access_q); (merge_pins(s_intr_en_q, ribp.wdata, ribp.wstrb) & s_user_access_q);
end end
`RIBP_GPIO_USER_INTR_ENABLE_SET: begin `RIBP_GPIO_USER_INTR_ENABLE_SET: begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = s_intr_enable_q | (s_write_bits & s_user_access_q); s_intr_en_d = s_intr_en_q | (s_write_bits & s_user_access_q);
end end
`RIBP_GPIO_USER_INTR_ENABLE_CLEAR: begin `RIBP_GPIO_USER_INTR_ENABLE_CLEAR: begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = s_intr_enable_q & ~(s_write_bits & s_user_access_q); s_intr_en_d = s_intr_en_q & ~(s_write_bits & s_user_access_q);
end end
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end else begin end else begin
unique case (s_offset) unique case (s_offset)
@@ -248,12 +248,12 @@ module gpio_reg #(
`RIBP_GPIO_USER_INTR_STATE: `RIBP_GPIO_USER_INTR_STATE:
s_ribp_rdata_d = extend_pins(s_intr_state_q & s_user_access_q); s_ribp_rdata_d = extend_pins(s_intr_state_q & s_user_access_q);
`RIBP_GPIO_USER_INTR_STATUS: `RIBP_GPIO_USER_INTR_STATUS:
s_ribp_rdata_d = extend_pins(s_intr_state_q & s_intr_enable_q & s_user_access_q); s_ribp_rdata_d = extend_pins(s_intr_state_q & s_intr_en_q & s_user_access_q);
`RIBP_GPIO_USER_INTR_ENABLE: `RIBP_GPIO_USER_INTR_ENABLE:
s_ribp_rdata_d = extend_pins(s_intr_enable_q & s_user_access_q); s_ribp_rdata_d = extend_pins(s_intr_en_q & s_user_access_q);
`RIBP_GPIO_IP_VERSION: s_ribp_rdata_d = IP_VERSION; `RIBP_GPIO_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_GPIO_CAPABILITY: s_ribp_rdata_d = CAPABILITY; `RIBP_GPIO_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end end
end else if (s_write) begin end else if (s_write) begin
@@ -279,58 +279,58 @@ module gpio_reg #(
`RIBP_GPIO_ADMIN_OE_CLEAR, `RIBP_GPIO_ADMIN_OE_CLEAR,
`RIBP_GPIO_ADMIN_OE_TOGGLE: begin `RIBP_GPIO_ADMIN_OE_TOGGLE: begin
if (s_offset == `RIBP_GPIO_ADMIN_OUTPUT_ENABLE) begin if (s_offset == `RIBP_GPIO_ADMIN_OUTPUT_ENABLE) begin
s_output_enable_d = merge_pins(s_output_enable_q, ribp.wdata, ribp.wstrb); s_output_en_d = merge_pins(s_output_en_q, ribp.wdata, ribp.wstrb);
end else if (s_offset == `RIBP_GPIO_ADMIN_OE_SET) begin end else if (s_offset == `RIBP_GPIO_ADMIN_OE_SET) begin
s_output_enable_d = s_output_enable_q | s_write_bits; s_output_en_d = s_output_en_q | s_write_bits;
end else if (s_offset == `RIBP_GPIO_ADMIN_OE_CLEAR) begin end else if (s_offset == `RIBP_GPIO_ADMIN_OE_CLEAR) begin
s_output_enable_d = s_output_enable_q & ~s_write_bits; s_output_en_d = s_output_en_q & ~s_write_bits;
end else begin end else begin
s_output_enable_d = s_output_enable_q ^ s_write_bits; s_output_en_d = s_output_en_q ^ s_write_bits;
end end
if (|((s_output_enable_d ^ s_output_enable_q) & s_config_lock_q)) begin if (|((s_output_en_d ^ s_output_en_q) & s_config_lock_q)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else s_output_enable_en = 1'b1; end else s_output_en_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_OPEN_DRAIN: begin `RIBP_GPIO_ADMIN_OPEN_DRAIN: begin
s_open_drain_d = merge_pins(s_open_drain_q, ribp.wdata, ribp.wstrb); s_open_drain_d = merge_pins(s_open_drain_q, ribp.wdata, ribp.wstrb);
if (|((s_open_drain_d ^ s_open_drain_q) & s_config_lock_q)) s_access_error = 1'b1; if (|((s_open_drain_d ^ s_open_drain_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_open_drain_en = 1'b1; else s_open_drain_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_INPUT_CMOS: begin `RIBP_GPIO_ADMIN_INPUT_CMOS: begin
s_input_cmos_d = merge_pins(s_input_cmos_q, ribp.wdata, ribp.wstrb); s_input_cmos_d = merge_pins(s_input_cmos_q, ribp.wdata, ribp.wstrb);
if ((!HAS_INPUT_CMOS && (|s_input_cmos_d)) || if ((!HAS_INPUT_CMOS && (|s_input_cmos_d)) ||
(|((s_input_cmos_d ^ s_input_cmos_q) & s_config_lock_q))) begin (|((s_input_cmos_d ^ s_input_cmos_q) & s_config_lock_q))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else s_input_cmos_en = 1'b1; end else s_input_cmos_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_PULL_UP: begin `RIBP_GPIO_ADMIN_PULL_UP: begin
s_pull_up_d = merge_pins(s_pull_up_q, ribp.wdata, ribp.wstrb); s_pull_up_d = merge_pins(s_pull_up_q, ribp.wdata, ribp.wstrb);
if ((!HAS_PULL_UP && (|s_pull_up_d)) || (|(s_pull_up_d & s_pull_down_q)) || if ((!HAS_PULL_UP && (|s_pull_up_d)) || (|(s_pull_up_d & s_pull_down_q)) ||
(|((s_pull_up_d ^ s_pull_up_q) & s_config_lock_q))) begin (|((s_pull_up_d ^ s_pull_up_q) & s_config_lock_q))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else s_pull_up_en = 1'b1; end else s_pull_up_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_PULL_DOWN: begin `RIBP_GPIO_ADMIN_PULL_DOWN: begin
s_pull_down_d = merge_pins(s_pull_down_q, ribp.wdata, ribp.wstrb); s_pull_down_d = merge_pins(s_pull_down_q, ribp.wdata, ribp.wstrb);
if ((!HAS_PULL_DOWN && (|s_pull_down_d)) || (|(s_pull_down_d & s_pull_up_q)) || if ((!HAS_PULL_DOWN && (|s_pull_down_d)) || (|(s_pull_down_d & s_pull_up_q)) ||
(|((s_pull_down_d ^ s_pull_down_q) & s_config_lock_q))) begin (|((s_pull_down_d ^ s_pull_down_q) & s_config_lock_q))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else s_pull_down_en = 1'b1; end else s_pull_down_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_ALT_ENABLE: begin `RIBP_GPIO_ADMIN_ALT_ENABLE: begin
s_alt_enable_d = merge_pins(s_alt_enable_q, ribp.wdata, ribp.wstrb); s_alt_en_d = merge_pins(s_alt_en_q, ribp.wdata, ribp.wstrb);
if (|((s_alt_enable_d ^ s_alt_enable_q) & s_config_lock_q)) s_access_error = 1'b1; if (|((s_alt_en_d ^ s_alt_en_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_alt_enable_en = 1'b1; else s_alt_en_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_ALT_SELECT: begin `RIBP_GPIO_ADMIN_ALT_SELECT: begin
s_alt_select_d = merge_pins(s_alt_select_q, ribp.wdata, ribp.wstrb); s_alt_sel_d = merge_pins(s_alt_sel_q, ribp.wdata, ribp.wstrb);
if (|((s_alt_select_d ^ s_alt_select_q) & s_config_lock_q)) s_access_error = 1'b1; if (|((s_alt_sel_d ^ s_alt_sel_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_alt_select_en = 1'b1; else s_alt_sel_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_USER_SELECT: begin `RIBP_GPIO_ADMIN_USER_SELECT: begin
s_user_select_d = merge_pins(s_user_select_q, ribp.wdata, ribp.wstrb); s_user_sel_d = merge_pins(s_user_sel_q, ribp.wdata, ribp.wstrb);
if (|((s_user_select_d ^ s_user_select_q) & s_user_lock_q)) s_access_error = 1'b1; if (|((s_user_sel_d ^ s_user_sel_q) & s_user_lock_q)) s_access_err = 1'b1;
else s_user_select_en = 1'b1; else s_user_sel_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_USER_LOCK: begin `RIBP_GPIO_ADMIN_USER_LOCK: begin
s_user_lock_en = 1'b1; s_user_lock_en = 1'b1;
@@ -338,7 +338,7 @@ module gpio_reg #(
end end
`RIBP_GPIO_ADMIN_USER_ACCESS_MASK: begin `RIBP_GPIO_ADMIN_USER_ACCESS_MASK: begin
s_user_access_d = merge_pins(s_user_access_q, ribp.wdata, ribp.wstrb); s_user_access_d = merge_pins(s_user_access_q, ribp.wdata, ribp.wstrb);
if (|((s_user_access_d ^ s_user_access_q) & s_config_lock_q)) s_access_error = 1'b1; if (|((s_user_access_d ^ s_user_access_q) & s_config_lock_q)) s_access_err = 1'b1;
else s_user_access_en = 1'b1; else s_user_access_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_INTR_RISE_ENABLE, `RIBP_GPIO_ADMIN_INTR_RISE_ENABLE,
@@ -359,7 +359,7 @@ module gpio_reg #(
) || (|(((s_intr_rise_d ^ s_intr_rise_q) | (s_intr_fall_d ^ s_intr_fall_q) | ) || (|(((s_intr_rise_d ^ s_intr_rise_q) | (s_intr_fall_d ^ s_intr_fall_q) |
(s_intr_high_d ^ s_intr_high_q) | (s_intr_low_d ^ s_intr_low_q)) & (s_intr_high_d ^ s_intr_high_q) | (s_intr_low_d ^ s_intr_low_q)) &
s_config_lock_q))) begin s_config_lock_q))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_rise_en = s_offset == `RIBP_GPIO_ADMIN_INTR_RISE_ENABLE; s_intr_rise_en = s_offset == `RIBP_GPIO_ADMIN_INTR_RISE_ENABLE;
s_intr_fall_en = s_offset == `RIBP_GPIO_ADMIN_INTR_FALL_ENABLE; s_intr_fall_en = s_offset == `RIBP_GPIO_ADMIN_INTR_FALL_ENABLE;
@@ -368,24 +368,24 @@ module gpio_reg #(
end end
end end
`RIBP_GPIO_ADMIN_INTR_ENABLE: begin `RIBP_GPIO_ADMIN_INTR_ENABLE: begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = merge_pins(s_intr_enable_q, ribp.wdata, ribp.wstrb); s_intr_en_d = merge_pins(s_intr_en_q, ribp.wdata, ribp.wstrb);
end end
`RIBP_GPIO_ADMIN_INTR_STATE: s_intr_clear = s_write_bits; `RIBP_GPIO_ADMIN_INTR_STATE: s_intr_clear = s_write_bits;
`RIBP_GPIO_ADMIN_INTR_TEST: s_intr_test = s_write_bits; `RIBP_GPIO_ADMIN_INTR_TEST: s_intr_test = s_write_bits;
`RIBP_GPIO_ADMIN_FILTER_ENABLE: begin `RIBP_GPIO_ADMIN_FILTER_ENABLE: begin
s_filter_enable_d = merge_pins(s_filter_enable_q, ribp.wdata, ribp.wstrb); s_filter_en_d = merge_pins(s_filter_en_q, ribp.wdata, ribp.wstrb);
if (((|s_filter_enable_d) && (s_filter_count_q == 4'd0)) || if (((|s_filter_en_d) && (s_filter_count_q == 4'd0)) ||
(|((s_filter_enable_d ^ s_filter_enable_q) & s_config_lock_q))) begin (|((s_filter_en_d ^ s_filter_en_q) & s_config_lock_q))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else s_filter_enable_en = 1'b1; end else s_filter_en_en = 1'b1;
end end
`RIBP_GPIO_ADMIN_FILTER_DIV: begin `RIBP_GPIO_ADMIN_FILTER_DIV: begin
if (|s_filter_enable_q) begin if (|s_filter_en_q) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_ribp_rdata_d = merge_wstrb({16'd0, s_filter_div_q}, ribp.wdata, ribp.wstrb); s_ribp_rdata_d = merge_wstrb({16'd0, s_filter_div_q}, ribp.wdata, ribp.wstrb);
if (|s_ribp_rdata_d[31:16]) s_access_error = 1'b1; if (|s_ribp_rdata_d[31:16]) s_access_err = 1'b1;
else begin else begin
s_filter_div_en = 1'b1; s_filter_div_en = 1'b1;
s_filter_div_d = s_ribp_rdata_d[15:0]; s_filter_div_d = s_ribp_rdata_d[15:0];
@@ -393,12 +393,12 @@ module gpio_reg #(
end end
end end
`RIBP_GPIO_ADMIN_FILTER_COUNT: begin `RIBP_GPIO_ADMIN_FILTER_COUNT: begin
if (|s_filter_enable_q) begin if (|s_filter_en_q) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_ribp_rdata_d = merge_wstrb({28'd0, s_filter_count_q}, ribp.wdata, ribp.wstrb); s_ribp_rdata_d = merge_wstrb({28'd0, s_filter_count_q}, ribp.wdata, ribp.wstrb);
if ((|s_ribp_rdata_d[31:4]) || (s_ribp_rdata_d[3:0] == 4'd0)) begin if ((|s_ribp_rdata_d[31:4]) || (s_ribp_rdata_d[3:0] == 4'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_filter_count_en = 1'b1; s_filter_count_en = 1'b1;
s_filter_count_d = s_ribp_rdata_d[3:0]; s_filter_count_d = s_ribp_rdata_d[3:0];
@@ -409,190 +409,231 @@ module gpio_reg #(
s_config_lock_en = 1'b1; s_config_lock_en = 1'b1;
s_config_lock_d = s_config_lock_q | s_write_bits; s_config_lock_d = s_config_lock_q | s_write_bits;
end end
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end else begin end else begin
unique case (s_offset) unique case (s_offset)
`RIBP_GPIO_ADMIN_DATA_IN: s_ribp_rdata_d = extend_pins(data_in_i); `RIBP_GPIO_ADMIN_DATA_IN: s_ribp_rdata_d = extend_pins(data_in_i);
`RIBP_GPIO_ADMIN_DATA_OUT: s_ribp_rdata_d = extend_pins(s_data_out_q); `RIBP_GPIO_ADMIN_DATA_OUT: s_ribp_rdata_d = extend_pins(s_data_out_q);
`RIBP_GPIO_ADMIN_OUTPUT_ENABLE: s_ribp_rdata_d = extend_pins(s_output_enable_q); `RIBP_GPIO_ADMIN_OUTPUT_ENABLE: s_ribp_rdata_d = extend_pins(s_output_en_q);
`RIBP_GPIO_ADMIN_OPEN_DRAIN: s_ribp_rdata_d = extend_pins(s_open_drain_q); `RIBP_GPIO_ADMIN_OPEN_DRAIN: s_ribp_rdata_d = extend_pins(s_open_drain_q);
`RIBP_GPIO_ADMIN_INPUT_CMOS: s_ribp_rdata_d = extend_pins(s_input_cmos_q); `RIBP_GPIO_ADMIN_INPUT_CMOS: s_ribp_rdata_d = extend_pins(s_input_cmos_q);
`RIBP_GPIO_ADMIN_PULL_UP: s_ribp_rdata_d = extend_pins(s_pull_up_q); `RIBP_GPIO_ADMIN_PULL_UP: s_ribp_rdata_d = extend_pins(s_pull_up_q);
`RIBP_GPIO_ADMIN_PULL_DOWN: s_ribp_rdata_d = extend_pins(s_pull_down_q); `RIBP_GPIO_ADMIN_PULL_DOWN: s_ribp_rdata_d = extend_pins(s_pull_down_q);
`RIBP_GPIO_ADMIN_ALT_ENABLE: s_ribp_rdata_d = extend_pins(s_alt_enable_q); `RIBP_GPIO_ADMIN_ALT_ENABLE: s_ribp_rdata_d = extend_pins(s_alt_en_q);
`RIBP_GPIO_ADMIN_ALT_SELECT: s_ribp_rdata_d = extend_pins(s_alt_select_q); `RIBP_GPIO_ADMIN_ALT_SELECT: s_ribp_rdata_d = extend_pins(s_alt_sel_q);
`RIBP_GPIO_ADMIN_USER_SELECT: s_ribp_rdata_d = extend_pins(s_user_select_q); `RIBP_GPIO_ADMIN_USER_SELECT: s_ribp_rdata_d = extend_pins(s_user_sel_q);
`RIBP_GPIO_ADMIN_USER_LOCK: s_ribp_rdata_d = extend_pins(s_user_lock_q); `RIBP_GPIO_ADMIN_USER_LOCK: s_ribp_rdata_d = extend_pins(s_user_lock_q);
`RIBP_GPIO_ADMIN_USER_STATUS: `RIBP_GPIO_ADMIN_USER_STATUS:
s_ribp_rdata_d = extend_pins(s_user_select_q & ~s_user_handoff_q); s_ribp_rdata_d = extend_pins(s_user_sel_q & ~s_user_handoff_q);
`RIBP_GPIO_ADMIN_USER_ACCESS_MASK: s_ribp_rdata_d = extend_pins(s_user_access_q); `RIBP_GPIO_ADMIN_USER_ACCESS_MASK: s_ribp_rdata_d = extend_pins(s_user_access_q);
`RIBP_GPIO_ADMIN_INTR_RISE_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_rise_q); `RIBP_GPIO_ADMIN_INTR_RISE_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_rise_q);
`RIBP_GPIO_ADMIN_INTR_FALL_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_fall_q); `RIBP_GPIO_ADMIN_INTR_FALL_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_fall_q);
`RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_high_q); `RIBP_GPIO_ADMIN_INTR_HIGH_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_high_q);
`RIBP_GPIO_ADMIN_INTR_LOW_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_low_q); `RIBP_GPIO_ADMIN_INTR_LOW_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_low_q);
`RIBP_GPIO_ADMIN_INTR_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_enable_q); `RIBP_GPIO_ADMIN_INTR_ENABLE: s_ribp_rdata_d = extend_pins(s_intr_en_q);
`RIBP_GPIO_ADMIN_INTR_STATE: s_ribp_rdata_d = extend_pins(s_intr_state_q); `RIBP_GPIO_ADMIN_INTR_STATE: s_ribp_rdata_d = extend_pins(s_intr_state_q);
`RIBP_GPIO_ADMIN_INTR_STATUS: `RIBP_GPIO_ADMIN_INTR_STATUS: s_ribp_rdata_d = extend_pins(s_intr_state_q & s_intr_en_q);
s_ribp_rdata_d = extend_pins(s_intr_state_q & s_intr_enable_q); `RIBP_GPIO_ADMIN_FILTER_ENABLE: s_ribp_rdata_d = extend_pins(s_filter_en_q);
`RIBP_GPIO_ADMIN_FILTER_ENABLE: s_ribp_rdata_d = extend_pins(s_filter_enable_q);
`RIBP_GPIO_ADMIN_FILTER_DIV: s_ribp_rdata_d = {16'd0, s_filter_div_q}; `RIBP_GPIO_ADMIN_FILTER_DIV: s_ribp_rdata_d = {16'd0, s_filter_div_q};
`RIBP_GPIO_ADMIN_FILTER_COUNT: s_ribp_rdata_d = {28'd0, s_filter_count_q}; `RIBP_GPIO_ADMIN_FILTER_COUNT: s_ribp_rdata_d = {28'd0, s_filter_count_q};
`RIBP_GPIO_ADMIN_CONFIG_LOCK: s_ribp_rdata_d = extend_pins(s_config_lock_q); `RIBP_GPIO_ADMIN_CONFIG_LOCK: s_ribp_rdata_d = extend_pins(s_config_lock_q);
`RIBP_GPIO_PAD_CAPABILITY: s_ribp_rdata_d = PAD_CAPABILITY; `RIBP_GPIO_PAD_CAPABILITY: s_ribp_rdata_d = PAD_CAPABILITY;
`RIBP_GPIO_IP_VERSION: s_ribp_rdata_d = IP_VERSION; `RIBP_GPIO_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_GPIO_CAPABILITY: s_ribp_rdata_d = CAPABILITY; `RIBP_GPIO_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end end
end end
end end
assign s_user_handoff_d = s_user_select_en ? (s_user_select_d ^ s_user_select_q) : '0; assign s_user_handoff_d = s_user_sel_en ? (s_user_sel_d ^ s_user_sel_q) : '0;
assign s_intr_state_d = (s_intr_state_q & ~s_intr_clear) | intr_event_i | s_intr_test; assign s_intr_state_d = (s_intr_state_q & ~s_intr_clear) | intr_event_i | s_intr_test;
assign s_intr_state_en = (|s_intr_clear) || (|intr_event_i) || (|s_intr_test); assign s_intr_state_en = (|s_intr_clear) || (|intr_event_i) || (|s_intr_test);
dffer #(PIN_NUM) u_data_out_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_data_out_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_data_out_en), .en_i (s_data_out_en),
.dat_i (s_data_out_d), .dat_i (s_data_out_d),
.dat_o (s_data_out_q) .dat_o (s_data_out_q)
); );
dffer #(PIN_NUM) u_output_enable_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_output_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_output_enable_en), .en_i (s_output_en_en),
.dat_i (s_output_enable_d), .dat_i (s_output_en_d),
.dat_o (s_output_enable_q) .dat_o (s_output_en_q)
); );
dffer #(PIN_NUM) u_open_drain_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_open_drain_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_open_drain_en), .en_i (s_open_drain_en),
.dat_i (s_open_drain_d), .dat_i (s_open_drain_d),
.dat_o (s_open_drain_q) .dat_o (s_open_drain_q)
); );
dffer #(PIN_NUM) u_input_cmos_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_input_cmos_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_input_cmos_en), .en_i (s_input_cmos_en),
.dat_i (s_input_cmos_d), .dat_i (s_input_cmos_d),
.dat_o (s_input_cmos_q) .dat_o (s_input_cmos_q)
); );
dffer #(PIN_NUM) u_pull_up_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_pull_up_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_pull_up_en), .en_i (s_pull_up_en),
.dat_i (s_pull_up_d), .dat_i (s_pull_up_d),
.dat_o (s_pull_up_q) .dat_o (s_pull_up_q)
); );
dffer #(PIN_NUM) u_pull_down_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_pull_down_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_pull_down_en), .en_i (s_pull_down_en),
.dat_i (s_pull_down_d), .dat_i (s_pull_down_d),
.dat_o (s_pull_down_q) .dat_o (s_pull_down_q)
); );
dffer #(PIN_NUM) u_alt_enable_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_alt_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_alt_enable_en), .en_i (s_alt_en_en),
.dat_i (s_alt_enable_d), .dat_i (s_alt_en_d),
.dat_o (s_alt_enable_q) .dat_o (s_alt_en_q)
); );
dffer #(PIN_NUM) u_alt_select_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_alt_select_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_alt_select_en), .en_i (s_alt_sel_en),
.dat_i (s_alt_select_d), .dat_i (s_alt_sel_d),
.dat_o (s_alt_select_q) .dat_o (s_alt_sel_q)
); );
dffer #(PIN_NUM) u_user_select_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_user_select_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_user_select_en), .en_i (s_user_sel_en),
.dat_i (s_user_select_d), .dat_i (s_user_sel_d),
.dat_o (s_user_select_q) .dat_o (s_user_sel_q)
); );
dffer #(PIN_NUM) u_user_lock_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_user_lock_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_user_lock_en), .en_i (s_user_lock_en),
.dat_i (s_user_lock_d), .dat_i (s_user_lock_d),
.dat_o (s_user_lock_q) .dat_o (s_user_lock_q)
); );
dffer #(PIN_NUM) u_user_access_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_user_access_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_user_access_en), .en_i (s_user_access_en),
.dat_i (s_user_access_d), .dat_i (s_user_access_d),
.dat_o (s_user_access_q) .dat_o (s_user_access_q)
); );
dffer #(PIN_NUM) u_intr_rise_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_intr_rise_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_rise_en), .en_i (s_intr_rise_en),
.dat_i (s_intr_rise_d), .dat_i (s_intr_rise_d),
.dat_o (s_intr_rise_q) .dat_o (s_intr_rise_q)
); );
dffer #(PIN_NUM) u_intr_fall_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_intr_fall_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_fall_en), .en_i (s_intr_fall_en),
.dat_i (s_intr_fall_d), .dat_i (s_intr_fall_d),
.dat_o (s_intr_fall_q) .dat_o (s_intr_fall_q)
); );
dffer #(PIN_NUM) u_intr_high_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_intr_high_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_high_en), .en_i (s_intr_high_en),
.dat_i (s_intr_high_d), .dat_i (s_intr_high_d),
.dat_o (s_intr_high_q) .dat_o (s_intr_high_q)
); );
dffer #(PIN_NUM) u_intr_low_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_intr_low_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_low_en), .en_i (s_intr_low_en),
.dat_i (s_intr_low_d), .dat_i (s_intr_low_d),
.dat_o (s_intr_low_q) .dat_o (s_intr_low_q)
); );
dffer #(PIN_NUM) u_intr_enable_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_intr_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_enable_en), .en_i (s_intr_en_en),
.dat_i (s_intr_enable_d), .dat_i (s_intr_en_d),
.dat_o (s_intr_enable_q) .dat_o (s_intr_en_q)
); );
dffer #(PIN_NUM) u_intr_state_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_intr_state_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_state_en), .en_i (s_intr_state_en),
.dat_i (s_intr_state_d), .dat_i (s_intr_state_d),
.dat_o (s_intr_state_q) .dat_o (s_intr_state_q)
); );
dffer #(PIN_NUM) u_filter_enable_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_filter_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_filter_enable_en), .en_i (s_filter_en_en),
.dat_i (s_filter_enable_d), .dat_i (s_filter_en_d),
.dat_o (s_filter_enable_q) .dat_o (s_filter_en_q)
); );
dffer #(PIN_NUM) u_config_lock_dffer ( dffer #(
.DATA_WIDTH(PIN_NUM)
) u_config_lock_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_config_lock_en), .en_i (s_config_lock_en),
.dat_i (s_config_lock_d), .dat_i (s_config_lock_d),
.dat_o (s_config_lock_q) .dat_o (s_config_lock_q)
); );
dffer #(16) u_filter_div_dffer ( dffer #(
.DATA_WIDTH(16)
) u_filter_div_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_filter_div_en), .en_i (s_filter_div_en),
.dat_i (s_filter_div_d), .dat_i (s_filter_div_d),
.dat_o (s_filter_div_q) .dat_o (s_filter_div_q)
); );
dffer #(4) u_filter_count_dffer ( dffer #(
.DATA_WIDTH(4)
) u_filter_count_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_filter_count_en), .en_i (s_filter_count_en),
@@ -600,28 +641,36 @@ module gpio_reg #(
.dat_o (s_filter_count_q) .dat_o (s_filter_count_q)
); );
dffr #(PIN_NUM) u_user_handoff_dffr ( dffr #(
.DATA_WIDTH(PIN_NUM)
) u_user_handoff_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_user_handoff_d), .dat_i (s_user_handoff_d),
.dat_o (s_user_handoff_q) .dat_o (s_user_handoff_q)
); );
dffr #(1) u_ribp_ready_dffr ( dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_req_accept), .dat_i (s_req_accept),
.dat_o (s_ribp_ready_q) .dat_o (s_ribp_ready_q)
); );
assign s_ribp_resp_err_d = s_access_error; assign s_ribp_resp_err_d = s_access_err;
dffer #(1) u_ribp_resp_err_dffer ( dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d), .dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q) .dat_o (s_ribp_resp_err_q)
); );
dffer #(32) u_ribp_rdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
@@ -630,16 +679,16 @@ module gpio_reg #(
); );
assign data_out_o = s_data_out_q; assign data_out_o = s_data_out_q;
assign output_enable_o = s_output_enable_q; assign output_enable_o = s_output_en_q;
assign open_drain_o = s_open_drain_q; assign open_drain_o = s_open_drain_q;
assign input_cmos_o = s_input_cmos_q; assign input_cmos_o = s_input_cmos_q;
assign pull_up_o = s_pull_up_q; assign pull_up_o = s_pull_up_q;
assign pull_down_o = s_pull_down_q; assign pull_down_o = s_pull_down_q;
assign alt_enable_o = s_alt_enable_q; assign alt_enable_o = s_alt_en_q;
assign alt_select_o = s_alt_select_q; assign alt_select_o = s_alt_sel_q;
assign user_select_o = s_user_select_q; assign user_select_o = s_user_sel_q;
assign user_handoff_o = s_user_handoff_q; assign user_handoff_o = s_user_handoff_q;
assign filter_enable_o = s_filter_enable_q; assign filter_enable_o = s_filter_en_q;
assign filter_div_o = s_filter_div_q; assign filter_div_o = s_filter_div_q;
assign filter_count_o = s_filter_count_q; assign filter_count_o = s_filter_count_q;
assign intr_rise_enable_o = s_intr_rise_q; assign intr_rise_enable_o = s_intr_rise_q;
rtl/ip/ribp/peripheral/ribp_gpio.sv
+27 -27
View File
@@ -20,22 +20,22 @@ module ribp_gpio #(
logic [PIN_NUM-1:0] s_data_in; logic [PIN_NUM-1:0] s_data_in;
logic [PIN_NUM-1:0] s_data_out; logic [PIN_NUM-1:0] s_data_out;
logic [PIN_NUM-1:0] s_output_enable; logic [PIN_NUM-1:0] s_output_en;
logic [PIN_NUM-1:0] s_open_drain; logic [PIN_NUM-1:0] s_open_drain;
logic [PIN_NUM-1:0] s_input_cmos; logic [PIN_NUM-1:0] s_input_cmos;
logic [PIN_NUM-1:0] s_pull_up; logic [PIN_NUM-1:0] s_pull_up;
logic [PIN_NUM-1:0] s_pull_down; logic [PIN_NUM-1:0] s_pull_down;
logic [PIN_NUM-1:0] s_alt_enable; logic [PIN_NUM-1:0] s_alt_en;
logic [PIN_NUM-1:0] s_alt_select; logic [PIN_NUM-1:0] s_alt_sel;
logic [PIN_NUM-1:0] s_user_select; logic [PIN_NUM-1:0] s_user_sel;
logic [PIN_NUM-1:0] s_user_handoff; logic [PIN_NUM-1:0] s_user_handoff;
logic [PIN_NUM-1:0] s_filter_enable; logic [PIN_NUM-1:0] s_filter_en;
logic [ 15:0] s_filter_div; logic [ 15:0] s_filter_div;
logic [ 3:0] s_filter_count; logic [ 3:0] s_filter_count;
logic [PIN_NUM-1:0] s_intr_rise_enable; logic [PIN_NUM-1:0] s_intr_rise_en;
logic [PIN_NUM-1:0] s_intr_fall_enable; logic [PIN_NUM-1:0] s_intr_fall_en;
logic [PIN_NUM-1:0] s_intr_high_enable; logic [PIN_NUM-1:0] s_intr_high_en;
logic [PIN_NUM-1:0] s_intr_low_enable; logic [PIN_NUM-1:0] s_intr_low_en;
logic [PIN_NUM-1:0] s_intr_event; logic [PIN_NUM-1:0] s_intr_event;
logic s_irq; logic s_irq;
@@ -53,22 +53,22 @@ module ribp_gpio #(
.data_in_i (s_data_in), .data_in_i (s_data_in),
.intr_event_i (s_intr_event), .intr_event_i (s_intr_event),
.data_out_o (s_data_out), .data_out_o (s_data_out),
.output_enable_o (s_output_enable), .output_enable_o (s_output_en),
.open_drain_o (s_open_drain), .open_drain_o (s_open_drain),
.input_cmos_o (s_input_cmos), .input_cmos_o (s_input_cmos),
.pull_up_o (s_pull_up), .pull_up_o (s_pull_up),
.pull_down_o (s_pull_down), .pull_down_o (s_pull_down),
.alt_enable_o (s_alt_enable), .alt_enable_o (s_alt_en),
.alt_select_o (s_alt_select), .alt_select_o (s_alt_sel),
.user_select_o (s_user_select), .user_select_o (s_user_sel),
.user_handoff_o (s_user_handoff), .user_handoff_o (s_user_handoff),
.filter_enable_o (s_filter_enable), .filter_enable_o (s_filter_en),
.filter_div_o (s_filter_div), .filter_div_o (s_filter_div),
.filter_count_o (s_filter_count), .filter_count_o (s_filter_count),
.intr_rise_enable_o(s_intr_rise_enable), .intr_rise_enable_o(s_intr_rise_en),
.intr_fall_enable_o(s_intr_fall_enable), .intr_fall_enable_o(s_intr_fall_en),
.intr_high_enable_o(s_intr_high_enable), .intr_high_enable_o(s_intr_high_en),
.intr_low_enable_o (s_intr_low_enable), .intr_low_enable_o (s_intr_low_en),
.irq_o (s_irq) .irq_o (s_irq)
); );
@@ -78,22 +78,22 @@ module ribp_gpio #(
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.data_out_i (s_data_out), .data_out_i (s_data_out),
.output_enable_i (s_output_enable), .output_enable_i (s_output_en),
.open_drain_i (s_open_drain), .open_drain_i (s_open_drain),
.input_cmos_i (s_input_cmos), .input_cmos_i (s_input_cmos),
.pull_up_i (s_pull_up), .pull_up_i (s_pull_up),
.pull_down_i (s_pull_down), .pull_down_i (s_pull_down),
.alt_enable_i (s_alt_enable), .alt_enable_i (s_alt_en),
.alt_select_i (s_alt_select), .alt_select_i (s_alt_sel),
.user_select_i (s_user_select), .user_select_i (s_user_sel),
.user_handoff_i (s_user_handoff), .user_handoff_i (s_user_handoff),
.filter_enable_i (s_filter_enable), .filter_enable_i (s_filter_en),
.filter_div_i (s_filter_div), .filter_div_i (s_filter_div),
.filter_count_i (s_filter_count), .filter_count_i (s_filter_count),
.intr_rise_enable_i(s_intr_rise_enable), .intr_rise_enable_i(s_intr_rise_en),
.intr_fall_enable_i(s_intr_fall_enable), .intr_fall_enable_i(s_intr_fall_en),
.intr_high_enable_i(s_intr_high_enable), .intr_high_enable_i(s_intr_high_en),
.intr_low_enable_i (s_intr_low_enable), .intr_low_enable_i (s_intr_low_en),
.irq_i (s_irq), .irq_i (s_irq),
.data_in_o (s_data_in), .data_in_o (s_data_in),
.intr_event_o (s_intr_event), .intr_event_o (s_intr_event),
rtl/ip/ribp/peripheral/ribp_timer.sv
+12 -12
View File
@@ -11,12 +11,12 @@ module ribp_timer (
// verilog_format: on // verilog_format: on
); );
logic s_enable; logic s_en;
logic [ 1:0] s_mode; logic [ 1:0] s_mode;
logic s_direction; logic s_direction;
logic s_debug_freeze_enable; logic s_debug_freeze_en;
logic s_compare0_enable; logic s_compare0_en;
logic s_compare1_enable; logic s_compare1_en;
logic [15:0] s_prescale; logic [15:0] s_prescale;
logic [31:0] s_load; logic [31:0] s_load;
logic [31:0] s_compare0; logic [31:0] s_compare0;
@@ -41,12 +41,12 @@ module ribp_timer (
.compare0_event_i (s_compare0_event), .compare0_event_i (s_compare0_event),
.compare1_event_i (s_compare1_event), .compare1_event_i (s_compare1_event),
.one_shot_done_i (s_one_shot_done), .one_shot_done_i (s_one_shot_done),
.enable_o (s_enable), .enable_o (s_en),
.mode_o (s_mode), .mode_o (s_mode),
.direction_o (s_direction), .direction_o (s_direction),
.debug_freeze_enable_o(s_debug_freeze_enable), .debug_freeze_enable_o(s_debug_freeze_en),
.compare0_enable_o (s_compare0_enable), .compare0_enable_o (s_compare0_en),
.compare1_enable_o (s_compare1_enable), .compare1_enable_o (s_compare1_en),
.prescale_o (s_prescale), .prescale_o (s_prescale),
.load_o (s_load), .load_o (s_load),
.compare0_o (s_compare0), .compare0_o (s_compare0),
@@ -60,13 +60,13 @@ module ribp_timer (
timer_core u_timer_core ( timer_core u_timer_core (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.enable_i (s_enable), .enable_i (s_en),
.mode_i (s_mode), .mode_i (s_mode),
.direction_i (s_direction), .direction_i (s_direction),
.debug_freeze_enable_i(s_debug_freeze_enable), .debug_freeze_enable_i(s_debug_freeze_en),
.debug_halted_i (debug_halted_i), .debug_halted_i (debug_halted_i),
.compare0_enable_i (s_compare0_enable), .compare0_enable_i (s_compare0_en),
.compare1_enable_i (s_compare1_enable), .compare1_enable_i (s_compare1_en),
.prescale_i (s_prescale), .prescale_i (s_prescale),
.load_i (s_load), .load_i (s_load),
.compare0_i (s_compare0), .compare0_i (s_compare0),
rtl/ip/ribp/peripheral/sysctrl.sv
+317 -243
View File
@@ -144,25 +144,25 @@ module ribp_sysctrl (
logic s_user_reset_en; logic s_user_reset_en;
logic s_user_running_d, s_user_running_q; logic s_user_running_d, s_user_running_q;
logic s_user_draining_d, s_user_draining_q; logic s_user_draining_d, s_user_draining_q;
logic s_user_config_error_d, s_user_config_error_q; logic s_user_config_err_d, s_user_config_err_q;
logic s_user_config_error_clear; logic s_user_config_err_clear;
logic s_user_reset_write_legal; logic s_user_reset_write_legal;
logic [`USER_CORE_COUNT-1:0] s_user_reset_write_data; logic [`USER_CORE_COUNT-1:0] s_user_reset_write_data;
logic s_sysctrl_ipsel_en; logic s_sysctrl_ipsel_en;
logic [`USER_IPSEL_WIDTH-1:0] s_sysctrl_ipsel_d, s_sysctrl_ipsel_q; logic [`USER_IPSEL_WIDTH-1:0] s_sysctrl_ipsel_d, s_sysctrl_ipsel_q;
logic [2:0] s_pll_cfg_d, s_pll_cfg_q; logic [2:0] s_pll_cfg_d, s_pll_cfg_q;
logic s_pll_cfg_en; logic s_pll_cfg_en;
logic s_pll_apply, s_pll_clear_error; logic s_pll_apply, s_pll_clear_err;
logic s_pll_req_valid_d, s_pll_req_valid_q; logic s_pll_req_valid_d, s_pll_req_valid_q;
logic s_pll_busy_d, s_pll_busy_q; logic s_pll_busy_d, s_pll_busy_q;
logic s_pll_rsp_accept; logic s_pll_rsp_accept;
logic s_pll_error_d, s_pll_error_q; logic s_pll_err_d, s_pll_err_q;
logic [1:0] s_pll_error_reason_d, s_pll_error_reason_q; logic [1:0] s_pll_err_reason_d, s_pll_err_reason_q;
logic [2:0] s_pll_active_sel_d, s_pll_active_sel_q; logic [2:0] s_pll_active_sel_d, s_pll_active_sel_q;
logic s_pll_active_valid_d, s_pll_active_valid_q; logic s_pll_active_valid_d, s_pll_active_valid_q;
logic s_pll_safe_clk_d, s_pll_safe_clk_q; logic s_pll_safe_clk_d, s_pll_safe_clk_q;
logic s_pll_lock_d, s_pll_lock_q; logic s_pll_lock_d, s_pll_lock_q;
logic s_fault_status_clear; logic s_fault_stat_clear;
logic s_fault_pending_d, s_fault_pending_q; logic s_fault_pending_d, s_fault_pending_q;
logic s_fault_write_d, s_fault_write_q; logic s_fault_write_d, s_fault_write_q;
logic [2:0] s_fault_reason_d, s_fault_reason_q; logic [2:0] s_fault_reason_d, s_fault_reason_q;
@@ -170,8 +170,8 @@ module ribp_sysctrl (
logic [31:0] s_fault_addr_d, s_fault_addr_q; logic [31:0] s_fault_addr_d, s_fault_addr_q;
logic [31:0] s_fault_count_d, s_fault_count_q; logic [31:0] s_fault_count_d, s_fault_count_q;
logic [1:0] s_fault_master_d, s_fault_master_q; logic [1:0] s_fault_master_d, s_fault_master_q;
logic s_perf_enable_d, s_perf_enable_q; logic s_perf_en_d, s_perf_en_q;
logic s_perf_enable_en, s_perf_clear, s_perf_snapshot; logic s_perf_en_en, s_perf_clear, s_perf_snapshot;
logic [63:0] s_perf_mgmt_wait_q; logic [63:0] s_perf_mgmt_wait_q;
logic [63:0] s_perf_user_wait_q; logic [63:0] s_perf_user_wait_q;
logic [63:0] s_perf_dma_wait_q; logic [63:0] s_perf_dma_wait_q;
@@ -183,7 +183,7 @@ module ribp_sysctrl (
logic s_test_done_d, s_test_done_q; logic s_test_done_d, s_test_done_q;
logic s_test_pass_d, s_test_pass_q; logic s_test_pass_d, s_test_pass_q;
logic [7:0] s_test_code_d, s_test_code_q; logic [7:0] s_test_code_d, s_test_code_q;
logic s_test_status_write; logic s_test_stat_write;
logic s_rtc_wake_sync; logic s_rtc_wake_sync;
logic s_rtc_wake_clear; logic s_rtc_wake_clear;
logic s_rtc_wake_seen_d, s_rtc_wake_seen_q; logic s_rtc_wake_seen_d, s_rtc_wake_seen_q;
@@ -198,7 +198,7 @@ module ribp_sysctrl (
assign sysctrl.core_sel_o = s_sysctrl_coresel_q; assign sysctrl.core_sel_o = s_sysctrl_coresel_q;
assign sysctrl.core_reset_o = s_user_reset_q; assign sysctrl.core_reset_o = s_user_reset_q;
assign sysctrl.user_bus_enable_o = s_user_running_q; assign sysctrl.user_bus_enable_o = s_user_running_q;
assign sysctrl.perf_enable_o = s_perf_enable_q; assign sysctrl.perf_enable_o = s_perf_en_q;
assign sysctrl.perf_clear_o = s_perf_clear; assign sysctrl.perf_clear_o = s_perf_clear;
assign sysctrl.test_done_o = s_test_done_q; assign sysctrl.test_done_o = s_test_done_q;
assign sysctrl.test_pass_o = s_test_pass_q; assign sysctrl.test_pass_o = s_test_pass_q;
@@ -242,12 +242,14 @@ module ribp_sysctrl (
ribp.wstrb[0] && s_sysctrl_coresel_write_valid && ribp.wstrb[0] && s_sysctrl_coresel_write_valid &&
(&s_user_reset_q) && sysctrl.user_bus_idle_i && ~s_user_running_q; (&s_user_reset_q) && sysctrl.user_bus_idle_i && ~s_user_running_q;
assign s_sysctrl_coresel_d = ribp.wdata[`USER_CORESEL_WIDTH-1:0]; assign s_sysctrl_coresel_d = ribp.wdata[`USER_CORESEL_WIDTH-1:0];
dffer #(`USER_CORESEL_WIDTH) u_sysctrl_coresel_dffer ( dffer #(
clk_i, .DATA_WIDTH(`USER_CORESEL_WIDTH)
rst_n_i, ) u_sysctrl_coresel_dffer (
s_sysctrl_coresel_en, .clk_i (clk_i),
s_sysctrl_coresel_d, .rst_n_i(rst_n_i),
s_sysctrl_coresel_q .en_i (s_sysctrl_coresel_en),
.dat_i (s_sysctrl_coresel_d),
.dat_o (s_sysctrl_coresel_q)
); );
assign s_user_reset_write_data = ribp.wdata[`USER_CORE_COUNT-1:0]; assign s_user_reset_write_data = ribp.wdata[`USER_CORE_COUNT-1:0];
@@ -257,23 +259,23 @@ module ribp_sysctrl (
({{(`USER_CORE_COUNT - 1){1'b0}}, 1'b1} << s_sysctrl_coresel_q))); ({{(`USER_CORE_COUNT - 1){1'b0}}, 1'b1} << s_sysctrl_coresel_q)));
assign s_user_reset_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET && assign s_user_reset_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
ribp.wstrb[0]; ribp.wstrb[0];
assign s_user_config_error_clear = s_ribp_wr_hdshk && assign s_user_config_err_clear = s_ribp_wr_hdshk &&
ribp.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && ribp.wstrb[1] && ribp.wdata[11]; ribp.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && ribp.wstrb[1] && ribp.wdata[11];
always_comb begin always_comb begin
s_user_reset_d = s_user_reset_q; s_user_reset_d = s_user_reset_q;
s_user_running_d = s_user_running_q; s_user_running_d = s_user_running_q;
s_user_draining_d = s_user_draining_q; s_user_draining_d = s_user_draining_q;
s_user_config_error_d = s_user_config_error_q; s_user_config_err_d = s_user_config_err_q;
if (s_user_config_error_clear) begin if (s_user_config_err_clear) begin
s_user_config_error_d = 1'b0; s_user_config_err_d = 1'b0;
end end
if (s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin if (s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin
s_user_config_error_d = 1'b1; s_user_config_err_d = 1'b1;
end end
if (s_user_reset_en) begin if (s_user_reset_en) begin
if (~s_user_reset_write_legal) begin if (~s_user_reset_write_legal) begin
s_user_config_error_d = 1'b1; s_user_config_err_d = 1'b1;
end else if (&s_user_reset_write_data) begin end else if (&s_user_reset_write_data) begin
s_user_running_d = 1'b0; s_user_running_d = 1'b0;
if (sysctrl.user_bus_idle_i) begin if (sysctrl.user_bus_idle_i) begin
@@ -287,7 +289,7 @@ module ribp_sysctrl (
s_user_running_d = 1'b1; s_user_running_d = 1'b1;
s_user_draining_d = 1'b0; s_user_draining_d = 1'b0;
end else begin end else begin
s_user_config_error_d = 1'b1; s_user_config_err_d = 1'b1;
end end
end end
if (s_user_draining_q && sysctrl.user_bus_idle_i) begin if (s_user_draining_q && sysctrl.user_bus_idle_i) begin
@@ -295,54 +297,67 @@ module ribp_sysctrl (
s_user_draining_d = 1'b0; s_user_draining_d = 1'b0;
end end
end end
dffrc #(`USER_CORE_COUNT, '1) u_user_reset_dffrc ( dffrc #(
clk_i, .DATA_WIDTH(`USER_CORE_COUNT),
rst_n_i, .RESET_VAL ('1)
s_user_reset_d, ) u_user_reset_dffrc (
s_user_reset_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.dat_i (s_user_reset_d),
.dat_o (s_user_reset_q)
); );
dffr #(1) u_user_running_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_user_running_dffr (
s_user_running_d, .clk_i (clk_i),
s_user_running_q .rst_n_i(rst_n_i),
.dat_i (s_user_running_d),
.dat_o (s_user_running_q)
); );
dffr #(1) u_user_draining_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_user_draining_dffr (
s_user_draining_d, .clk_i (clk_i),
s_user_draining_q .rst_n_i(rst_n_i),
.dat_i (s_user_draining_d),
.dat_o (s_user_draining_q)
); );
dffr #(1) u_user_config_error_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_user_config_error_dffr (
s_user_config_error_d, .clk_i (clk_i),
s_user_config_error_q .rst_n_i(rst_n_i),
.dat_i (s_user_config_err_d),
.dat_o (s_user_config_err_q)
); );
assign s_sysctrl_ipsel_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_IPSEL_OFFSET; assign s_sysctrl_ipsel_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_IPSEL_OFFSET;
assign s_sysctrl_ipsel_d = ribp.wdata[`USER_IPSEL_WIDTH-1:0]; assign s_sysctrl_ipsel_d = ribp.wdata[`USER_IPSEL_WIDTH-1:0];
dffer #(`USER_IPSEL_WIDTH) u_sysctrl_ipsel_dffer ( dffer #(
clk_i, .DATA_WIDTH(`USER_IPSEL_WIDTH)
rst_n_i, ) u_sysctrl_ipsel_dffer (
s_sysctrl_ipsel_en, .clk_i (clk_i),
s_sysctrl_ipsel_d, .rst_n_i(rst_n_i),
s_sysctrl_ipsel_q .en_i (s_sysctrl_ipsel_en),
.dat_i (s_sysctrl_ipsel_d),
.dat_o (s_sysctrl_ipsel_q)
); );
assign s_pll_cfg_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && ribp.wstrb[0]; assign s_pll_cfg_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && ribp.wstrb[0];
assign s_pll_cfg_d = ribp.wdata[2:0]; assign s_pll_cfg_d = ribp.wdata[2:0];
dffer #(3) u_pll_cfg_dffer ( dffer #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_pll_cfg_dffer (
s_pll_cfg_en, .clk_i (clk_i),
s_pll_cfg_d, .rst_n_i(rst_n_i),
s_pll_cfg_q .en_i (s_pll_cfg_en),
.dat_i (s_pll_cfg_d),
.dat_o (s_pll_cfg_q)
); );
assign s_pll_apply = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET && assign s_pll_apply = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
ribp.wstrb[0] && ribp.wdata[0]; ribp.wstrb[0] && ribp.wdata[0];
assign s_pll_clear_error = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET && assign s_pll_clear_err = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
ribp.wstrb[0] && ribp.wdata[1]; ribp.wstrb[0] && ribp.wdata[1];
assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i && pll_ctrl.rsp_ready_o; assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i && pll_ctrl.rsp_ready_o;
@@ -360,178 +375,219 @@ module ribp_sysctrl (
s_pll_busy_d = 1'b0; s_pll_busy_d = 1'b0;
end end
end end
dffr #(1) u_pll_req_valid_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_pll_req_valid_dffr (
s_pll_req_valid_d, .clk_i (clk_i),
s_pll_req_valid_q .rst_n_i(rst_n_i),
.dat_i (s_pll_req_valid_d),
.dat_o (s_pll_req_valid_q)
); );
dffr #(1) u_pll_busy_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_pll_busy_dffr (
s_pll_busy_d, .clk_i (clk_i),
s_pll_busy_q .rst_n_i(rst_n_i),
.dat_i (s_pll_busy_d),
.dat_o (s_pll_busy_q)
); );
always_comb begin always_comb begin
s_pll_error_d = s_pll_error_q; s_pll_err_d = s_pll_err_q;
s_pll_error_reason_d = s_pll_error_reason_q; s_pll_err_reason_d = s_pll_err_reason_q;
if (s_pll_clear_error) begin if (s_pll_clear_err) begin
s_pll_error_d = 1'b0; s_pll_err_d = 1'b0;
s_pll_error_reason_d = 2'd0; s_pll_err_reason_d = 2'd0;
end end
if (s_pll_apply && (s_pll_busy_q || s_pll_req_valid_q)) begin if (s_pll_apply && (s_pll_busy_q || s_pll_req_valid_q)) begin
s_pll_error_d = 1'b1; s_pll_err_d = 1'b1;
s_pll_error_reason_d = 2'd3; s_pll_err_reason_d = 2'd3;
end end
if (s_pll_rsp_accept && |pll_ctrl.rsp_error_i) begin if (s_pll_rsp_accept && |pll_ctrl.rsp_error_i) begin
s_pll_error_d = 1'b1; s_pll_err_d = 1'b1;
s_pll_error_reason_d = pll_ctrl.rsp_error_i; s_pll_err_reason_d = pll_ctrl.rsp_error_i;
end end
end end
dffr #(1) u_pll_error_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_pll_error_dffr (
s_pll_error_d, .clk_i (clk_i),
s_pll_error_q .rst_n_i(rst_n_i),
.dat_i (s_pll_err_d),
.dat_o (s_pll_err_q)
); );
dffr #(2) u_pll_error_reason_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_pll_error_reason_dffr (
s_pll_error_reason_d, .clk_i (clk_i),
s_pll_error_reason_q .rst_n_i(rst_n_i),
.dat_i (s_pll_err_reason_d),
.dat_o (s_pll_err_reason_q)
); );
assign s_pll_active_sel_d = pll_ctrl.rsp_active_sel_i; assign s_pll_active_sel_d = pll_ctrl.rsp_active_sel_i;
dffer #(3) u_pll_active_sel_dffer ( dffer #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_pll_active_sel_dffer (
s_pll_rsp_accept, .clk_i (clk_i),
s_pll_active_sel_d, .rst_n_i(rst_n_i),
s_pll_active_sel_q .en_i (s_pll_rsp_accept),
.dat_i (s_pll_active_sel_d),
.dat_o (s_pll_active_sel_q)
); );
assign s_pll_active_valid_d = pll_ctrl.rsp_active_valid_i; assign s_pll_active_valid_d = pll_ctrl.rsp_active_valid_i;
dffer #(1) u_pll_active_valid_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_pll_active_valid_dffer (
s_pll_rsp_accept, .clk_i (clk_i),
s_pll_active_valid_d, .rst_n_i(rst_n_i),
s_pll_active_valid_q .en_i (s_pll_rsp_accept),
.dat_i (s_pll_active_valid_d),
.dat_o (s_pll_active_valid_q)
); );
assign s_pll_safe_clk_d = pll_ctrl.rsp_safe_clk_i; assign s_pll_safe_clk_d = pll_ctrl.rsp_safe_clk_i;
dfferc #(1, 1'b1) u_pll_safe_clk_dfferc ( dfferc #(
clk_i, .DATA_WIDTH(1),
rst_n_i, .RESET_VAL (1'b1)
s_pll_rsp_accept, ) u_pll_safe_clk_dfferc (
s_pll_safe_clk_d, .clk_i (clk_i),
s_pll_safe_clk_q .rst_n_i(rst_n_i),
.en_i (s_pll_rsp_accept),
.dat_i (s_pll_safe_clk_d),
.dat_o (s_pll_safe_clk_q)
); );
assign s_pll_lock_d = pll_ctrl.rsp_pll_lock_i; assign s_pll_lock_d = pll_ctrl.rsp_pll_lock_i;
dffer #(1) u_pll_lock_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_pll_lock_dffer (
s_pll_rsp_accept, .clk_i (clk_i),
s_pll_lock_d, .rst_n_i(rst_n_i),
s_pll_lock_q .en_i (s_pll_rsp_accept),
.dat_i (s_pll_lock_d),
.dat_o (s_pll_lock_q)
); );
assign s_perf_enable_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET && assign s_perf_en_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET &&
ribp.wstrb[0]; ribp.wstrb[0];
assign s_perf_enable_d = ribp.wdata[0]; assign s_perf_en_d = ribp.wdata[0];
assign s_perf_clear = s_perf_enable_en && ribp.wdata[1]; assign s_perf_clear = s_perf_en_en && ribp.wdata[1];
assign s_perf_snapshot = s_perf_enable_en && ribp.wdata[2]; assign s_perf_snapshot = s_perf_en_en && ribp.wdata[2];
dffer #(1) u_perf_enable_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_perf_enable_dffer (
s_perf_enable_en, .clk_i (clk_i),
s_perf_enable_d, .rst_n_i(rst_n_i),
s_perf_enable_q .en_i (s_perf_en_en),
.dat_i (s_perf_en_d),
.dat_o (s_perf_en_q)
); );
dffer #(64) u_perf_mgmt_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_mgmt_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_mgmt_wait_i, .rst_n_i(rst_n_i),
s_perf_mgmt_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_mgmt_wait_i),
.dat_o (s_perf_mgmt_wait_q)
); );
dffer #(64) u_perf_user_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_user_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_user_wait_i, .rst_n_i(rst_n_i),
s_perf_user_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_user_wait_i),
.dat_o (s_perf_user_wait_q)
); );
dffer #(64) u_perf_dma_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_dma_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_dma_wait_i, .rst_n_i(rst_n_i),
s_perf_dma_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_dma_wait_i),
.dat_o (s_perf_dma_wait_q)
); );
dffer #(64) u_perf_ribp_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_ribp_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_ribp_wait_i, .rst_n_i(rst_n_i),
s_perf_ribp_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_ribp_wait_i),
.dat_o (s_perf_ribp_wait_q)
); );
dffer #(64) u_perf_apb_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_apb_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_apb_wait_i, .rst_n_i(rst_n_i),
s_perf_apb_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_apb_wait_i),
.dat_o (s_perf_apb_wait_q)
); );
dffer #(64) u_perf_sdram_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_sdram_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_sdram_wait_i, .rst_n_i(rst_n_i),
s_perf_sdram_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_sdram_wait_i),
.dat_o (s_perf_sdram_wait_q)
); );
dffer #(64) u_perf_psram_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_psram_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_psram_wait_i, .rst_n_i(rst_n_i),
s_perf_psram_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_psram_wait_i),
.dat_o (s_perf_psram_wait_q)
); );
dffer #(64) u_perf_flash_wait_dffer ( dffer #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_flash_wait_dffer (
s_perf_snapshot, .clk_i (clk_i),
sysctrl.perf_flash_wait_i, .rst_n_i(rst_n_i),
s_perf_flash_wait_q .en_i (s_perf_snapshot),
.dat_i (sysctrl.perf_flash_wait_i),
.dat_o (s_perf_flash_wait_q)
); );
assign s_test_status_write = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_TEST_STATUS_OFFSET && assign s_test_stat_write = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_TEST_STATUS_OFFSET &&
ribp.wstrb == 4'hF && ribp.wdata[31] && ~s_test_done_q; ribp.wstrb == 4'hF && ribp.wdata[31] && ~s_test_done_q;
assign s_test_done_d = 1'b1; assign s_test_done_d = 1'b1;
dffer #(1) u_test_done_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_test_done_dffer (
s_test_status_write, .clk_i (clk_i),
s_test_done_d, .rst_n_i(rst_n_i),
s_test_done_q .en_i (s_test_stat_write),
.dat_i (s_test_done_d),
.dat_o (s_test_done_q)
); );
assign s_test_pass_d = ribp.wdata[0]; assign s_test_pass_d = ribp.wdata[0];
dffer #(1) u_test_pass_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_test_pass_dffer (
s_test_status_write, .clk_i (clk_i),
s_test_pass_d, .rst_n_i(rst_n_i),
s_test_pass_q .en_i (s_test_stat_write),
.dat_i (s_test_pass_d),
.dat_o (s_test_pass_q)
); );
assign s_test_code_d = ribp.wdata[15:8]; assign s_test_code_d = ribp.wdata[15:8];
dffer #(8) u_test_code_dffer ( dffer #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_test_code_dffer (
s_test_status_write, .clk_i (clk_i),
s_test_code_d, .rst_n_i(rst_n_i),
s_test_code_q .en_i (s_test_stat_write),
.dat_i (s_test_code_d),
.dat_o (s_test_code_q)
); );
assign s_fault_status_clear = s_ribp_wr_hdshk && assign s_fault_stat_clear = s_ribp_wr_hdshk &&
ribp.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET && ribp.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET &&
ribp.wstrb[0] && ribp.wdata[0]; ribp.wstrb[0] && ribp.wdata[0];
always_comb begin always_comb begin
@@ -541,12 +597,12 @@ module ribp_sysctrl (
s_fault_detail_d = s_fault_detail_q; s_fault_detail_d = s_fault_detail_q;
s_fault_addr_d = s_fault_addr_q; s_fault_addr_d = s_fault_addr_q;
s_fault_count_d = s_fault_count_q; s_fault_count_d = s_fault_count_q;
if (s_fault_status_clear) begin if (s_fault_stat_clear) begin
s_fault_pending_d = 1'b0; s_fault_pending_d = 1'b0;
end end
if (fault_valid_i) begin if (fault_valid_i) begin
s_fault_pending_d = 1'b1; s_fault_pending_d = 1'b1;
if (~s_fault_pending_q || s_fault_status_clear) begin if (~s_fault_pending_q || s_fault_stat_clear) begin
s_fault_write_d = |fault_wstrb_i; s_fault_write_d = |fault_wstrb_i;
s_fault_detail_d = |sysctrl.fault_code_i ? sysctrl.fault_code_i : s_fault_detail_d = |sysctrl.fault_code_i ? sysctrl.fault_code_i :
sysctrl.fault_access_i ? `RIB_RESP_PROTERR : sysctrl.fault_access_i ? `RIB_RESP_PROTERR :
@@ -565,61 +621,77 @@ module ribp_sysctrl (
end end
end end
end end
dffr #(1) u_fault_pending_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_fault_pending_dffr (
s_fault_pending_d, .clk_i (clk_i),
s_fault_pending_q .rst_n_i(rst_n_i),
.dat_i (s_fault_pending_d),
.dat_o (s_fault_pending_q)
); );
dffr #(1) u_fault_write_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_fault_write_dffr (
s_fault_write_d, .clk_i (clk_i),
s_fault_write_q .rst_n_i(rst_n_i),
.dat_i (s_fault_write_d),
.dat_o (s_fault_write_q)
); );
dffr #(3) u_fault_reason_dffr ( dffr #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_fault_reason_dffr (
s_fault_reason_d, .clk_i (clk_i),
s_fault_reason_q .rst_n_i(rst_n_i),
.dat_i (s_fault_reason_d),
.dat_o (s_fault_reason_q)
); );
dffr #(3) u_fault_detail_dffr ( dffr #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_fault_detail_dffr (
s_fault_detail_d, .clk_i (clk_i),
s_fault_detail_q .rst_n_i(rst_n_i),
.dat_i (s_fault_detail_d),
.dat_o (s_fault_detail_q)
); );
dffr #(32) u_fault_addr_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_fault_addr_dffr (
s_fault_addr_d, .clk_i (clk_i),
s_fault_addr_q .rst_n_i(rst_n_i),
.dat_i (s_fault_addr_d),
.dat_o (s_fault_addr_q)
); );
dffr #(32) u_fault_count_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_fault_count_dffr (
s_fault_count_d, .clk_i (clk_i),
s_fault_count_q .rst_n_i(rst_n_i),
.dat_i (s_fault_count_d),
.dat_o (s_fault_count_q)
); );
always_comb begin always_comb begin
s_fault_master_d = s_fault_master_q; s_fault_master_d = s_fault_master_q;
if (fault_valid_i && (~s_fault_pending_q || s_fault_status_clear)) begin if (fault_valid_i && (~s_fault_pending_q || s_fault_stat_clear)) begin
s_fault_master_d = sysctrl.fault_master_i; s_fault_master_d = sysctrl.fault_master_i;
end end
end end
dffr #(2) u_fault_master_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_fault_master_dffr (
s_fault_master_d, .clk_i (clk_i),
s_fault_master_q .rst_n_i(rst_n_i),
.dat_i (s_fault_master_d),
.dat_o (s_fault_master_q)
); );
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
assign s_ribp_rdata_en = s_ribp_rd_hdshk; assign s_ribp_rdata_en = s_ribp_rd_hdshk;
@@ -638,8 +710,8 @@ module ribp_sysctrl (
pll_ctrl.capable_i, pll_ctrl.capable_i,
s_pll_lock_q, s_pll_lock_q,
s_pll_safe_clk_q, s_pll_safe_clk_q,
s_pll_error_reason_q, s_pll_err_reason_q,
s_pll_error_q, s_pll_err_q,
s_pll_busy_q, s_pll_busy_q,
s_pll_active_valid_q, s_pll_active_valid_q,
s_pll_active_sel_q s_pll_active_sel_q
@@ -647,7 +719,7 @@ module ribp_sysctrl (
SYSCTRL_USER_CORE_RESET_OFFSET: s_ribp_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q}; SYSCTRL_USER_CORE_RESET_OFFSET: s_ribp_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q};
SYSCTRL_USER_CORE_STATUS_OFFSET: s_ribp_rdata_d = { SYSCTRL_USER_CORE_STATUS_OFFSET: s_ribp_rdata_d = {
20'd0, 20'd0,
s_user_config_error_q, s_user_config_err_q,
s_user_draining_q, s_user_draining_q,
sysctrl.user_bus_idle_i, sysctrl.user_bus_idle_i,
s_user_running_q, s_user_running_q,
@@ -656,7 +728,7 @@ module ribp_sysctrl (
}; };
SYSCTRL_FAULT_MASTER_OFFSET: s_ribp_rdata_d = {30'd0, s_fault_master_q}; SYSCTRL_FAULT_MASTER_OFFSET: s_ribp_rdata_d = {30'd0, s_fault_master_q};
SYSCTRL_FAULT_DETAIL_OFFSET: s_ribp_rdata_d = {29'd0, s_fault_detail_q}; SYSCTRL_FAULT_DETAIL_OFFSET: s_ribp_rdata_d = {29'd0, s_fault_detail_q};
SYSCTRL_PERF_CTRL_OFFSET: s_ribp_rdata_d = {31'd0, s_perf_enable_q}; SYSCTRL_PERF_CTRL_OFFSET: s_ribp_rdata_d = {31'd0, s_perf_en_q};
SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_mgmt_wait_q[31:0]; SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_mgmt_wait_q[31:0];
SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_mgmt_wait_q[63:32]; SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_mgmt_wait_q[63:32];
SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_user_wait_q[31:0]; SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_user_wait_q[31:0];
@@ -683,12 +755,14 @@ module ribp_sysctrl (
endcase endcase
// verilog_format: on // verilog_format: on
end end
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
endmodule endmodule
rtl/ip/ribp/peripheral/timer_core.sv
+6 -4
View File
@@ -37,7 +37,7 @@ module timer_core #(
logic [PRESCALE_WIDTH-1:0] s_prescale_count; logic [PRESCALE_WIDTH-1:0] s_prescale_count;
logic s_prescale_load; logic s_prescale_load;
logic s_prescale_enable; logic s_prescale_en;
logic s_tick; logic s_tick;
logic s_terminal; logic s_terminal;
logic s_prescale_overflow; logic s_prescale_overflow;
@@ -54,7 +54,7 @@ module timer_core #(
assign s_tick = enable_i && !debug_frozen_o && !start_i && !stop_i && !load_now_i && assign s_tick = enable_i && !debug_frozen_o && !start_i && !stop_i && !load_now_i &&
(s_prescale_count == '0) && !s_prescale_overflow; (s_prescale_count == '0) && !s_prescale_overflow;
assign s_prescale_load = start_i || (enable_i && load_now_i) || s_tick; assign s_prescale_load = start_i || (enable_i && load_now_i) || s_tick;
assign s_prescale_enable = enable_i && !debug_frozen_o && !start_i && !stop_i && !load_now_i && assign s_prescale_en = enable_i && !debug_frozen_o && !start_i && !stop_i && !load_now_i &&
!s_tick; !s_tick;
rs_counter #( rs_counter #(
@@ -63,7 +63,7 @@ module timer_core #(
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.clr_i (1'b0), .clr_i (1'b0),
.en_i (s_prescale_enable), .en_i (s_prescale_en),
.load_i (s_prescale_load), .load_i (s_prescale_load),
.down_i (1'b1), .down_i (1'b1),
.dat_i (prescale_i), .dat_i (prescale_i),
@@ -114,7 +114,9 @@ module timer_core #(
end end
end end
dffr #(COUNTER_WIDTH) u_value_dffr ( dffr #(
.DATA_WIDTH(COUNTER_WIDTH)
) u_value_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_value_d), .dat_i (s_value_d),
rtl/ip/ribp/peripheral/timer_reg.sv
+77 -59
View File
@@ -49,7 +49,7 @@ module timer_reg (
logic s_req_accept; logic s_req_accept;
logic [11:0] s_offset; logic [11:0] s_offset;
logic s_aligned; logic s_aligned;
logic s_access_error; logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q; logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q; logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q; logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
@@ -60,13 +60,13 @@ module timer_reg (
logic [15:0] s_prescale_write_value; logic [15:0] s_prescale_write_value;
logic [31:0] s_compare0_write_value; logic [31:0] s_compare0_write_value;
logic [31:0] s_compare1_write_value; logic [31:0] s_compare1_write_value;
logic [ 2:0] s_intr_enable_write_value; logic [ 2:0] s_intr_en_write_value;
logic [ 2:0] s_intr_clear; logic [ 2:0] s_intr_clear;
logic [ 2:0] s_intr_set; logic [ 2:0] s_intr_set;
logic [ 2:0] s_intr_state_d; logic [ 2:0] s_intr_state_d;
logic [ 2:0] s_intr_state_q; logic [ 2:0] s_intr_state_q;
logic [ 2:0] s_intr_enable_d; logic [ 2:0] s_intr_en_d;
logic [ 2:0] s_intr_enable_q; logic [ 2:0] s_intr_en_q;
logic [31:0] s_ctrl_d, s_ctrl_q; logic [31:0] s_ctrl_d, s_ctrl_q;
logic [31:0] s_load_d, s_load_q; logic [31:0] s_load_d, s_load_q;
logic [15:0] s_prescale_d, s_prescale_q; logic [15:0] s_prescale_d, s_prescale_q;
@@ -103,19 +103,17 @@ module timer_reg (
assign s_prescale_write_value = 16'(merge_wstrb({16'd0, s_prescale_q}, ribp.wdata, ribp.wstrb)); assign s_prescale_write_value = 16'(merge_wstrb({16'd0, s_prescale_q}, ribp.wdata, ribp.wstrb));
assign s_compare0_write_value = merge_wstrb(s_compare0_q, ribp.wdata, ribp.wstrb); assign s_compare0_write_value = merge_wstrb(s_compare0_q, ribp.wdata, ribp.wstrb);
assign s_compare1_write_value = merge_wstrb(s_compare1_q, ribp.wdata, ribp.wstrb); assign s_compare1_write_value = merge_wstrb(s_compare1_q, ribp.wdata, ribp.wstrb);
assign s_intr_enable_write_value = 3'(merge_wstrb( assign s_intr_en_write_value = 3'(merge_wstrb({29'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb));
{29'd0, s_intr_enable_q}, ribp.wdata, ribp.wstrb
));
always_comb begin always_comb begin
s_access_error = !s_aligned; s_access_err = !s_aligned;
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
if (s_aligned) begin if (s_aligned) begin
unique case (s_offset) unique case (s_offset)
`RIBP_TIMER_CTRL: begin `RIBP_TIMER_CTRL: begin
s_ribp_rdata_d = s_ctrl_q; s_ribp_rdata_d = s_ctrl_q;
if (s_write) begin if (s_write) begin
s_access_error = s_access_err =
(s_ctrl_write_value[2:1] == MODE_RESERVED) || (s_ctrl_write_value[2:1] == MODE_RESERVED) ||
(enable_o && (|((s_ctrl_write_value ^ s_ctrl_q) & CTRL_ACTIVE_IMMUTABLE_MASK))); (enable_o && (|((s_ctrl_write_value ^ s_ctrl_q) & CTRL_ACTIVE_IMMUTABLE_MASK)));
end end
@@ -123,57 +121,59 @@ module timer_reg (
`RIBP_TIMER_LOAD: s_ribp_rdata_d = s_load_q; `RIBP_TIMER_LOAD: s_ribp_rdata_d = s_load_q;
`RIBP_TIMER_VALUE: begin `RIBP_TIMER_VALUE: begin
s_ribp_rdata_d = value_i; s_ribp_rdata_d = value_i;
s_access_error = s_write; s_access_err = s_write;
end end
`RIBP_TIMER_BGLOAD: s_ribp_rdata_d = s_load_q; `RIBP_TIMER_BGLOAD: s_ribp_rdata_d = s_load_q;
`RIBP_TIMER_PRESCALE: begin `RIBP_TIMER_PRESCALE: begin
s_ribp_rdata_d = {16'd0, s_prescale_q}; s_ribp_rdata_d = {16'd0, s_prescale_q};
s_access_error = s_write && enable_o; s_access_err = s_write && enable_o;
end end
`RIBP_TIMER_COMPARE0: s_ribp_rdata_d = s_compare0_q; `RIBP_TIMER_COMPARE0: s_ribp_rdata_d = s_compare0_q;
`RIBP_TIMER_COMPARE1: s_ribp_rdata_d = s_compare1_q; `RIBP_TIMER_COMPARE1: s_ribp_rdata_d = s_compare1_q;
`RIBP_TIMER_STATUS: begin `RIBP_TIMER_STATUS: begin
s_ribp_rdata_d = {30'd0, debug_frozen_i, enable_o}; s_ribp_rdata_d = {30'd0, debug_frozen_i, enable_o};
s_access_error = s_write; s_access_err = s_write;
end end
`RIBP_TIMER_INTR_STATE: s_ribp_rdata_d = {29'd0, s_intr_state_q}; `RIBP_TIMER_INTR_STATE: s_ribp_rdata_d = {29'd0, s_intr_state_q};
`RIBP_TIMER_INTR_ENABLE: s_ribp_rdata_d = {29'd0, s_intr_enable_q}; `RIBP_TIMER_INTR_ENABLE: s_ribp_rdata_d = {29'd0, s_intr_en_q};
`RIBP_TIMER_INTR_STATUS: begin `RIBP_TIMER_INTR_STATUS: begin
s_ribp_rdata_d = {29'd0, s_intr_state_q & s_intr_enable_q}; s_ribp_rdata_d = {29'd0, s_intr_state_q & s_intr_en_q};
s_access_error = s_write; s_access_err = s_write;
end end
`RIBP_TIMER_INTR_TEST: s_access_error = !s_write; `RIBP_TIMER_INTR_TEST: s_access_err = !s_write;
`RIBP_TIMER_IP_VERSION: begin `RIBP_TIMER_IP_VERSION: begin
s_ribp_rdata_d = IP_VERSION; s_ribp_rdata_d = IP_VERSION;
s_access_error = s_write; s_access_err = s_write;
end end
`RIBP_TIMER_CAPABILITY: begin `RIBP_TIMER_CAPABILITY: begin
s_ribp_rdata_d = CAPABILITY; s_ribp_rdata_d = CAPABILITY;
s_access_error = s_write; s_access_err = s_write;
end end
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end end
end end
assign start_o = s_req_accept && s_write && !s_access_error && assign start_o = s_req_accept && s_write && !s_access_err &&
(s_offset == `RIBP_TIMER_CTRL) && !enable_o && (s_offset == `RIBP_TIMER_CTRL) && !enable_o &&
s_ctrl_write_value[`TIMER_CTRL_ENABLE]; s_ctrl_write_value[`TIMER_CTRL_ENABLE];
assign stop_o = s_req_accept && s_write && !s_access_error && assign stop_o = s_req_accept && s_write && !s_access_err &&
(s_offset == `RIBP_TIMER_CTRL) && enable_o && (s_offset == `RIBP_TIMER_CTRL) && enable_o &&
!s_ctrl_write_value[`TIMER_CTRL_ENABLE]; !s_ctrl_write_value[`TIMER_CTRL_ENABLE];
assign load_now_o = s_req_accept && s_write && !s_access_error && (s_offset == `RIBP_TIMER_LOAD); assign load_now_o = s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_LOAD);
always_comb begin always_comb begin
s_ctrl_d = s_ctrl_q; s_ctrl_d = s_ctrl_q;
if (s_req_accept && s_write && !s_access_error && (s_offset == `RIBP_TIMER_CTRL)) begin if (s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_CTRL)) begin
s_ctrl_d = s_ctrl_write_value; s_ctrl_d = s_ctrl_write_value;
end end
if (one_shot_done_i) begin if (one_shot_done_i) begin
s_ctrl_d[`TIMER_CTRL_ENABLE] = 1'b0; s_ctrl_d[`TIMER_CTRL_ENABLE] = 1'b0;
end end
end end
dffr #(32) u_ctrl_dffr ( dffr #(
.DATA_WIDTH(32)
) u_ctrl_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_ctrl_d), .dat_i (s_ctrl_d),
@@ -182,12 +182,14 @@ module timer_reg (
always_comb begin always_comb begin
s_load_d = s_load_q; s_load_d = s_load_q;
if (s_req_accept && s_write && !s_access_error) begin if (s_req_accept && s_write && !s_access_err) begin
if (s_offset == `RIBP_TIMER_LOAD) s_load_d = s_load_write_value; if (s_offset == `RIBP_TIMER_LOAD) s_load_d = s_load_write_value;
else if (s_offset == `RIBP_TIMER_BGLOAD) s_load_d = s_bgload_write_value; else if (s_offset == `RIBP_TIMER_BGLOAD) s_load_d = s_bgload_write_value;
end end
end end
dffr #(32) u_load_dffr ( dffr #(
.DATA_WIDTH(32)
) u_load_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_load_d), .dat_i (s_load_d),
@@ -196,11 +198,13 @@ module timer_reg (
always_comb begin always_comb begin
s_prescale_d = s_prescale_q; s_prescale_d = s_prescale_q;
if (s_req_accept && s_write && !s_access_error && (s_offset == `RIBP_TIMER_PRESCALE)) begin if (s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_PRESCALE)) begin
s_prescale_d = s_prescale_write_value; s_prescale_d = s_prescale_write_value;
end end
end end
dffr #(16) u_prescale_dffr ( dffr #(
.DATA_WIDTH(16)
) u_prescale_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_prescale_d), .dat_i (s_prescale_d),
@@ -210,18 +214,22 @@ module timer_reg (
always_comb begin always_comb begin
s_compare0_d = s_compare0_q; s_compare0_d = s_compare0_q;
s_compare1_d = s_compare1_q; s_compare1_d = s_compare1_q;
if (s_req_accept && s_write && !s_access_error) begin if (s_req_accept && s_write && !s_access_err) begin
if (s_offset == `RIBP_TIMER_COMPARE0) s_compare0_d = s_compare0_write_value; if (s_offset == `RIBP_TIMER_COMPARE0) s_compare0_d = s_compare0_write_value;
if (s_offset == `RIBP_TIMER_COMPARE1) s_compare1_d = s_compare1_write_value; if (s_offset == `RIBP_TIMER_COMPARE1) s_compare1_d = s_compare1_write_value;
end end
end end
dffr #(32) u_compare0_dffr ( dffr #(
.DATA_WIDTH(32)
) u_compare0_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_compare0_d), .dat_i (s_compare0_d),
.dat_o (s_compare0_q) .dat_o (s_compare0_q)
); );
dffr #(32) u_compare1_dffr ( dffr #(
.DATA_WIDTH(32)
) u_compare1_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_compare1_d), .dat_i (s_compare1_d),
@@ -229,22 +237,24 @@ module timer_reg (
); );
always_comb begin always_comb begin
s_intr_enable_d = s_intr_enable_q; s_intr_en_d = s_intr_en_q;
if (s_req_accept && s_write && !s_access_error && (s_offset == `RIBP_TIMER_INTR_ENABLE)) begin if (s_req_accept && s_write && !s_access_err && (s_offset == `RIBP_TIMER_INTR_ENABLE)) begin
s_intr_enable_d = s_intr_enable_write_value; s_intr_en_d = s_intr_en_write_value;
end end
end end
dffr #(3) u_intr_enable_dffr ( dffr #(
.DATA_WIDTH(3)
) u_intr_enable_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_intr_enable_d), .dat_i (s_intr_en_d),
.dat_o (s_intr_enable_q) .dat_o (s_intr_en_q)
); );
always_comb begin always_comb begin
s_intr_clear = '0; s_intr_clear = '0;
s_intr_set = {compare1_event_i, compare0_event_i, timeout_event_i}; s_intr_set = {compare1_event_i, compare0_event_i, timeout_event_i};
if (s_req_accept && s_write && !s_access_error) begin if (s_req_accept && s_write && !s_access_err) begin
if ((s_offset == `RIBP_TIMER_INTR_STATE) && ribp.wstrb[0]) begin if ((s_offset == `RIBP_TIMER_INTR_STATE) && ribp.wstrb[0]) begin
s_intr_clear = ribp.wdata[2:0]; s_intr_clear = ribp.wdata[2:0];
end end
@@ -254,7 +264,9 @@ module timer_reg (
end end
s_intr_state_d = (s_intr_state_q & ~s_intr_clear) | s_intr_set; s_intr_state_d = (s_intr_state_q & ~s_intr_clear) | s_intr_set;
end end
dffr #(3) u_intr_state_dffr ( dffr #(
.DATA_WIDTH(3)
) u_intr_state_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_intr_state_d), .dat_i (s_intr_state_d),
@@ -268,7 +280,7 @@ module timer_reg (
assign compare0_enable_o = s_ctrl_q[`TIMER_CTRL_COMPARE0_ENABLE]; assign compare0_enable_o = s_ctrl_q[`TIMER_CTRL_COMPARE0_ENABLE];
assign compare1_enable_o = s_ctrl_q[`TIMER_CTRL_COMPARE1_ENABLE]; assign compare1_enable_o = s_ctrl_q[`TIMER_CTRL_COMPARE1_ENABLE];
assign prescale_o = s_prescale_q; assign prescale_o = s_prescale_q;
assign load_o = (s_req_accept && s_write && !s_access_error && assign load_o = (s_req_accept && s_write && !s_access_err &&
((s_offset == `RIBP_TIMER_LOAD) || ((s_offset == `RIBP_TIMER_LOAD) ||
(s_offset == `RIBP_TIMER_BGLOAD))) ? (s_offset == `RIBP_TIMER_BGLOAD))) ?
(s_offset == `RIBP_TIMER_LOAD ? (s_offset == `RIBP_TIMER_LOAD ?
@@ -276,30 +288,36 @@ module timer_reg (
s_load_q; s_load_q;
assign compare0_o = s_compare0_q; assign compare0_o = s_compare0_q;
assign compare1_o = s_compare1_q; assign compare1_o = s_compare1_q;
assign irq_o = |(s_intr_state_q & s_intr_enable_q); assign irq_o = |(s_intr_state_q & s_intr_en_q);
assign s_ribp_ready_d = s_req_accept; assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_error; assign s_ribp_resp_err_d = s_access_err;
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
dffer #(1) u_ribp_resp_err_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_resp_err_dffer (
s_req_accept, .clk_i (clk_i),
s_ribp_resp_err_d, .rst_n_i(rst_n_i),
s_ribp_resp_err_q .en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
); );
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_req_accept, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
endmodule endmodule
rtl/ip/ribp/serial/i2c_core.sv
+130 -104
View File
@@ -94,13 +94,13 @@ module i2c_core (
logic [$bits(i2c_byte_role_t)-1:0] s_byte_role_d_raw, s_byte_role_q_raw; logic [$bits(i2c_byte_role_t)-1:0] s_byte_role_d_raw, s_byte_role_q_raw;
logic [23:0] s_phase_count_d, s_phase_count_q; logic [23:0] s_phase_count_d, s_phase_count_q;
logic [23:0] s_stretch_count_d, s_stretch_count_q; logic [23:0] s_stretch_count_d, s_stretch_count_q;
logic [23:0] s_command_count_d, s_command_count_q; logic [23:0] s_cmd_count_d, s_cmd_count_q;
logic [11:0] s_command_d, s_command_q; logic [11:0] s_cmd_d, s_cmd_q;
logic [7:0] s_tx_byte_d, s_tx_byte_q; logic [7:0] s_tx_byte_d, s_tx_byte_q;
logic [7:0] s_rx_byte_d, s_rx_byte_q; logic [7:0] s_rx_byte_d, s_rx_byte_q;
logic [2:0] s_bit_index_d, s_bit_index_q; logic [2:0] s_bit_index_d, s_bit_index_q;
logic [3:0] s_recovery_pulse_d, s_recovery_pulse_q; logic [3:0] s_recovery_pulse_d, s_recovery_pulse_q;
logic s_command_active_d, s_command_active_q; logic s_cmd_active_d, s_cmd_active_q;
logic s_bus_owned_d, s_bus_owned_q; logic s_bus_owned_d, s_bus_owned_q;
logic s_recovery_d, s_recovery_q; logic s_recovery_d, s_recovery_q;
logic s_read_header_only_d, s_read_header_only_q; logic s_read_header_only_d, s_read_header_only_q;
@@ -111,7 +111,7 @@ module i2c_core (
logic s_low_phase_done; logic s_low_phase_done;
logic s_stretch_timeout; logic s_stretch_timeout;
logic s_bus_idle_timeout; logic s_bus_idle_timeout;
logic s_command_timeout; logic s_cmd_timeout;
logic s_arbitration_lost; logic s_arbitration_lost;
function automatic logic timeout_expired(input logic [23:0] count, input logic [23:0] limit); function automatic logic timeout_expired(input logic [23:0] count, input logic [23:0] limit);
@@ -137,10 +137,10 @@ module i2c_core (
({1'b0, s_phase_count_q[15:0]} >= (s_data_low_cycles - 1'b1))); ({1'b0, s_phase_count_q[15:0]} >= (s_data_low_cycles - 1'b1)));
assign s_stretch_timeout = timeout_expired(s_stretch_count_q, stretch_timeout_i); assign s_stretch_timeout = timeout_expired(s_stretch_count_q, stretch_timeout_i);
assign s_bus_idle_timeout = timeout_expired(s_phase_count_q, bus_idle_timeout_i); assign s_bus_idle_timeout = timeout_expired(s_phase_count_q, bus_idle_timeout_i);
assign s_command_timeout = timeout_expired(s_command_count_q, command_timeout_i); assign s_cmd_timeout = timeout_expired(s_cmd_count_q, command_timeout_i);
assign s_arbitration_lost = (s_bit_action_q == BIT_TX) && s_tx_bit && !sda_i; assign s_arbitration_lost = (s_bit_action_q == BIT_TX) && s_tx_bit && !sda_i;
assign busy_o = (s_fsm_q != FSM_IDLE) || s_command_active_q || s_recovery_q; assign busy_o = (s_fsm_q != FSM_IDLE) || s_cmd_active_q || s_recovery_q;
assign recovery_active_o = s_recovery_q; assign recovery_active_o = s_recovery_q;
assign rx_data_o = s_rx_byte_q; assign rx_data_o = s_rx_byte_q;
@@ -156,7 +156,7 @@ module i2c_core (
scl_pull_low_o = s_fsm_q == FSM_BIT_LOW; scl_pull_low_o = s_fsm_q == FSM_BIT_LOW;
unique case (s_bit_action_q) unique case (s_bit_action_q)
BIT_TX: sda_pull_low_o = !s_tx_bit; BIT_TX: sda_pull_low_o = !s_tx_bit;
BIT_CONTROLLER_ACK: sda_pull_low_o = !s_command_q[11] && !s_rx_overflow_q; BIT_CONTROLLER_ACK: sda_pull_low_o = !s_cmd_q[11] && !s_rx_overflow_q;
default: sda_pull_low_o = 1'b0; default: sda_pull_low_o = 1'b0;
endcase endcase
end end
@@ -186,13 +186,13 @@ module i2c_core (
s_byte_role_d = s_byte_role_q; s_byte_role_d = s_byte_role_q;
s_phase_count_d = s_phase_count_q; s_phase_count_d = s_phase_count_q;
s_stretch_count_d = s_stretch_count_q; s_stretch_count_d = s_stretch_count_q;
s_command_count_d = s_command_count_q; s_cmd_count_d = s_cmd_count_q;
s_command_d = s_command_q; s_cmd_d = s_cmd_q;
s_tx_byte_d = s_tx_byte_q; s_tx_byte_d = s_tx_byte_q;
s_rx_byte_d = s_rx_byte_q; s_rx_byte_d = s_rx_byte_q;
s_bit_index_d = s_bit_index_q; s_bit_index_d = s_bit_index_q;
s_recovery_pulse_d = s_recovery_pulse_q; s_recovery_pulse_d = s_recovery_pulse_q;
s_command_active_d = s_command_active_q; s_cmd_active_d = s_cmd_active_q;
s_bus_owned_d = s_bus_owned_q; s_bus_owned_d = s_bus_owned_q;
s_recovery_d = s_recovery_q; s_recovery_d = s_recovery_q;
s_read_header_only_d = s_read_header_only_q; s_read_header_only_d = s_read_header_only_q;
@@ -216,19 +216,19 @@ module i2c_core (
if ((s_fsm_q != FSM_IDLE) && (s_fsm_q != FSM_BUS_FREE) && if ((s_fsm_q != FSM_IDLE) && (s_fsm_q != FSM_BUS_FREE) &&
(s_fsm_q != FSM_RECOVERY_LOW) && (s_fsm_q != FSM_RECOVERY_HIGH_WAIT) && (s_fsm_q != FSM_RECOVERY_LOW) && (s_fsm_q != FSM_RECOVERY_HIGH_WAIT) &&
(s_fsm_q != FSM_RECOVERY_HIGH)) begin (s_fsm_q != FSM_RECOVERY_HIGH)) begin
if (!s_command_timeout) begin if (!s_cmd_timeout) begin
s_command_count_d = s_command_count_q + 1'b1; s_cmd_count_d = s_cmd_count_q + 1'b1;
end end
end else begin end else begin
s_command_count_d = '0; s_cmd_count_d = '0;
end end
if (abort_i && (s_fsm_q != FSM_IDLE)) begin if (abort_i && (s_fsm_q != FSM_IDLE)) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_recovery_d = 1'b0; s_recovery_d = 1'b0;
s_rx_overflow_d = 1'b0; s_rx_overflow_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
aborted_event_o = 1'b1; aborted_event_o = 1'b1;
if (s_bus_owned_q) begin if (s_bus_owned_q) begin
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
s_phase_count_d = '0; s_phase_count_d = '0;
@@ -236,10 +236,10 @@ module i2c_core (
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
end end
end else if (s_command_timeout && (s_fsm_q != FSM_IDLE) && !s_recovery_q && end else if (s_cmd_timeout && (s_fsm_q != FSM_IDLE) && !s_recovery_q &&
(s_fsm_q != FSM_STOP_LOW) && (s_fsm_q != FSM_STOP_HIGH_WAIT) && (s_fsm_q != FSM_STOP_LOW) && (s_fsm_q != FSM_STOP_HIGH_WAIT) &&
(s_fsm_q != FSM_STOP_SETUP) && (s_fsm_q != FSM_BUS_FREE)) begin (s_fsm_q != FSM_STOP_SETUP) && (s_fsm_q != FSM_BUS_FREE)) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_rx_overflow_d = 1'b0; s_rx_overflow_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
command_timeout_event_o = 1'b1; command_timeout_event_o = 1'b1;
@@ -250,8 +250,8 @@ module i2c_core (
FSM_IDLE: begin FSM_IDLE: begin
s_phase_count_d = '0; s_phase_count_d = '0;
s_stretch_count_d = '0; s_stretch_count_d = '0;
s_command_count_d = '0; s_cmd_count_d = '0;
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
s_recovery_d = 1'b0; s_recovery_d = 1'b0;
s_read_header_only_d = 1'b0; s_read_header_only_d = 1'b0;
@@ -261,10 +261,10 @@ module i2c_core (
s_recovery_pulse_d = '0; s_recovery_pulse_d = '0;
s_fsm_d = FSM_RECOVERY_LOW; s_fsm_d = FSM_RECOVERY_LOW;
end else if (cmd_valid_i && enable_i) begin end else if (cmd_valid_i && enable_i) begin
s_command_d = cmd_data_i; s_cmd_d = cmd_data_i;
s_command_active_d = 1'b1; s_cmd_active_d = 1'b1;
cmd_pop_o = 1'b1; cmd_pop_o = 1'b1;
s_fsm_d = FSM_BUS_WAIT; s_fsm_d = FSM_BUS_WAIT;
end end
end end
@@ -277,7 +277,7 @@ module i2c_core (
s_phase_count_d = s_phase_count_q + 1'b1; s_phase_count_d = s_phase_count_q + 1'b1;
end end
end else if (s_bus_idle_timeout) begin end else if (s_bus_idle_timeout) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
bus_timeout_event_o = 1'b1; bus_timeout_event_o = 1'b1;
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
@@ -299,7 +299,7 @@ module i2c_core (
if (!scl_i) begin if (!scl_i) begin
s_phase_count_d = '0; s_phase_count_d = '0;
if (s_stretch_timeout) begin if (s_stretch_timeout) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
stretch_timeout_event_o = 1'b1; stretch_timeout_event_o = 1'b1;
@@ -311,11 +311,11 @@ module i2c_core (
s_phase_count_d = '0; s_phase_count_d = '0;
s_stretch_count_d = '0; s_stretch_count_d = '0;
if (s_bus_owned_q) begin if (s_bus_owned_q) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
arb_lost_event_o = 1'b1; arb_lost_event_o = 1'b1;
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
end else begin end else begin
s_fsm_d = FSM_BUS_WAIT; s_fsm_d = FSM_BUS_WAIT;
end end
@@ -335,7 +335,7 @@ module i2c_core (
s_bit_index_d = 3'd7; s_bit_index_d = 3'd7;
s_bit_action_d = BIT_TX; s_bit_action_d = BIT_TX;
if (!ten_bit_i) begin if (!ten_bit_i) begin
s_tx_byte_d = {target_addr_i[6:0], s_command_q[8]}; s_tx_byte_d = {target_addr_i[6:0], s_cmd_q[8]};
s_byte_role_d = BYTE_ADDR_7; s_byte_role_d = BYTE_ADDR_7;
end else if (s_read_header_only_q) begin end else if (s_read_header_only_q) begin
s_tx_byte_d = {5'b11110, target_addr_i[9:8], 1'b1}; s_tx_byte_d = {5'b11110, target_addr_i[9:8], 1'b1};
@@ -369,16 +369,16 @@ module i2c_core (
s_rx_byte_d[s_bit_index_q] = sda_i; s_rx_byte_d[s_bit_index_q] = sda_i;
end end
if (s_arbitration_lost) begin if (s_arbitration_lost) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
arb_lost_event_o = 1'b1; arb_lost_event_o = 1'b1;
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
end else begin end else begin
s_fsm_d = FSM_BIT_HIGH; s_fsm_d = FSM_BIT_HIGH;
end end
end else if (s_stretch_timeout) begin end else if (s_stretch_timeout) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
stretch_timeout_event_o = 1'b1; stretch_timeout_event_o = 1'b1;
@@ -390,11 +390,11 @@ module i2c_core (
FSM_BIT_HIGH: begin FSM_BIT_HIGH: begin
if (s_arbitration_lost) begin if (s_arbitration_lost) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
arb_lost_event_o = 1'b1; arb_lost_event_o = 1'b1;
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
end else if (s_phase_done) begin end else if (s_phase_done) begin
s_phase_count_d = '0; s_phase_count_d = '0;
if ((s_bit_action_q == BIT_TX) || (s_bit_action_q == BIT_RX)) begin if ((s_bit_action_q == BIT_TX) || (s_bit_action_q == BIT_RX)) begin
@@ -418,22 +418,22 @@ module i2c_core (
end else begin end else begin
addr_nack_event_o = 1'b1; addr_nack_event_o = 1'b1;
end end
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_rx_overflow_d = 1'b0; s_rx_overflow_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
end else begin end else begin
unique case (s_byte_role_q) unique case (s_byte_role_q)
BYTE_ADDR_7, BYTE_ADDR_10_HEADER_R: begin BYTE_ADDR_7, BYTE_ADDR_10_HEADER_R: begin
s_bit_index_d = 3'd7; s_bit_index_d = 3'd7;
if (s_command_q[8]) begin if (s_cmd_q[8]) begin
s_bit_action_d = BIT_RX; s_bit_action_d = BIT_RX;
s_byte_role_d = BYTE_READ; s_byte_role_d = BYTE_READ;
s_rx_byte_d = '0; s_rx_byte_d = '0;
end else begin end else begin
s_bit_action_d = BIT_TX; s_bit_action_d = BIT_TX;
s_byte_role_d = BYTE_WRITE; s_byte_role_d = BYTE_WRITE;
s_tx_byte_d = s_command_q[7:0]; s_tx_byte_d = s_cmd_q[7:0];
end end
s_fsm_d = FSM_BIT_LOW; s_fsm_d = FSM_BIT_LOW;
end end
@@ -445,27 +445,27 @@ module i2c_core (
s_fsm_d = FSM_BIT_LOW; s_fsm_d = FSM_BIT_LOW;
end end
BYTE_ADDR_10_LOW: begin BYTE_ADDR_10_LOW: begin
if (s_command_q[8]) begin if (s_cmd_q[8]) begin
s_read_header_only_d = 1'b1; s_read_header_only_d = 1'b1;
s_fsm_d = FSM_RESTART_LOW; s_fsm_d = FSM_RESTART_LOW;
end else begin end else begin
s_bit_action_d = BIT_TX; s_bit_action_d = BIT_TX;
s_byte_role_d = BYTE_WRITE; s_byte_role_d = BYTE_WRITE;
s_tx_byte_d = s_command_q[7:0]; s_tx_byte_d = s_cmd_q[7:0];
s_bit_index_d = 3'd7; s_bit_index_d = 3'd7;
s_fsm_d = FSM_BIT_LOW; s_fsm_d = FSM_BIT_LOW;
end end
end end
BYTE_WRITE: begin BYTE_WRITE: begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
if (s_command_q[10]) begin if (s_cmd_q[10]) begin
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
end else if (cmd_valid_i) begin end else if (cmd_valid_i) begin
s_command_d = cmd_data_i; s_cmd_d = cmd_data_i;
s_command_active_d = 1'b1; s_cmd_active_d = 1'b1;
s_command_count_d = '0; s_cmd_count_d = '0;
cmd_pop_o = 1'b1; cmd_pop_o = 1'b1;
if (cmd_data_i[9] || (cmd_data_i[8] != s_command_q[8])) begin if (cmd_data_i[9] || (cmd_data_i[8] != s_cmd_q[8])) begin
s_read_header_only_d = 1'b0; s_read_header_only_d = 1'b0;
s_fsm_d = FSM_RESTART_LOW; s_fsm_d = FSM_RESTART_LOW;
end else begin end else begin
@@ -480,7 +480,7 @@ module i2c_core (
end end
end end
default: begin default: begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
command_error_event_o = 1'b1; command_error_event_o = 1'b1;
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
@@ -489,27 +489,27 @@ module i2c_core (
end end
end else begin end else begin
if (s_rx_overflow_q) begin if (s_rx_overflow_q) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_rx_overflow_d = 1'b0; s_rx_overflow_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
rx_overflow_event_o = 1'b1; rx_overflow_event_o = 1'b1;
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
end else begin end else begin
rx_push_o = 1'b1; rx_push_o = 1'b1;
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_rx_overflow_d = 1'b0; s_rx_overflow_d = 1'b0;
if (s_command_q[10]) begin if (s_cmd_q[10]) begin
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
end else if (cmd_valid_i) begin end else if (cmd_valid_i) begin
if (s_command_q[11] && !cmd_data_i[9]) begin if (s_cmd_q[11] && !cmd_data_i[9]) begin
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
command_error_event_o = 1'b1; command_error_event_o = 1'b1;
s_fsm_d = FSM_STOP_LOW; s_fsm_d = FSM_STOP_LOW;
end else begin end else begin
s_command_d = cmd_data_i; s_cmd_d = cmd_data_i;
s_command_active_d = 1'b1; s_cmd_active_d = 1'b1;
s_command_count_d = '0; s_cmd_count_d = '0;
cmd_pop_o = 1'b1; cmd_pop_o = 1'b1;
if (cmd_data_i[9] || !cmd_data_i[8]) begin if (cmd_data_i[9] || !cmd_data_i[8]) begin
s_read_header_only_d = 1'b0; s_read_header_only_d = 1'b0;
s_fsm_d = FSM_RESTART_LOW; s_fsm_d = FSM_RESTART_LOW;
@@ -533,10 +533,10 @@ module i2c_core (
FSM_HOLD: begin FSM_HOLD: begin
if (cmd_valid_i) begin if (cmd_valid_i) begin
s_command_d = cmd_data_i; s_cmd_d = cmd_data_i;
s_command_active_d = 1'b1; s_cmd_active_d = 1'b1;
s_command_count_d = '0; s_cmd_count_d = '0;
cmd_pop_o = 1'b1; cmd_pop_o = 1'b1;
if (cmd_data_i[9]) begin if (cmd_data_i[9]) begin
s_read_header_only_d = 1'b0; s_read_header_only_d = 1'b0;
s_fsm_d = FSM_RESTART_LOW; s_fsm_d = FSM_RESTART_LOW;
@@ -572,7 +572,7 @@ module i2c_core (
s_stretch_count_d = '0; s_stretch_count_d = '0;
s_fsm_d = FSM_STOP_SETUP; s_fsm_d = FSM_STOP_SETUP;
end else if (s_stretch_timeout) begin end else if (s_stretch_timeout) begin
s_command_active_d = 1'b0; s_cmd_active_d = 1'b0;
s_bus_owned_d = 1'b0; s_bus_owned_d = 1'b0;
s_recovery_d = 1'b0; s_recovery_d = 1'b0;
cmd_flush_o = 1'b1; cmd_flush_o = 1'b1;
@@ -669,118 +669,144 @@ module i2c_core (
end end
end end
dffr #($bits( dffr #(
i2c_fsm_t .DATA_WIDTH($bits(i2c_fsm_t))
)) u_fsm_dffr ( ) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d_raw), .dat_i (s_fsm_d_raw),
.dat_o (s_fsm_q_raw) .dat_o (s_fsm_q_raw)
); );
dffr #($bits( dffr #(
i2c_bit_action_t .DATA_WIDTH($bits(i2c_bit_action_t))
)) u_bit_action_dffr ( ) u_bit_action_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bit_action_d_raw), .dat_i (s_bit_action_d_raw),
.dat_o (s_bit_action_q_raw) .dat_o (s_bit_action_q_raw)
); );
dffr #($bits( dffr #(
i2c_byte_role_t .DATA_WIDTH($bits(i2c_byte_role_t))
)) u_byte_role_dffr ( ) u_byte_role_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_byte_role_d_raw), .dat_i (s_byte_role_d_raw),
.dat_o (s_byte_role_q_raw) .dat_o (s_byte_role_q_raw)
); );
dffr #(COUNTER_WIDTH) u_phase_count_dffr ( dffr #(
.DATA_WIDTH(COUNTER_WIDTH)
) u_phase_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_phase_count_d), .dat_i (s_phase_count_d),
.dat_o (s_phase_count_q) .dat_o (s_phase_count_q)
); );
dffr #(COUNTER_WIDTH) u_stretch_count_dffr ( dffr #(
.DATA_WIDTH(COUNTER_WIDTH)
) u_stretch_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_stretch_count_d), .dat_i (s_stretch_count_d),
.dat_o (s_stretch_count_q) .dat_o (s_stretch_count_q)
); );
dffr #(COUNTER_WIDTH) u_command_count_dffr ( dffr #(
.DATA_WIDTH(COUNTER_WIDTH)
) u_command_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_command_count_d), .dat_i (s_cmd_count_d),
.dat_o (s_command_count_q) .dat_o (s_cmd_count_q)
); );
dffr #(12) u_command_dffr ( dffr #(
.DATA_WIDTH(12)
) u_command_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_command_d), .dat_i (s_cmd_d),
.dat_o (s_command_q) .dat_o (s_cmd_q)
); );
dffr #(8) u_tx_byte_dffr ( dffr #(
.DATA_WIDTH(8)
) u_tx_byte_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_tx_byte_d), .dat_i (s_tx_byte_d),
.dat_o (s_tx_byte_q) .dat_o (s_tx_byte_q)
); );
dffr #(8) u_rx_byte_dffr ( dffr #(
.DATA_WIDTH(8)
) u_rx_byte_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rx_byte_d), .dat_i (s_rx_byte_d),
.dat_o (s_rx_byte_q) .dat_o (s_rx_byte_q)
); );
dffr #(3) u_bit_index_dffr ( dffr #(
.DATA_WIDTH(3)
) u_bit_index_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bit_index_d), .dat_i (s_bit_index_d),
.dat_o (s_bit_index_q) .dat_o (s_bit_index_q)
); );
dffr #(4) u_recovery_pulse_dffr ( dffr #(
.DATA_WIDTH(4)
) u_recovery_pulse_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_recovery_pulse_d), .dat_i (s_recovery_pulse_d),
.dat_o (s_recovery_pulse_q) .dat_o (s_recovery_pulse_q)
); );
dffr #(1) u_command_active_dffr ( dffr #(
.DATA_WIDTH(1)
) u_command_active_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_command_active_d), .dat_i (s_cmd_active_d),
.dat_o (s_command_active_q) .dat_o (s_cmd_active_q)
); );
dffr #(1) u_bus_owned_dffr ( dffr #(
.DATA_WIDTH(1)
) u_bus_owned_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bus_owned_d), .dat_i (s_bus_owned_d),
.dat_o (s_bus_owned_q) .dat_o (s_bus_owned_q)
); );
dffr #(1) u_recovery_dffr ( dffr #(
.DATA_WIDTH(1)
) u_recovery_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_recovery_d), .dat_i (s_recovery_d),
.dat_o (s_recovery_q) .dat_o (s_recovery_q)
); );
dffr #(1) u_read_header_only_dffr ( dffr #(
.DATA_WIDTH(1)
) u_read_header_only_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_header_only_d), .dat_i (s_read_header_only_d),
.dat_o (s_read_header_only_q) .dat_o (s_read_header_only_q)
); );
dffr #(1) u_rx_overflow_dffr ( dffr #(
.DATA_WIDTH(1)
) u_rx_overflow_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rx_overflow_d), .dat_i (s_rx_overflow_d),
rtl/ip/ribp/serial/i2c_filter.sv
+6 -2
View File
@@ -78,14 +78,18 @@ module i2c_filter (
.dat_o (s_sda_q) .dat_o (s_sda_q)
); );
dffr #(4) u_scl_count_dffr ( dffr #(
.DATA_WIDTH(4)
) u_scl_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_scl_count_d), .dat_i (s_scl_count_d),
.dat_o (s_scl_count_q) .dat_o (s_scl_count_q)
); );
dffr #(4) u_sda_count_dffr ( dffr #(
.DATA_WIDTH(4)
) u_sda_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sda_count_d), .dat_i (s_sda_count_d),
rtl/ip/ribp/serial/i2c_reg.sv
+226 -197
View File
@@ -70,13 +70,13 @@ module i2c_reg #(
logic s_req; logic s_req;
logic s_write; logic s_write;
logic s_req_accept; logic s_req_accept;
logic s_access_error; logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q; logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q; logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q; logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_enable_en; logic s_en_en;
logic s_enable_d, s_enable_q; logic s_en_d, s_en_q;
logic s_scl_timing_en; logic s_scl_timing_en;
logic [31:0] s_scl_timing_d, s_scl_timing_q; logic [31:0] s_scl_timing_d, s_scl_timing_q;
logic s_start_timing_en; logic s_start_timing_en;
@@ -91,16 +91,16 @@ module i2c_reg #(
logic [23:0] s_stretch_timeout_d, s_stretch_timeout_q; logic [23:0] s_stretch_timeout_d, s_stretch_timeout_q;
logic s_bus_idle_timeout_en; logic s_bus_idle_timeout_en;
logic [23:0] s_bus_idle_timeout_d, s_bus_idle_timeout_q; logic [23:0] s_bus_idle_timeout_d, s_bus_idle_timeout_q;
logic s_command_timeout_en; logic s_cmd_timeout_en;
logic [23:0] s_command_timeout_d, s_command_timeout_q; logic [23:0] s_cmd_timeout_d, s_cmd_timeout_q;
logic s_target_addr_en; logic s_target_addr_en;
logic [10:0] s_target_addr_d, s_target_addr_q; logic [10:0] s_target_addr_d, s_target_addr_q;
logic s_cmd_watermark_en; logic s_cmd_watermark_en;
logic [7:0] s_cmd_watermark_d, s_cmd_watermark_q; logic [7:0] s_cmd_watermark_d, s_cmd_watermark_q;
logic s_rx_watermark_en; logic s_rx_watermark_en;
logic [7:0] s_rx_watermark_d, s_rx_watermark_q; logic [7:0] s_rx_watermark_d, s_rx_watermark_q;
logic s_intr_enable_en; logic s_intr_en_en;
logic [7:0] s_intr_enable_d, s_intr_enable_q; logic [7:0] s_intr_en_d, s_intr_en_q;
logic s_cmd_push; logic s_cmd_push;
logic s_cmd_flush_cmd; logic s_cmd_flush_cmd;
@@ -115,21 +115,21 @@ module i2c_reg #(
logic [ 7:0] s_rx_pop_data; logic [ 7:0] s_rx_pop_data;
logic [ RX_FIFO_LOG_DEPTH:0] s_rx_count; logic [ RX_FIFO_LOG_DEPTH:0] s_rx_count;
logic [10:0] s_error_status_d, s_error_status_q; logic [10:0] s_err_stat_d, s_err_stat_q;
logic [7:0] s_intr_state_d, s_intr_state_q; logic [7:0] s_intr_state_d, s_intr_state_q;
logic [10:0] s_error_clear; logic [10:0] s_err_clear;
logic [ 7:0] s_intr_clear; logic [ 7:0] s_intr_clear;
logic [ 7:0] s_intr_test; logic [ 7:0] s_intr_test;
logic s_config_error_event; logic s_config_err_event;
logic s_sw_command_error_event; logic s_sw_cmd_err_event;
logic s_timeout_event; logic s_timeout_event;
logic s_error_event; logic s_err_event;
logic s_cmd_watermark_active; logic s_cmd_watermark_active;
logic s_rx_watermark_active; logic s_rx_watermark_active;
logic s_tx_dma_req; logic s_tx_dma_req;
logic s_rx_dma_req; logic s_rx_dma_req;
logic s_config_valid; logic s_config_valid;
logic [31:0] s_status; logic [31:0] s_stat;
logic [31:0] s_fifo_level; logic [31:0] s_fifo_level;
logic [31:0] s_line_state; logic [31:0] s_line_state;
logic [31:0] s_merge_value; logic [31:0] s_merge_value;
@@ -160,7 +160,7 @@ module i2c_reg #(
assign ribp.ready = s_ribp_ready_q; assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = s_ribp_resp_err_q; assign ribp.resp_err = s_ribp_resp_err_q;
assign ribp.rdata = s_ribp_rdata_q; assign ribp.rdata = s_ribp_rdata_q;
assign enable_o = s_enable_q; assign enable_o = s_en_q;
assign scl_low_cycles_o = s_scl_timing_q[15:0]; assign scl_low_cycles_o = s_scl_timing_q[15:0];
assign scl_high_cycles_o = s_scl_timing_q[31:16]; assign scl_high_cycles_o = s_scl_timing_q[31:16];
assign start_hold_cycles_o = s_start_timing_q[15:0]; assign start_hold_cycles_o = s_start_timing_q[15:0];
@@ -173,7 +173,7 @@ module i2c_reg #(
assign sda_filter_cycles_o = s_filter_q[11:8]; assign sda_filter_cycles_o = s_filter_q[11:8];
assign stretch_timeout_o = s_stretch_timeout_q; assign stretch_timeout_o = s_stretch_timeout_q;
assign bus_idle_timeout_o = s_bus_idle_timeout_q; assign bus_idle_timeout_o = s_bus_idle_timeout_q;
assign command_timeout_o = s_command_timeout_q; assign command_timeout_o = s_cmd_timeout_q;
assign target_addr_o = s_target_addr_q[9:0]; assign target_addr_o = s_target_addr_q[9:0];
assign ten_bit_o = s_target_addr_q[10]; assign ten_bit_o = s_target_addr_q[10];
assign cmd_valid_o = !s_cmd_empty; assign cmd_valid_o = !s_cmd_empty;
@@ -190,129 +190,129 @@ module i2c_reg #(
(s_stop_timing_q[15:0] != 16'd0) && (s_stop_timing_q[15:0] != 16'd0) &&
(s_stop_timing_q[31:16] != 16'd0) && (s_stop_timing_q[31:16] != 16'd0) &&
(s_target_addr_q[10] || (s_target_addr_q[9:7] == 3'd0)); (s_target_addr_q[10] || (s_target_addr_q[9:7] == 3'd0));
assign s_cmd_watermark_active = s_enable_q && (8'(s_cmd_count) <= s_cmd_watermark_q); assign s_cmd_watermark_active = s_en_q && (8'(s_cmd_count) <= s_cmd_watermark_q);
assign s_rx_watermark_active = s_enable_q && (8'(s_rx_count) >= s_rx_watermark_q); assign s_rx_watermark_active = s_en_q && (8'(s_rx_count) >= s_rx_watermark_q);
assign s_tx_dma_req = s_enable_q && s_config_valid && !s_cmd_full; assign s_tx_dma_req = s_en_q && s_config_valid && !s_cmd_full;
assign s_rx_dma_req = s_enable_q && !s_rx_empty; assign s_rx_dma_req = s_en_q && !s_rx_empty;
assign dma_tx_stall_o = !s_tx_dma_req; assign dma_tx_stall_o = !s_tx_dma_req;
assign dma_rx_stall_o = !s_rx_dma_req; assign dma_rx_stall_o = !s_rx_dma_req;
assign irq_o = |(s_intr_state_q & s_intr_enable_q); assign irq_o = |(s_intr_state_q & s_intr_en_q);
always_comb begin always_comb begin
s_status = '0; s_stat = '0;
s_status[`I2C_STATUS_ENABLE] = s_enable_q; s_stat[`I2C_STATUS_ENABLE] = s_en_q;
s_status[`I2C_STATUS_BUSY] = busy_i; s_stat[`I2C_STATUS_BUSY] = busy_i;
s_status[`I2C_STATUS_BUS_BUSY] = !(scl_i && sda_i); s_stat[`I2C_STATUS_BUS_BUSY] = !(scl_i && sda_i);
s_status[`I2C_STATUS_CMD_EMPTY] = s_cmd_empty; s_stat[`I2C_STATUS_CMD_EMPTY] = s_cmd_empty;
s_status[`I2C_STATUS_CMD_FULL] = s_cmd_full; s_stat[`I2C_STATUS_CMD_FULL] = s_cmd_full;
s_status[`I2C_STATUS_RX_EMPTY] = s_rx_empty; s_stat[`I2C_STATUS_RX_EMPTY] = s_rx_empty;
s_status[`I2C_STATUS_RX_FULL] = s_rx_full; s_stat[`I2C_STATUS_RX_FULL] = s_rx_full;
s_status[`I2C_STATUS_CONFIG_VALID] = s_config_valid; s_stat[`I2C_STATUS_CONFIG_VALID] = s_config_valid;
s_status[`I2C_STATUS_RECOVERY_ACTIVE] = recovery_active_i; s_stat[`I2C_STATUS_RECOVERY_ACTIVE] = recovery_active_i;
s_status[`I2C_STATUS_SCL] = scl_i; s_stat[`I2C_STATUS_SCL] = scl_i;
s_status[`I2C_STATUS_SDA] = sda_i; s_stat[`I2C_STATUS_SDA] = sda_i;
s_status[`I2C_STATUS_TX_DMA_REQ] = s_tx_dma_req; s_stat[`I2C_STATUS_TX_DMA_REQ] = s_tx_dma_req;
s_status[`I2C_STATUS_RX_DMA_REQ] = s_rx_dma_req; s_stat[`I2C_STATUS_RX_DMA_REQ] = s_rx_dma_req;
s_fifo_level = '0; s_fifo_level = '0;
s_fifo_level[7:0] = 8'(s_cmd_count); s_fifo_level[7:0] = 8'(s_cmd_count);
s_fifo_level[23:16] = 8'(s_rx_count); s_fifo_level[23:16] = 8'(s_rx_count);
s_line_state = '0; s_line_state = '0;
s_line_state[`I2C_LINE_SCL] = scl_i; s_line_state[`I2C_LINE_SCL] = scl_i;
s_line_state[`I2C_LINE_SDA] = sda_i; s_line_state[`I2C_LINE_SDA] = sda_i;
s_line_state[`I2C_LINE_BUS_FREE] = scl_i && sda_i; s_line_state[`I2C_LINE_BUS_FREE] = scl_i && sda_i;
end end
always_comb begin always_comb begin
s_req_accept = s_req; s_req_accept = s_req;
s_access_error = 1'b0; s_access_err = 1'b0;
s_enable_en = 1'b0; s_en_en = 1'b0;
s_scl_timing_en = 1'b0; s_scl_timing_en = 1'b0;
s_start_timing_en = 1'b0; s_start_timing_en = 1'b0;
s_data_timing_en = 1'b0; s_data_timing_en = 1'b0;
s_stop_timing_en = 1'b0; s_stop_timing_en = 1'b0;
s_filter_en = 1'b0; s_filter_en = 1'b0;
s_stretch_timeout_en = 1'b0; s_stretch_timeout_en = 1'b0;
s_bus_idle_timeout_en = 1'b0; s_bus_idle_timeout_en = 1'b0;
s_command_timeout_en = 1'b0; s_cmd_timeout_en = 1'b0;
s_target_addr_en = 1'b0; s_target_addr_en = 1'b0;
s_cmd_watermark_en = 1'b0; s_cmd_watermark_en = 1'b0;
s_rx_watermark_en = 1'b0; s_rx_watermark_en = 1'b0;
s_intr_enable_en = 1'b0; s_intr_en_en = 1'b0;
s_enable_d = s_enable_q; s_en_d = s_en_q;
s_scl_timing_d = s_scl_timing_q; s_scl_timing_d = s_scl_timing_q;
s_start_timing_d = s_start_timing_q; s_start_timing_d = s_start_timing_q;
s_data_timing_d = s_data_timing_q; s_data_timing_d = s_data_timing_q;
s_stop_timing_d = s_stop_timing_q; s_stop_timing_d = s_stop_timing_q;
s_filter_d = s_filter_q; s_filter_d = s_filter_q;
s_stretch_timeout_d = s_stretch_timeout_q; s_stretch_timeout_d = s_stretch_timeout_q;
s_bus_idle_timeout_d = s_bus_idle_timeout_q; s_bus_idle_timeout_d = s_bus_idle_timeout_q;
s_command_timeout_d = s_command_timeout_q; s_cmd_timeout_d = s_cmd_timeout_q;
s_target_addr_d = s_target_addr_q; s_target_addr_d = s_target_addr_q;
s_cmd_watermark_d = s_cmd_watermark_q; s_cmd_watermark_d = s_cmd_watermark_q;
s_rx_watermark_d = s_rx_watermark_q; s_rx_watermark_d = s_rx_watermark_q;
s_intr_enable_d = s_intr_enable_q; s_intr_en_d = s_intr_en_q;
s_cmd_push = 1'b0; s_cmd_push = 1'b0;
s_rx_pop = 1'b0; s_rx_pop = 1'b0;
s_cmd_flush_cmd = 1'b0; s_cmd_flush_cmd = 1'b0;
s_rx_flush_cmd = 1'b0; s_rx_flush_cmd = 1'b0;
abort_o = 1'b0; abort_o = 1'b0;
recover_o = 1'b0; recover_o = 1'b0;
s_error_clear = '0; s_err_clear = '0;
s_intr_clear = '0; s_intr_clear = '0;
s_intr_test = '0; s_intr_test = '0;
s_config_error_event = 1'b0; s_config_err_event = 1'b0;
s_sw_command_error_event = 1'b0; s_sw_cmd_err_event = 1'b0;
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
s_merge_value = '0; s_merge_value = '0;
if (s_req) begin if (s_req) begin
if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else if (s_write) begin end else if (s_write) begin
unique case (ribp.addr[7:0]) unique case (ribp.addr[7:0])
`RIBP_I2C_CTRL: begin `RIBP_I2C_CTRL: begin
s_merge_value = merge_wstrb({31'd0, s_enable_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({31'd0, s_en_q}, ribp.wdata, ribp.wstrb);
if ((s_merge_value[31:1] != 31'd0) || if ((s_merge_value[31:1] != 31'd0) ||
(s_merge_value[0] && !s_config_valid) || (s_merge_value[0] && !s_config_valid) ||
(!s_merge_value[0] && (busy_i || recovery_active_i))) begin (!s_merge_value[0] && (busy_i || recovery_active_i))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_enable_en = 1'b1; s_en_en = 1'b1;
s_enable_d = s_merge_value[0]; s_en_d = s_merge_value[0];
end end
end end
`RIBP_I2C_SCL_TIMING: begin `RIBP_I2C_SCL_TIMING: begin
if (s_enable_q || busy_i || recovery_active_i) begin if (s_en_q || busy_i || recovery_active_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_scl_timing_en = 1'b1; s_scl_timing_en = 1'b1;
s_scl_timing_d = merge_wstrb(s_scl_timing_q, ribp.wdata, ribp.wstrb); s_scl_timing_d = merge_wstrb(s_scl_timing_q, ribp.wdata, ribp.wstrb);
end end
end end
`RIBP_I2C_START_TIMING: begin `RIBP_I2C_START_TIMING: begin
if (s_enable_q || busy_i || recovery_active_i) begin if (s_en_q || busy_i || recovery_active_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_start_timing_en = 1'b1; s_start_timing_en = 1'b1;
s_start_timing_d = merge_wstrb(s_start_timing_q, ribp.wdata, ribp.wstrb); s_start_timing_d = merge_wstrb(s_start_timing_q, ribp.wdata, ribp.wstrb);
end end
end end
`RIBP_I2C_DATA_TIMING: begin `RIBP_I2C_DATA_TIMING: begin
if (s_enable_q || busy_i || recovery_active_i) begin if (s_en_q || busy_i || recovery_active_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_data_timing_en = 1'b1; s_data_timing_en = 1'b1;
s_data_timing_d = merge_wstrb(s_data_timing_q, ribp.wdata, ribp.wstrb); s_data_timing_d = merge_wstrb(s_data_timing_q, ribp.wdata, ribp.wstrb);
end end
end end
`RIBP_I2C_STOP_TIMING: begin `RIBP_I2C_STOP_TIMING: begin
if (s_enable_q || busy_i || recovery_active_i) begin if (s_en_q || busy_i || recovery_active_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_stop_timing_en = 1'b1; s_stop_timing_en = 1'b1;
s_stop_timing_d = merge_wstrb(s_stop_timing_q, ribp.wdata, ribp.wstrb); s_stop_timing_d = merge_wstrb(s_stop_timing_q, ribp.wdata, ribp.wstrb);
@@ -320,10 +320,10 @@ module i2c_reg #(
end end
`RIBP_I2C_FILTER: begin `RIBP_I2C_FILTER: begin
s_merge_value = merge_wstrb({20'd0, s_filter_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({20'd0, s_filter_q}, ribp.wdata, ribp.wstrb);
if (s_enable_q || busy_i || recovery_active_i || if (s_en_q || busy_i || recovery_active_i ||
(s_merge_value[31:12] != 20'd0) || (s_merge_value[7:4] != 4'd0)) begin (s_merge_value[31:12] != 20'd0) || (s_merge_value[7:4] != 4'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_filter_en = 1'b1; s_filter_en = 1'b1;
s_filter_d = s_merge_value[11:0]; s_filter_d = s_merge_value[11:0];
@@ -331,9 +331,9 @@ module i2c_reg #(
end end
`RIBP_I2C_STRETCH_TIMEOUT: begin `RIBP_I2C_STRETCH_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_stretch_timeout_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({8'd0, s_stretch_timeout_q}, ribp.wdata, ribp.wstrb);
if (s_enable_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin if (s_en_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_stretch_timeout_en = 1'b1; s_stretch_timeout_en = 1'b1;
s_stretch_timeout_d = s_merge_value[23:0]; s_stretch_timeout_d = s_merge_value[23:0];
@@ -341,22 +341,22 @@ module i2c_reg #(
end end
`RIBP_I2C_BUS_IDLE_TIMEOUT: begin `RIBP_I2C_BUS_IDLE_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_bus_idle_timeout_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({8'd0, s_bus_idle_timeout_q}, ribp.wdata, ribp.wstrb);
if (s_enable_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin if (s_en_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_bus_idle_timeout_en = 1'b1; s_bus_idle_timeout_en = 1'b1;
s_bus_idle_timeout_d = s_merge_value[23:0]; s_bus_idle_timeout_d = s_merge_value[23:0];
end end
end end
`RIBP_I2C_COMMAND_TIMEOUT: begin `RIBP_I2C_COMMAND_TIMEOUT: begin
s_merge_value = merge_wstrb({8'd0, s_command_timeout_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({8'd0, s_cmd_timeout_q}, ribp.wdata, ribp.wstrb);
if (s_enable_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin if (s_en_q || busy_i || recovery_active_i || (s_merge_value[31:24] != 8'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_command_timeout_en = 1'b1; s_cmd_timeout_en = 1'b1;
s_command_timeout_d = s_merge_value[23:0]; s_cmd_timeout_d = s_merge_value[23:0];
end end
end end
`RIBP_I2C_TARGET_ADDR: begin `RIBP_I2C_TARGET_ADDR: begin
@@ -364,8 +364,8 @@ module i2c_reg #(
if (busy_i || recovery_active_i || !s_cmd_empty || if (busy_i || recovery_active_i || !s_cmd_empty ||
(s_merge_value[31:11] != 21'd0) || (s_merge_value[31:11] != 21'd0) ||
(!s_merge_value[10] && (s_merge_value[9:7] != 3'd0))) begin (!s_merge_value[10] && (s_merge_value[9:7] != 3'd0))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_target_addr_en = 1'b1; s_target_addr_en = 1'b1;
s_target_addr_d = s_merge_value[10:0]; s_target_addr_d = s_merge_value[10:0];
@@ -377,39 +377,39 @@ module i2c_reg #(
ribp.wdata[`I2C_DATA_CMD_NACK_LAST]) || ribp.wdata[`I2C_DATA_CMD_NACK_LAST]) ||
(ribp.wdata[`I2C_DATA_CMD_READ] && ribp.wdata[`I2C_DATA_CMD_STOP] && (ribp.wdata[`I2C_DATA_CMD_READ] && ribp.wdata[`I2C_DATA_CMD_STOP] &&
!ribp.wdata[`I2C_DATA_CMD_NACK_LAST])) begin !ribp.wdata[`I2C_DATA_CMD_NACK_LAST])) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else if (s_cmd_full && s_enable_q && s_config_valid) begin end else if (s_cmd_full && s_en_q && s_config_valid) begin
s_req_accept = 1'b0; s_req_accept = 1'b0;
end else if (s_cmd_full) begin end else if (s_cmd_full) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
s_cmd_push = 1'b1; s_cmd_push = 1'b1;
end end
end end
`RIBP_I2C_COMMAND: begin `RIBP_I2C_COMMAND: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:4] != 28'd0) || (ribp.wdata[3:0] == 4'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:4] != 28'd0) || (ribp.wdata[3:0] == 4'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else if (ribp.wdata[`I2C_COMMAND_ABORT]) begin end else if (ribp.wdata[`I2C_COMMAND_ABORT]) begin
if ((ribp.wdata[3:0] != 4'b0001) || (!busy_i && !recovery_active_i)) begin if ((ribp.wdata[3:0] != 4'b0001) || (!busy_i && !recovery_active_i)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
abort_o = 1'b1; abort_o = 1'b1;
end end
end else if (ribp.wdata[`I2C_COMMAND_RECOVER]) begin end else if (ribp.wdata[`I2C_COMMAND_RECOVER]) begin
if ((ribp.wdata[3:0] != 4'b0010) || !s_enable_q || !s_config_valid || if ((ribp.wdata[3:0] != 4'b0010) || !s_en_q || !s_config_valid ||
busy_i || recovery_active_i || !s_cmd_empty) begin busy_i || recovery_active_i || !s_cmd_empty) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
recover_o = 1'b1; recover_o = 1'b1;
end end
end else if (busy_i || recovery_active_i || (ribp.wdata[1:0] != 2'd0)) begin end else if (busy_i || recovery_active_i || (ribp.wdata[1:0] != 2'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
s_cmd_flush_cmd = ribp.wdata[`I2C_COMMAND_CMD_FLUSH]; s_cmd_flush_cmd = ribp.wdata[`I2C_COMMAND_CMD_FLUSH];
s_rx_flush_cmd = ribp.wdata[`I2C_COMMAND_RX_FLUSH]; s_rx_flush_cmd = ribp.wdata[`I2C_COMMAND_RX_FLUSH];
@@ -418,8 +418,8 @@ module i2c_reg #(
`RIBP_I2C_CMD_WATERMARK: begin `RIBP_I2C_CMD_WATERMARK: begin
s_merge_value = merge_wstrb({24'd0, s_cmd_watermark_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({24'd0, s_cmd_watermark_q}, ribp.wdata, ribp.wstrb);
if ((s_merge_value[31:8] != 24'd0) || (s_merge_value[7:0] >= CMD_DEPTH_INFO)) begin if ((s_merge_value[31:8] != 24'd0) || (s_merge_value[7:0] >= CMD_DEPTH_INFO)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
s_cmd_watermark_en = 1'b1; s_cmd_watermark_en = 1'b1;
s_cmd_watermark_d = s_merge_value[7:0]; s_cmd_watermark_d = s_merge_value[7:0];
@@ -429,8 +429,8 @@ module i2c_reg #(
s_merge_value = merge_wstrb({24'd0, s_rx_watermark_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({24'd0, s_rx_watermark_q}, ribp.wdata, ribp.wstrb);
if ((s_merge_value[31:8] != 24'd0) || (s_merge_value[7:0] == 8'd0) || if ((s_merge_value[31:8] != 24'd0) || (s_merge_value[7:0] == 8'd0) ||
(s_merge_value[7:0] > RX_DEPTH_INFO)) begin (s_merge_value[7:0] > RX_DEPTH_INFO)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
s_rx_watermark_en = 1'b1; s_rx_watermark_en = 1'b1;
s_rx_watermark_d = s_merge_value[7:0]; s_rx_watermark_d = s_merge_value[7:0];
@@ -438,39 +438,39 @@ module i2c_reg #(
end end
`RIBP_I2C_ERROR_STATUS: begin `RIBP_I2C_ERROR_STATUS: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:11] != 21'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:11] != 21'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_error_clear = ribp.wdata[10:0]; s_err_clear = ribp.wdata[10:0];
end end
end end
`RIBP_I2C_INTR_STATE: begin `RIBP_I2C_INTR_STATE: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:8] != 24'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:8] != 24'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_clear = ribp.wdata[7:0]; s_intr_clear = ribp.wdata[7:0];
end end
end end
`RIBP_I2C_INTR_ENABLE: begin `RIBP_I2C_INTR_ENABLE: begin
s_merge_value = merge_wstrb({24'd0, s_intr_enable_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({24'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb);
if (s_merge_value[31:8] != 24'd0) begin if (s_merge_value[31:8] != 24'd0) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = s_merge_value[7:0]; s_intr_en_d = s_merge_value[7:0];
end end
end end
`RIBP_I2C_INTR_TEST: begin `RIBP_I2C_INTR_TEST: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:8] != 24'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:8] != 24'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_test = ribp.wdata[7:0]; s_intr_test = ribp.wdata[7:0];
end end
end end
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end else begin end else begin
unique case (ribp.addr[7:0]) unique case (ribp.addr[7:0])
`RIBP_I2C_CTRL: s_ribp_rdata_d = {31'd0, s_enable_q}; `RIBP_I2C_CTRL: s_ribp_rdata_d = {31'd0, s_en_q};
`RIBP_I2C_SCL_TIMING: s_ribp_rdata_d = s_scl_timing_q; `RIBP_I2C_SCL_TIMING: s_ribp_rdata_d = s_scl_timing_q;
`RIBP_I2C_START_TIMING: s_ribp_rdata_d = s_start_timing_q; `RIBP_I2C_START_TIMING: s_ribp_rdata_d = s_start_timing_q;
`RIBP_I2C_DATA_TIMING: s_ribp_rdata_d = s_data_timing_q; `RIBP_I2C_DATA_TIMING: s_ribp_rdata_d = s_data_timing_q;
@@ -478,30 +478,30 @@ module i2c_reg #(
`RIBP_I2C_FILTER: s_ribp_rdata_d = {20'd0, s_filter_q}; `RIBP_I2C_FILTER: s_ribp_rdata_d = {20'd0, s_filter_q};
`RIBP_I2C_STRETCH_TIMEOUT: s_ribp_rdata_d = {8'd0, s_stretch_timeout_q}; `RIBP_I2C_STRETCH_TIMEOUT: s_ribp_rdata_d = {8'd0, s_stretch_timeout_q};
`RIBP_I2C_BUS_IDLE_TIMEOUT: s_ribp_rdata_d = {8'd0, s_bus_idle_timeout_q}; `RIBP_I2C_BUS_IDLE_TIMEOUT: s_ribp_rdata_d = {8'd0, s_bus_idle_timeout_q};
`RIBP_I2C_COMMAND_TIMEOUT: s_ribp_rdata_d = {8'd0, s_command_timeout_q}; `RIBP_I2C_COMMAND_TIMEOUT: s_ribp_rdata_d = {8'd0, s_cmd_timeout_q};
`RIBP_I2C_TARGET_ADDR: s_ribp_rdata_d = {21'd0, s_target_addr_q}; `RIBP_I2C_TARGET_ADDR: s_ribp_rdata_d = {21'd0, s_target_addr_q};
`RIBP_I2C_RXDATA: begin `RIBP_I2C_RXDATA: begin
if (s_rx_empty) begin if (s_rx_empty) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_sw_command_error_event = 1'b1; s_sw_cmd_err_event = 1'b1;
end else begin end else begin
s_ribp_rdata_d = {24'd0, s_rx_pop_data}; s_ribp_rdata_d = {24'd0, s_rx_pop_data};
s_rx_pop = 1'b1; s_rx_pop = 1'b1;
end end
end end
`RIBP_I2C_STATUS: s_ribp_rdata_d = s_status; `RIBP_I2C_STATUS: s_ribp_rdata_d = s_stat;
`RIBP_I2C_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level; `RIBP_I2C_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level;
`RIBP_I2C_CMD_WATERMARK: s_ribp_rdata_d = {24'd0, s_cmd_watermark_q}; `RIBP_I2C_CMD_WATERMARK: s_ribp_rdata_d = {24'd0, s_cmd_watermark_q};
`RIBP_I2C_RX_WATERMARK: s_ribp_rdata_d = {24'd0, s_rx_watermark_q}; `RIBP_I2C_RX_WATERMARK: s_ribp_rdata_d = {24'd0, s_rx_watermark_q};
`RIBP_I2C_ERROR_STATUS: s_ribp_rdata_d = {21'd0, s_error_status_q}; `RIBP_I2C_ERROR_STATUS: s_ribp_rdata_d = {21'd0, s_err_stat_q};
`RIBP_I2C_INTR_STATE: s_ribp_rdata_d = {24'd0, s_intr_state_q}; `RIBP_I2C_INTR_STATE: s_ribp_rdata_d = {24'd0, s_intr_state_q};
`RIBP_I2C_INTR_ENABLE: s_ribp_rdata_d = {24'd0, s_intr_enable_q}; `RIBP_I2C_INTR_ENABLE: s_ribp_rdata_d = {24'd0, s_intr_en_q};
`RIBP_I2C_INTR_STATUS: s_ribp_rdata_d = {24'd0, (s_intr_state_q & s_intr_enable_q)}; `RIBP_I2C_INTR_STATUS: s_ribp_rdata_d = {24'd0, (s_intr_state_q & s_intr_en_q)};
`RIBP_I2C_LINE_STATE: s_ribp_rdata_d = s_line_state; `RIBP_I2C_LINE_STATE: s_ribp_rdata_d = s_line_state;
`RIBP_I2C_IP_VERSION: s_ribp_rdata_d = IP_VERSION; `RIBP_I2C_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_I2C_CAPABILITY: s_ribp_rdata_d = CAPABILITY; `RIBP_I2C_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
default: begin default: begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
end end
endcase endcase
@@ -510,22 +510,28 @@ module i2c_reg #(
end end
assign s_ribp_ready_d = s_req_accept; assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_error; assign s_ribp_resp_err_d = s_access_err;
dffr #(1) u_ribp_ready_dffr ( dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d), .dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q) .dat_o (s_ribp_ready_q)
); );
dffer #(1) u_ribp_resp_err_dffer ( dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d), .dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q) .dat_o (s_ribp_resp_err_q)
); );
dffer #(32) u_ribp_rdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
@@ -533,35 +539,45 @@ module i2c_reg #(
.dat_o (s_ribp_rdata_q) .dat_o (s_ribp_rdata_q)
); );
dffer #(1) u_enable_dffer ( dffer #(
.DATA_WIDTH(1)
) u_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_enable_en), .en_i (s_en_en),
.dat_i (s_enable_d), .dat_i (s_en_d),
.dat_o (s_enable_q) .dat_o (s_en_q)
); );
dffer #(32) u_scl_timing_dffer ( dffer #(
.DATA_WIDTH(32)
) u_scl_timing_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_scl_timing_en), .en_i (s_scl_timing_en),
.dat_i (s_scl_timing_d), .dat_i (s_scl_timing_d),
.dat_o (s_scl_timing_q) .dat_o (s_scl_timing_q)
); );
dffer #(32) u_start_timing_dffer ( dffer #(
.DATA_WIDTH(32)
) u_start_timing_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_start_timing_en), .en_i (s_start_timing_en),
.dat_i (s_start_timing_d), .dat_i (s_start_timing_d),
.dat_o (s_start_timing_q) .dat_o (s_start_timing_q)
); );
dffer #(32) u_data_timing_dffer ( dffer #(
.DATA_WIDTH(32)
) u_data_timing_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_data_timing_en), .en_i (s_data_timing_en),
.dat_i (s_data_timing_d), .dat_i (s_data_timing_d),
.dat_o (s_data_timing_q) .dat_o (s_data_timing_q)
); );
dffer #(32) u_stop_timing_dffer ( dffer #(
.DATA_WIDTH(32)
) u_stop_timing_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_stop_timing_en), .en_i (s_stop_timing_en),
@@ -578,28 +594,36 @@ module i2c_reg #(
.dat_i (s_filter_d), .dat_i (s_filter_d),
.dat_o (s_filter_q) .dat_o (s_filter_q)
); );
dffer #(24) u_stretch_timeout_dffer ( dffer #(
.DATA_WIDTH(24)
) u_stretch_timeout_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_stretch_timeout_en), .en_i (s_stretch_timeout_en),
.dat_i (s_stretch_timeout_d), .dat_i (s_stretch_timeout_d),
.dat_o (s_stretch_timeout_q) .dat_o (s_stretch_timeout_q)
); );
dffer #(24) u_bus_idle_timeout_dffer ( dffer #(
.DATA_WIDTH(24)
) u_bus_idle_timeout_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_bus_idle_timeout_en), .en_i (s_bus_idle_timeout_en),
.dat_i (s_bus_idle_timeout_d), .dat_i (s_bus_idle_timeout_d),
.dat_o (s_bus_idle_timeout_q) .dat_o (s_bus_idle_timeout_q)
); );
dffer #(24) u_command_timeout_dffer ( dffer #(
.DATA_WIDTH(24)
) u_command_timeout_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_command_timeout_en), .en_i (s_cmd_timeout_en),
.dat_i (s_command_timeout_d), .dat_i (s_cmd_timeout_d),
.dat_o (s_command_timeout_q) .dat_o (s_cmd_timeout_q)
); );
dffer #(11) u_target_addr_dffer ( dffer #(
.DATA_WIDTH(11)
) u_target_addr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_target_addr_en), .en_i (s_target_addr_en),
@@ -626,12 +650,14 @@ module i2c_reg #(
.dat_i (s_rx_watermark_d), .dat_i (s_rx_watermark_d),
.dat_o (s_rx_watermark_q) .dat_o (s_rx_watermark_q)
); );
dffer #(8) u_intr_enable_dffer ( dffer #(
.DATA_WIDTH(8)
) u_intr_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_enable_en), .en_i (s_intr_en_en),
.dat_i (s_intr_enable_d), .dat_i (s_intr_en_d),
.dat_o (s_intr_enable_q) .dat_o (s_intr_en_q)
); );
fifo #( fifo #(
@@ -670,31 +696,32 @@ module i2c_reg #(
assign s_timeout_event = stretch_timeout_event_i || bus_timeout_event_i || assign s_timeout_event = stretch_timeout_event_i || bus_timeout_event_i ||
command_timeout_event_i; command_timeout_event_i;
assign s_error_event = addr_nack_event_i || data_nack_event_i || arb_lost_event_i || assign s_err_event = addr_nack_event_i || data_nack_event_i || arb_lost_event_i ||
s_timeout_event || command_error_event_i || s_timeout_event || command_error_event_i ||
s_sw_command_error_event || rx_overflow_event_i || s_sw_cmd_err_event || rx_overflow_event_i ||
s_config_error_event || aborted_event_i || recovery_failed_event_i; s_config_err_event || aborted_event_i || recovery_failed_event_i;
always_comb begin always_comb begin
s_error_status_d = s_error_status_q & ~s_error_clear; s_err_stat_d = s_err_stat_q & ~s_err_clear;
if (addr_nack_event_i) s_error_status_d[`I2C_ERROR_ADDR_NACK] = 1'b1; if (addr_nack_event_i) s_err_stat_d[`I2C_ERROR_ADDR_NACK] = 1'b1;
if (data_nack_event_i) s_error_status_d[`I2C_ERROR_DATA_NACK] = 1'b1; if (data_nack_event_i) s_err_stat_d[`I2C_ERROR_DATA_NACK] = 1'b1;
if (arb_lost_event_i) s_error_status_d[`I2C_ERROR_ARB_LOST] = 1'b1; if (arb_lost_event_i) s_err_stat_d[`I2C_ERROR_ARB_LOST] = 1'b1;
if (stretch_timeout_event_i) s_error_status_d[`I2C_ERROR_STRETCH_TIMEOUT] = 1'b1; if (stretch_timeout_event_i) s_err_stat_d[`I2C_ERROR_STRETCH_TIMEOUT] = 1'b1;
if (bus_timeout_event_i) s_error_status_d[`I2C_ERROR_BUS_TIMEOUT] = 1'b1; if (bus_timeout_event_i) s_err_stat_d[`I2C_ERROR_BUS_TIMEOUT] = 1'b1;
if (command_timeout_event_i) s_error_status_d[`I2C_ERROR_COMMAND_TIMEOUT] = 1'b1; if (command_timeout_event_i) s_err_stat_d[`I2C_ERROR_COMMAND_TIMEOUT] = 1'b1;
if (command_error_event_i || s_sw_command_error_event) if (command_error_event_i || s_sw_cmd_err_event) s_err_stat_d[`I2C_ERROR_COMMAND] = 1'b1;
s_error_status_d[`I2C_ERROR_COMMAND] = 1'b1; if (rx_overflow_event_i) s_err_stat_d[`I2C_ERROR_RX_OVERFLOW] = 1'b1;
if (rx_overflow_event_i) s_error_status_d[`I2C_ERROR_RX_OVERFLOW] = 1'b1; if (s_config_err_event) s_err_stat_d[`I2C_ERROR_CONFIG] = 1'b1;
if (s_config_error_event) s_error_status_d[`I2C_ERROR_CONFIG] = 1'b1; if (aborted_event_i) s_err_stat_d[`I2C_ERROR_ABORTED] = 1'b1;
if (aborted_event_i) s_error_status_d[`I2C_ERROR_ABORTED] = 1'b1; if (recovery_failed_event_i) s_err_stat_d[`I2C_ERROR_RECOVERY_FAILED] = 1'b1;
if (recovery_failed_event_i) s_error_status_d[`I2C_ERROR_RECOVERY_FAILED] = 1'b1;
end end
dffr #(11) u_error_status_dffr ( dffr #(
.DATA_WIDTH(11)
) u_error_status_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_error_status_d), .dat_i (s_err_stat_d),
.dat_o (s_error_status_q) .dat_o (s_err_stat_q)
); );
always_comb begin always_comb begin
@@ -705,10 +732,12 @@ module i2c_reg #(
if (addr_nack_event_i || data_nack_event_i) s_intr_state_d[`I2C_INTR_NACK] = 1'b1; if (addr_nack_event_i || data_nack_event_i) s_intr_state_d[`I2C_INTR_NACK] = 1'b1;
if (arb_lost_event_i) s_intr_state_d[`I2C_INTR_ARB_LOST] = 1'b1; if (arb_lost_event_i) s_intr_state_d[`I2C_INTR_ARB_LOST] = 1'b1;
if (s_timeout_event) s_intr_state_d[`I2C_INTR_TIMEOUT] = 1'b1; if (s_timeout_event) s_intr_state_d[`I2C_INTR_TIMEOUT] = 1'b1;
if (s_error_event) s_intr_state_d[`I2C_INTR_ERROR] = 1'b1; if (s_err_event) s_intr_state_d[`I2C_INTR_ERROR] = 1'b1;
if (recovery_done_event_i) s_intr_state_d[`I2C_INTR_RECOVERY_DONE] = 1'b1; if (recovery_done_event_i) s_intr_state_d[`I2C_INTR_RECOVERY_DONE] = 1'b1;
end end
dffr #(8) u_intr_state_dffr ( dffr #(
.DATA_WIDTH(8)
) u_intr_state_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_intr_state_d), .dat_i (s_intr_state_d),
rtl/ip/ribp/serial/i2s.sv
+9 -9
View File
@@ -47,8 +47,8 @@ module ribp_i2s (
logic s_i2s_mode; logic s_i2s_mode;
logic [1:0] s_i2s_format; logic [1:0] s_i2s_format;
logic s_i2s_recven; logic s_i2s_recven;
logic s_i2s_stream_tx_enable; logic s_i2s_stream_tx_en;
logic s_i2s_stream_rx_enable; logic s_i2s_stream_rx_en;
// tx fifo // tx fifo
logic s_tx_push_valid, s_tx_pio_push_valid, s_tx_full, s_tx_empty; logic s_tx_push_valid, s_tx_pio_push_valid, s_tx_full, s_tx_empty;
logic s_tx_pop_valid, s_tx_pop_ready; logic s_tx_pop_valid, s_tx_pop_ready;
@@ -68,8 +68,8 @@ module ribp_i2s (
.mode_o (s_i2s_mode), .mode_o (s_i2s_mode),
.format_o (s_i2s_format), .format_o (s_i2s_format),
.recven_o (s_i2s_recven), .recven_o (s_i2s_recven),
.stream_tx_enable_o(s_i2s_stream_tx_enable), .stream_tx_enable_o(s_i2s_stream_tx_en),
.stream_rx_enable_o(s_i2s_stream_rx_enable), .stream_rx_enable_o(s_i2s_stream_rx_en),
.tx_push_valid_o (s_tx_pio_push_valid), .tx_push_valid_o (s_tx_pio_push_valid),
.tx_push_data_o (s_tx_pio_push_data), .tx_push_data_o (s_tx_pio_push_data),
.tx_full_i (s_tx_full), .tx_full_i (s_tx_full),
@@ -82,10 +82,10 @@ module ribp_i2s (
.dma_rx_stall_o (dma_rx_stall_o) .dma_rx_stall_o (dma_rx_stall_o)
); );
assign tx_axis.tready = s_i2s_stream_tx_enable && !s_tx_full; assign tx_axis.tready = s_i2s_stream_tx_en && !s_tx_full;
assign s_tx_push_valid = s_i2s_stream_tx_enable ? assign s_tx_push_valid = s_i2s_stream_tx_en ?
(tx_axis.tvalid && tx_axis.tready) : s_tx_pio_push_valid; (tx_axis.tvalid && tx_axis.tready) : s_tx_pio_push_valid;
assign s_tx_push_data = s_i2s_stream_tx_enable ? tx_axis.tdata : s_tx_pio_push_data; assign s_tx_push_data = s_i2s_stream_tx_en ? tx_axis.tdata : s_tx_pio_push_data;
assign rx_axis.tdata = s_rx_pop_data; assign rx_axis.tdata = s_rx_pop_data;
assign rx_axis.tkeep = '1; assign rx_axis.tkeep = '1;
@@ -94,8 +94,8 @@ module ribp_i2s (
assign rx_axis.tid = '0; assign rx_axis.tid = '0;
assign rx_axis.tdest = '0; assign rx_axis.tdest = '0;
assign rx_axis.tuser = '0; assign rx_axis.tuser = '0;
assign rx_axis.tvalid = s_i2s_stream_rx_enable && !s_rx_empty; assign rx_axis.tvalid = s_i2s_stream_rx_en && !s_rx_empty;
assign s_rx_pop_valid = s_i2s_stream_rx_enable ? assign s_rx_pop_valid = s_i2s_stream_rx_en ?
(rx_axis.tvalid && rx_axis.tready) : s_rx_pio_pop_valid; (rx_axis.tvalid && rx_axis.tready) : s_rx_pio_pop_valid;
rtl/ip/ribp/serial/i2s_clkgen.sv
+30 -22
View File
@@ -60,17 +60,21 @@ module i2s_clkgen (
s_sclk_div_cnt_d = s_sclk_div_cnt_q + 3'd1; s_sclk_div_cnt_d = s_sclk_div_cnt_q + 3'd1;
end end
end end
dffr #(3) u_sclk_div_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_sclk_div_cnt_dffr (
s_sclk_div_cnt_d, .clk_i (clk_i),
s_sclk_div_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_sclk_div_cnt_d),
.dat_o (s_sclk_div_cnt_q)
); );
dffr #(1) u_sclk_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_sclk_dffr (
s_sclk_d, .clk_i (clk_i),
s_sclk_q .rst_n_i(rst_n_i),
.dat_i (s_sclk_d),
.dat_o (s_sclk_q)
); );
@@ -95,19 +99,23 @@ module i2s_clkgen (
s_lrck_div_cnt_d = s_lrck_div_cnt_q + 5'd1; s_lrck_div_cnt_d = s_lrck_div_cnt_q + 5'd1;
end end
end end
dffer #(5) u_lrck_div_cnt_dffer ( dffer #(
clk_i, .DATA_WIDTH(5)
rst_n_i, ) u_lrck_div_cnt_dffer (
s_sclk_fall, .clk_i (clk_i),
s_lrck_div_cnt_d, .rst_n_i(rst_n_i),
s_lrck_div_cnt_q .en_i (s_sclk_fall),
.dat_i (s_lrck_div_cnt_d),
.dat_o (s_lrck_div_cnt_q)
); );
dffer #(1) u_lrck_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_lrck_dffer (
s_sclk_fall, .clk_i (clk_i),
s_lrck_d, .rst_n_i(rst_n_i),
s_lrck_q .en_i (s_sclk_fall),
.dat_i (s_lrck_d),
.dat_o (s_lrck_q)
); );
rtl/ip/ribp/serial/i2s_core.sv
+36 -28
View File
@@ -50,17 +50,17 @@ module i2s_core (
edge_det_sync_re u_recv_done_edge_det_sync_re ( edge_det_sync_re u_recv_done_edge_det_sync_re (
clk_i, .clk_i (clk_i),
rst_n_i, .rst_n_i(rst_n_i),
s_recv_done, .dat_i (s_recv_done),
s_recv_done_re .re_o (s_recv_done_re)
); );
edge_det_sync_re u_send_done_edge_det_sync_re ( edge_det_sync_re u_send_done_edge_det_sync_re (
clk_i, .clk_i (clk_i),
rst_n_i, .rst_n_i(rst_n_i),
s_send_done, .dat_i (s_send_done),
s_send_done_re .re_o (s_send_done_re)
); );
always_comb begin always_comb begin
@@ -91,17 +91,21 @@ module i2s_core (
end end
end end
end end
dffr #(1) u_recv_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_recv_cnt_dffr (
s_recv_cnt_d, .clk_i (clk_i),
s_recv_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_recv_cnt_d),
.dat_o (s_recv_cnt_q)
); );
dffr #(24) u_recv_data_dffr ( dffr #(
clk_i, .DATA_WIDTH(24)
rst_n_i, ) u_recv_data_dffr (
s_recv_data_d, .clk_i (clk_i),
s_recv_data_q .rst_n_i(rst_n_i),
.dat_i (s_recv_data_d),
.dat_o (s_recv_data_q)
); );
@@ -135,17 +139,21 @@ module i2s_core (
end end
end end
end end
dffr #(1) u_send_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_send_cnt_dffr (
s_send_cnt_d, .clk_i (clk_i),
s_send_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_send_cnt_d),
.dat_o (s_send_cnt_q)
); );
dffr #(32) u_send_data_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_send_data_dffr (
s_send_data_d, .clk_i (clk_i),
s_send_data_q .rst_n_i(rst_n_i),
.dat_i (s_send_data_d),
.dat_o (s_send_data_q)
); );
rtl/ip/ribp/serial/i2s_recv.sv
+40 -30
View File
@@ -36,12 +36,14 @@ module i2s_recv (
assign s_lrck_dely_d = lrck_i; assign s_lrck_dely_d = lrck_i;
dffer #(1) u_lrck_dely_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_lrck_dely_dffer (
sclk_pos_i, .clk_i (clk_i),
s_lrck_dely_d, .rst_n_i(rst_n_i),
s_lrck_dely_q .en_i (sclk_pos_i),
.dat_i (s_lrck_dely_d),
.dat_o (s_lrck_dely_q)
); );
@@ -52,12 +54,14 @@ module i2s_recv (
s_bit_cnt_d = s_bit_cnt_q + 1'b1; s_bit_cnt_d = s_bit_cnt_q + 1'b1;
end end
end end
dffer #(5) u_bit_cnt_dffer ( dffer #(
clk_i, .DATA_WIDTH(5)
rst_n_i, ) u_bit_cnt_dffer (
sclk_pos_i, .clk_i (clk_i),
s_bit_cnt_d, .rst_n_i(rst_n_i),
s_bit_cnt_q .en_i (sclk_pos_i),
.dat_i (s_bit_cnt_d),
.dat_o (s_bit_cnt_q)
); );
@@ -74,12 +78,14 @@ module i2s_recv (
end end
end end
end end
dffer #(24) u_recv_data_dffer ( dffer #(
clk_i, .DATA_WIDTH(24)
rst_n_i, ) u_recv_data_dffer (
sclk_pos_i, .clk_i (clk_i),
s_recv_data_d, .rst_n_i(rst_n_i),
s_recv_data_q .en_i (sclk_pos_i),
.dat_i (s_recv_data_d),
.dat_o (s_recv_data_q)
); );
@@ -87,12 +93,14 @@ module i2s_recv (
s_first_bit_d = s_first_bit_q; s_first_bit_d = s_first_bit_q;
if (s_lrck_trg) s_first_bit_d = adcdat_i; if (s_lrck_trg) s_first_bit_d = adcdat_i;
end end
dffer #(1) u_first_bit_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_first_bit_dffer (
sclk_pos_i, .clk_i (clk_i),
s_first_bit_d, .rst_n_i(rst_n_i),
s_first_bit_q .en_i (sclk_pos_i),
.dat_i (s_first_bit_d),
.dat_o (s_first_bit_q)
); );
@@ -103,12 +111,14 @@ module i2s_recv (
else s_data_d = {8'd0, s_recv_data_d[14:0], s_first_bit_q}; else s_data_d = {8'd0, s_recv_data_d[14:0], s_first_bit_q};
end end
end end
dffer #(24) u_data_dffer ( dffer #(
clk_i, .DATA_WIDTH(24)
rst_n_i, ) u_data_dffer (
sclk_pos_i, .clk_i (clk_i),
s_data_d, .rst_n_i(rst_n_i),
s_data_q .en_i (sclk_pos_i),
.dat_i (s_data_d),
.dat_o (s_data_q)
); );
endmodule endmodule
rtl/ip/ribp/serial/i2s_reg.sv
+83 -61
View File
@@ -49,7 +49,7 @@ module i2s_reg (
logic [7:0] s_i2s_lowbound_d, s_i2s_lowbound_q; logic [7:0] s_i2s_lowbound_d, s_i2s_lowbound_q;
logic s_i2s_recven_en; logic s_i2s_recven_en;
logic s_i2s_recven_d, s_i2s_recven_q; logic s_i2s_recven_d, s_i2s_recven_q;
logic [1:0] s_i2s_status_d, s_i2s_status_q; logic [1:0] s_i2s_stat_d, s_i2s_stat_q;
logic s_i2s_stream_en; logic s_i2s_stream_en;
logic [1:0] s_i2s_stream_d, s_i2s_stream_q; logic [1:0] s_i2s_stream_d, s_i2s_stream_q;
// common // common
@@ -76,61 +76,73 @@ module i2s_reg (
assign s_i2s_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_MODE; assign s_i2s_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_MODE;
assign s_i2s_mode_d = ribp.wdata[0]; assign s_i2s_mode_d = ribp.wdata[0];
dffer #(1) u_i2s_mode_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_i2s_mode_dffer (
s_i2s_mode_en, .clk_i (clk_i),
s_i2s_mode_d, .rst_n_i(rst_n_i),
s_i2s_mode_q .en_i (s_i2s_mode_en),
.dat_i (s_i2s_mode_d),
.dat_o (s_i2s_mode_q)
); );
assign s_i2s_format_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_FORMAT; assign s_i2s_format_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_FORMAT;
assign s_i2s_format_d = ribp.wdata[1:0]; assign s_i2s_format_d = ribp.wdata[1:0];
dffer #(2) u_i2s_format_dffer ( dffer #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_i2s_format_dffer (
s_i2s_format_en, .clk_i (clk_i),
s_i2s_format_d, .rst_n_i(rst_n_i),
s_i2s_format_q .en_i (s_i2s_format_en),
.dat_i (s_i2s_format_d),
.dat_o (s_i2s_format_q)
); );
assign s_i2s_upbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_UPBOUND; assign s_i2s_upbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_UPBOUND;
assign s_i2s_upbound_d = ribp.wdata[7:0]; assign s_i2s_upbound_d = ribp.wdata[7:0];
dfferh #(8) u_i2s_upbound_dfferh ( dfferh #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_i2s_upbound_dfferh (
s_i2s_upbound_en, .clk_i (clk_i),
s_i2s_upbound_d, .rst_n_i(rst_n_i),
s_i2s_upbound_q .en_i (s_i2s_upbound_en),
.dat_i (s_i2s_upbound_d),
.dat_o (s_i2s_upbound_q)
); );
assign s_i2s_lowbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_LOWBOUND; assign s_i2s_lowbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_LOWBOUND;
assign s_i2s_lowbound_d = ribp.wdata[7:0]; assign s_i2s_lowbound_d = ribp.wdata[7:0];
dffer #(8) u_i2s_lowbound_dffer ( dffer #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_i2s_lowbound_dffer (
s_i2s_lowbound_en, .clk_i (clk_i),
s_i2s_lowbound_d, .rst_n_i(rst_n_i),
s_i2s_lowbound_q .en_i (s_i2s_lowbound_en),
.dat_i (s_i2s_lowbound_d),
.dat_o (s_i2s_lowbound_q)
); );
assign s_i2s_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_RECVEN; assign s_i2s_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_RECVEN;
assign s_i2s_recven_d = ribp.wdata[0]; assign s_i2s_recven_d = ribp.wdata[0];
dffer #(1) u_i2s_recven_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_i2s_recven_dffer (
s_i2s_recven_en, .clk_i (clk_i),
s_i2s_recven_d, .rst_n_i(rst_n_i),
s_i2s_recven_q .en_i (s_i2s_recven_en),
.dat_i (s_i2s_recven_d),
.dat_o (s_i2s_recven_q)
); );
assign s_i2s_stream_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_STREAM_CTRL; assign s_i2s_stream_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_STREAM_CTRL;
assign s_i2s_stream_d = ribp.wdata[1:0]; assign s_i2s_stream_d = ribp.wdata[1:0];
dffer #(2) u_i2s_stream_dffer ( dffer #(
.DATA_WIDTH(2)
) u_i2s_stream_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_i2s_stream_en), .en_i (s_i2s_stream_en),
@@ -147,11 +159,13 @@ module i2s_reg (
s_tx_fifo_stall_d = 1'b0; s_tx_fifo_stall_d = 1'b0;
end end
end end
dffr #(1) u_tx_fifo_stall_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_tx_fifo_stall_dffr (
s_tx_fifo_stall_d, .clk_i (clk_i),
s_tx_fifo_stall_q .rst_n_i(rst_n_i),
.dat_i (s_tx_fifo_stall_d),
.dat_o (s_tx_fifo_stall_q)
); );
@@ -163,11 +177,13 @@ module i2s_reg (
s_rx_fifo_stall_d = 1'b0; s_rx_fifo_stall_d = 1'b0;
end end
end end
dffr #(1) u_rx_fifo_stall_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_rx_fifo_stall_dffr (
s_rx_fifo_stall_d, .clk_i (clk_i),
s_rx_fifo_stall_q .rst_n_i(rst_n_i),
.dat_i (s_rx_fifo_stall_d),
.dat_o (s_rx_fifo_stall_q)
); );
@@ -186,22 +202,26 @@ module i2s_reg (
always_comb begin always_comb begin
s_i2s_status_d[0] = tx_full_i; s_i2s_stat_d[0] = tx_full_i;
s_i2s_status_d[1] = rx_empty_i; s_i2s_stat_d[1] = rx_empty_i;
end end
dffr #(2) u_i2s_status_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_i2s_status_dffr (
s_i2s_status_d, .clk_i (clk_i),
s_i2s_status_q .rst_n_i(rst_n_i),
.dat_i (s_i2s_stat_d),
.dat_o (s_i2s_stat_q)
); );
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
assign s_ribp_rdata_en = s_ribp_rd_hdshk; assign s_ribp_rdata_en = s_ribp_rd_hdshk;
@@ -218,17 +238,19 @@ module i2s_reg (
else s_ribp_rdata_d = '0; else s_ribp_rdata_d = '0;
end end
end end
`RIBP_I2S_STATUS: s_ribp_rdata_d = {30'd0, s_i2s_status_q}; `RIBP_I2S_STATUS: s_ribp_rdata_d = {30'd0, s_i2s_stat_q};
`RIBP_I2S_STREAM_CTRL: s_ribp_rdata_d = {30'd0, s_i2s_stream_q}; `RIBP_I2S_STREAM_CTRL: s_ribp_rdata_d = {30'd0, s_i2s_stream_q};
default: s_ribp_rdata_d = s_ribp_rdata_q; default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase endcase
end end
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
endmodule endmodule
rtl/ip/ribp/serial/i2s_send.sv
+32 -24
View File
@@ -35,12 +35,14 @@ module i2s_send (
assign s_lrck_dely_d = lrck_i; assign s_lrck_dely_d = lrck_i;
dffer #(1) u_lrck_dely_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_lrck_dely_dffer (
sclk_pos_i, .clk_i (clk_i),
s_lrck_dely_d, .rst_n_i(rst_n_i),
s_lrck_dely_q .en_i (sclk_pos_i),
.dat_i (s_lrck_dely_d),
.dat_o (s_lrck_dely_q)
); );
@@ -53,12 +55,14 @@ module i2s_send (
end end
end end
end end
dffer #(5) u_bit_cnt_dffer ( dffer #(
clk_i, .DATA_WIDTH(5)
rst_n_i, ) u_bit_cnt_dffer (
sclk_pos_i, .clk_i (clk_i),
s_bit_cnt_d, .rst_n_i(rst_n_i),
s_bit_cnt_q .en_i (sclk_pos_i),
.dat_i (s_bit_cnt_d),
.dat_o (s_bit_cnt_q)
); );
@@ -75,12 +79,14 @@ module i2s_send (
end end
end end
end end
dffer #(24) u_xfer_data_dffer ( dffer #(
clk_i, .DATA_WIDTH(24)
rst_n_i, ) u_xfer_data_dffer (
sclk_pos_i, .clk_i (clk_i),
s_xfer_data_d, .rst_n_i(rst_n_i),
s_xfer_data_q .en_i (sclk_pos_i),
.dat_i (s_xfer_data_d),
.dat_o (s_xfer_data_q)
); );
@@ -91,12 +97,14 @@ module i2s_send (
else s_dacdat_d = s_xfer_data_q[15]; else s_dacdat_d = s_xfer_data_q[15];
end end
end end
dffer #(1) u_dacdat_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_dacdat_dffer (
sclk_fall_i, .clk_i (clk_i),
s_dacdat_d, .rst_n_i(rst_n_i),
s_dacdat_q .en_i (sclk_fall_i),
.dat_i (s_dacdat_d),
.dat_o (s_dacdat_q)
); );
endmodule endmodule
rtl/ip/ribp/serial/ribp_i2c.sv
+12 -12
View File
@@ -15,7 +15,7 @@ module ribp_i2c #(
// verilog_format: on // verilog_format: on
); );
logic s_enable; logic s_en;
logic [15:0] s_scl_low_cycles; logic [15:0] s_scl_low_cycles;
logic [15:0] s_scl_high_cycles; logic [15:0] s_scl_high_cycles;
logic [15:0] s_start_hold_cycles; logic [15:0] s_start_hold_cycles;
@@ -28,7 +28,7 @@ module ribp_i2c #(
logic [ 3:0] s_sda_filter_cycles; logic [ 3:0] s_sda_filter_cycles;
logic [23:0] s_stretch_timeout; logic [23:0] s_stretch_timeout;
logic [23:0] s_bus_idle_timeout; logic [23:0] s_bus_idle_timeout;
logic [23:0] s_command_timeout; logic [23:0] s_cmd_timeout;
logic [ 9:0] s_target_addr; logic [ 9:0] s_target_addr;
logic s_ten_bit; logic s_ten_bit;
logic s_abort; logic s_abort;
@@ -51,8 +51,8 @@ module ribp_i2c #(
logic s_arb_lost_event; logic s_arb_lost_event;
logic s_stretch_timeout_event; logic s_stretch_timeout_event;
logic s_bus_timeout_event; logic s_bus_timeout_event;
logic s_command_timeout_event; logic s_cmd_timeout_event;
logic s_command_error_event; logic s_cmd_err_event;
logic s_rx_overflow_event; logic s_rx_overflow_event;
logic s_aborted_event; logic s_aborted_event;
logic s_recovery_done_event; logic s_recovery_done_event;
@@ -82,7 +82,7 @@ module ribp_i2c #(
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.ribp (ribp), .ribp (ribp),
.enable_o (s_enable), .enable_o (s_en),
.scl_low_cycles_o (s_scl_low_cycles), .scl_low_cycles_o (s_scl_low_cycles),
.scl_high_cycles_o (s_scl_high_cycles), .scl_high_cycles_o (s_scl_high_cycles),
.start_hold_cycles_o (s_start_hold_cycles), .start_hold_cycles_o (s_start_hold_cycles),
@@ -95,7 +95,7 @@ module ribp_i2c #(
.sda_filter_cycles_o (s_sda_filter_cycles), .sda_filter_cycles_o (s_sda_filter_cycles),
.stretch_timeout_o (s_stretch_timeout), .stretch_timeout_o (s_stretch_timeout),
.bus_idle_timeout_o (s_bus_idle_timeout), .bus_idle_timeout_o (s_bus_idle_timeout),
.command_timeout_o (s_command_timeout), .command_timeout_o (s_cmd_timeout),
.target_addr_o (s_target_addr), .target_addr_o (s_target_addr),
.ten_bit_o (s_ten_bit), .ten_bit_o (s_ten_bit),
.abort_o (s_abort), .abort_o (s_abort),
@@ -117,8 +117,8 @@ module ribp_i2c #(
.arb_lost_event_i (s_arb_lost_event), .arb_lost_event_i (s_arb_lost_event),
.stretch_timeout_event_i(s_stretch_timeout_event), .stretch_timeout_event_i(s_stretch_timeout_event),
.bus_timeout_event_i (s_bus_timeout_event), .bus_timeout_event_i (s_bus_timeout_event),
.command_timeout_event_i(s_command_timeout_event), .command_timeout_event_i(s_cmd_timeout_event),
.command_error_event_i (s_command_error_event), .command_error_event_i (s_cmd_err_event),
.rx_overflow_event_i (s_rx_overflow_event), .rx_overflow_event_i (s_rx_overflow_event),
.aborted_event_i (s_aborted_event), .aborted_event_i (s_aborted_event),
.recovery_done_event_i (s_recovery_done_event), .recovery_done_event_i (s_recovery_done_event),
@@ -131,7 +131,7 @@ module ribp_i2c #(
i2c_core u_i2c_core ( i2c_core u_i2c_core (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.enable_i (s_enable), .enable_i (s_en),
.scl_low_cycles_i (s_scl_low_cycles), .scl_low_cycles_i (s_scl_low_cycles),
.scl_high_cycles_i (s_scl_high_cycles), .scl_high_cycles_i (s_scl_high_cycles),
.start_hold_cycles_i (s_start_hold_cycles), .start_hold_cycles_i (s_start_hold_cycles),
@@ -142,7 +142,7 @@ module ribp_i2c #(
.bus_free_cycles_i (s_bus_free_cycles), .bus_free_cycles_i (s_bus_free_cycles),
.stretch_timeout_i (s_stretch_timeout), .stretch_timeout_i (s_stretch_timeout),
.bus_idle_timeout_i (s_bus_idle_timeout), .bus_idle_timeout_i (s_bus_idle_timeout),
.command_timeout_i (s_command_timeout), .command_timeout_i (s_cmd_timeout),
.target_addr_i (s_target_addr), .target_addr_i (s_target_addr),
.ten_bit_i (s_ten_bit), .ten_bit_i (s_ten_bit),
.abort_i (s_abort), .abort_i (s_abort),
@@ -166,8 +166,8 @@ module ribp_i2c #(
.arb_lost_event_o (s_arb_lost_event), .arb_lost_event_o (s_arb_lost_event),
.stretch_timeout_event_o(s_stretch_timeout_event), .stretch_timeout_event_o(s_stretch_timeout_event),
.bus_timeout_event_o (s_bus_timeout_event), .bus_timeout_event_o (s_bus_timeout_event),
.command_timeout_event_o(s_command_timeout_event), .command_timeout_event_o(s_cmd_timeout_event),
.command_error_event_o (s_command_error_event), .command_error_event_o (s_cmd_err_event),
.rx_overflow_event_o (s_rx_overflow_event), .rx_overflow_event_o (s_rx_overflow_event),
.aborted_event_o (s_aborted_event), .aborted_event_o (s_aborted_event),
.recovery_done_event_o (s_recovery_done_event), .recovery_done_event_o (s_recovery_done_event),
rtl/ip/ribp/serial/ribp_uart.sv
+14 -14
View File
@@ -20,12 +20,12 @@ module ribp_uart #(
logic [ 1:0] s_data_bits; logic [ 1:0] s_data_bits;
logic s_stop2; logic s_stop2;
logic [ 1:0] s_parity; logic [ 1:0] s_parity;
logic s_tx_enable; logic s_tx_en;
logic s_rx_enable; logic s_rx_en;
logic s_loopback; logic s_loopback;
logic s_break; logic s_break;
logic s_auto_cts_enable; logic s_auto_cts_en;
logic s_auto_rts_enable; logic s_auto_rts_en;
logic [ 6:0] s_rts_assert_level; logic [ 6:0] s_rts_assert_level;
logic [ 6:0] s_rts_deassert_level; logic [ 6:0] s_rts_deassert_level;
logic s_tx_data_valid; logic s_tx_data_valid;
@@ -61,12 +61,12 @@ module ribp_uart #(
.data_bits_o (s_data_bits), .data_bits_o (s_data_bits),
.stop2_o (s_stop2), .stop2_o (s_stop2),
.parity_o (s_parity), .parity_o (s_parity),
.tx_enable_o (s_tx_enable), .tx_enable_o (s_tx_en),
.rx_enable_o (s_rx_enable), .rx_enable_o (s_rx_en),
.loopback_o (s_loopback), .loopback_o (s_loopback),
.break_o (s_break), .break_o (s_break),
.auto_cts_enable_o (s_auto_cts_enable), .auto_cts_enable_o (s_auto_cts_en),
.auto_rts_enable_o (s_auto_rts_enable), .auto_rts_enable_o (s_auto_rts_en),
.rts_assert_level_o (s_rts_assert_level), .rts_assert_level_o (s_rts_assert_level),
.rts_deassert_level_o(s_rts_deassert_level), .rts_deassert_level_o(s_rts_deassert_level),
.tx_data_valid_o (s_tx_data_valid), .tx_data_valid_o (s_tx_data_valid),
@@ -96,8 +96,8 @@ module ribp_uart #(
.data_bits_i (s_data_bits), .data_bits_i (s_data_bits),
.stop2_i (s_stop2), .stop2_i (s_stop2),
.parity_i (s_parity), .parity_i (s_parity),
.tx_enable_i (s_tx_enable), .tx_enable_i (s_tx_en),
.rx_enable_i (s_rx_enable), .rx_enable_i (s_rx_en),
.loopback_i (s_loopback), .loopback_i (s_loopback),
.tx_start_allowed_i(s_tx_start_allowed), .tx_start_allowed_i(s_tx_start_allowed),
.break_i (s_break), .break_i (s_break),
@@ -118,10 +118,10 @@ module ribp_uart #(
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.cts_n_async_i (uart.cts_n_i), .cts_n_async_i (uart.cts_n_i),
.auto_cts_enable_i (s_auto_cts_enable), .auto_cts_enable_i (s_auto_cts_en),
.auto_rts_enable_i (s_auto_rts_enable), .auto_rts_enable_i (s_auto_rts_en),
.tx_enable_i (s_tx_enable), .tx_enable_i (s_tx_en),
.rx_enable_i (s_rx_enable), .rx_enable_i (s_rx_en),
.loopback_i (s_loopback), .loopback_i (s_loopback),
.tx_data_valid_i (s_tx_data_valid), .tx_data_valid_i (s_tx_data_valid),
.tx_busy_i (s_tx_busy), .tx_busy_i (s_tx_busy),
rtl/ip/ribp/serial/ribp_uart_rx.sv
+64 -42
View File
@@ -34,8 +34,8 @@ module ribp_uart_rx (
logic s_sample_or_d, s_sample_or_q; logic s_sample_or_d, s_sample_or_q;
logic s_sample_value_d, s_sample_value_q; logic s_sample_value_d, s_sample_value_q;
logic [7:0] s_data_d, s_data_q; logic [7:0] s_data_d, s_data_q;
logic s_parity_error_d, s_parity_error_q; logic s_parity_err_d, s_parity_err_q;
logic s_frame_error_d, s_frame_error_q; logic s_frame_err_d, s_frame_err_q;
logic s_noise_d, s_noise_q; logic s_noise_d, s_noise_q;
logic [2:0] s_last_bit; logic [2:0] s_last_bit;
logic [7:0] s_data_mask; logic [7:0] s_data_mask;
@@ -70,33 +70,29 @@ module ribp_uart_rx (
s_sample_or_d = s_sample_or_q; s_sample_or_d = s_sample_or_q;
s_sample_value_d = s_sample_value_q; s_sample_value_d = s_sample_value_q;
s_data_d = s_data_q; s_data_d = s_data_q;
s_parity_error_d = s_parity_error_q; s_parity_err_d = s_parity_err_q;
s_frame_error_d = s_frame_error_q; s_frame_err_d = s_frame_err_q;
s_noise_d = s_noise_q; s_noise_d = s_noise_q;
data_valid_o = 1'b0; data_valid_o = 1'b0;
data_o = { data_o = {
s_noise_q, s_noise_q, (s_frame_err_q && (s_data_q == 8'd0)), s_frame_err_q, s_parity_err_q, s_data_q
(s_frame_error_q && (s_data_q == 8'd0)),
s_frame_error_q,
s_parity_error_q,
s_data_q
}; };
if (!enable_i) begin if (!enable_i) begin
s_state_d = STATE_IDLE; s_state_d = STATE_IDLE;
s_sample_d = '0; s_sample_d = '0;
s_bit_d = '0; s_bit_d = '0;
s_parity_error_d = 1'b0; s_parity_err_d = 1'b0;
s_frame_error_d = 1'b0; s_frame_err_d = 1'b0;
s_noise_d = 1'b0; s_noise_d = 1'b0;
end else if ((s_state_q == STATE_IDLE) && !s_rx_sync_q) begin end else if ((s_state_q == STATE_IDLE) && !s_rx_sync_q) begin
s_state_d = STATE_START; s_state_d = STATE_START;
s_sample_d = '0; s_sample_d = '0;
s_bit_d = '0; s_bit_d = '0;
s_data_d = '0; s_data_d = '0;
s_parity_error_d = 1'b0; s_parity_err_d = 1'b0;
s_frame_error_d = 1'b0; s_frame_err_d = 1'b0;
s_noise_d = 1'b0; s_noise_d = 1'b0;
end else if ((s_state_q != STATE_IDLE) && sample_tick_i) begin end else if ((s_state_q != STATE_IDLE) && sample_tick_i) begin
if (s_sample_q == 4'd7) begin if (s_sample_q == 4'd7) begin
s_sample_sum_d = {1'b0, s_rx_sync_q}; s_sample_sum_d = {1'b0, s_rx_sync_q};
@@ -111,9 +107,9 @@ module ribp_uart_rx (
s_noise_d = s_noise_q | s_samples_mixed; s_noise_d = s_noise_q | s_samples_mixed;
unique case (s_state_q) unique case (s_state_q)
STATE_DATA: s_data_d[s_bit_q] = s_majority; STATE_DATA: s_data_d[s_bit_q] = s_majority;
STATE_PARITY: s_parity_error_d = s_majority != s_expected_parity; STATE_PARITY: s_parity_err_d = s_majority != s_expected_parity;
STATE_STOP1: s_frame_error_d = !s_majority; STATE_STOP1: s_frame_err_d = !s_majority;
STATE_STOP2: s_frame_error_d = s_frame_error_q | !s_majority; STATE_STOP2: s_frame_err_d = s_frame_err_q | !s_majority;
default: begin default: begin
end end
endcase endcase
@@ -157,79 +153,105 @@ module ribp_uart_rx (
end end
end end
dffr #(1) u_rx_meta_dffr ( dffr #(
.DATA_WIDTH(1)
) u_rx_meta_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rx_meta_d), .dat_i (s_rx_meta_d),
.dat_o (s_rx_meta_q) .dat_o (s_rx_meta_q)
); );
dffr #(1) u_rx_sync_dffr ( dffr #(
.DATA_WIDTH(1)
) u_rx_sync_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rx_sync_d), .dat_i (s_rx_sync_d),
.dat_o (s_rx_sync_q) .dat_o (s_rx_sync_q)
); );
dffr #(3) u_state_dffr ( dffr #(
.DATA_WIDTH(3)
) u_state_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_state_d), .dat_i (s_state_d),
.dat_o (s_state_q) .dat_o (s_state_q)
); );
dffr #(4) u_sample_dffr ( dffr #(
.DATA_WIDTH(4)
) u_sample_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_d), .dat_i (s_sample_d),
.dat_o (s_sample_q) .dat_o (s_sample_q)
); );
dffr #(3) u_bit_dffr ( dffr #(
.DATA_WIDTH(3)
) u_bit_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bit_d), .dat_i (s_bit_d),
.dat_o (s_bit_q) .dat_o (s_bit_q)
); );
dffr #(2) u_sample_sum_dffr ( dffr #(
.DATA_WIDTH(2)
) u_sample_sum_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_sum_d), .dat_i (s_sample_sum_d),
.dat_o (s_sample_sum_q) .dat_o (s_sample_sum_q)
); );
dffr #(1) u_sample_and_dffr ( dffr #(
.DATA_WIDTH(1)
) u_sample_and_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_and_d), .dat_i (s_sample_and_d),
.dat_o (s_sample_and_q) .dat_o (s_sample_and_q)
); );
dffr #(1) u_sample_or_dffr ( dffr #(
.DATA_WIDTH(1)
) u_sample_or_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_or_d), .dat_i (s_sample_or_d),
.dat_o (s_sample_or_q) .dat_o (s_sample_or_q)
); );
dffr #(1) u_sample_value_dffr ( dffr #(
.DATA_WIDTH(1)
) u_sample_value_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_value_d), .dat_i (s_sample_value_d),
.dat_o (s_sample_value_q) .dat_o (s_sample_value_q)
); );
dffr #(8) u_data_dffr ( dffr #(
.DATA_WIDTH(8)
) u_data_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_data_d), .dat_i (s_data_d),
.dat_o (s_data_q) .dat_o (s_data_q)
); );
dffr #(1) u_parity_error_dffr ( dffr #(
.DATA_WIDTH(1)
) u_parity_error_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_parity_error_d), .dat_i (s_parity_err_d),
.dat_o (s_parity_error_q) .dat_o (s_parity_err_q)
); );
dffr #(1) u_frame_error_dffr ( dffr #(
.DATA_WIDTH(1)
) u_frame_error_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_frame_error_d), .dat_i (s_frame_err_d),
.dat_o (s_frame_error_q) .dat_o (s_frame_err_q)
); );
dffr #(1) u_noise_dffr ( dffr #(
.DATA_WIDTH(1)
) u_noise_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_noise_d), .dat_i (s_noise_d),
rtl/ip/ribp/serial/ribp_uart_tx.sv
+15 -5
View File
@@ -111,31 +111,41 @@ module ribp_uart_tx (
end end
end end
dffr #(3) u_state_dffr ( dffr #(
.DATA_WIDTH(3)
) u_state_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_state_d), .dat_i (s_state_d),
.dat_o (s_state_q) .dat_o (s_state_q)
); );
dffr #(4) u_sample_dffr ( dffr #(
.DATA_WIDTH(4)
) u_sample_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_d), .dat_i (s_sample_d),
.dat_o (s_sample_q) .dat_o (s_sample_q)
); );
dffr #(3) u_bit_dffr ( dffr #(
.DATA_WIDTH(3)
) u_bit_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bit_d), .dat_i (s_bit_d),
.dat_o (s_bit_q) .dat_o (s_bit_q)
); );
dffr #(8) u_shift_dffr ( dffr #(
.DATA_WIDTH(8)
) u_shift_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_shift_d), .dat_i (s_shift_d),
.dat_o (s_shift_q) .dat_o (s_shift_q)
); );
dffr #(1) u_parity_dffr ( dffr #(
.DATA_WIDTH(1)
) u_parity_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_parity_d), .dat_i (s_parity_d),
rtl/ip/ribp/serial/uart_baudgen.sv
+6 -2
View File
@@ -39,14 +39,18 @@ module uart_baudgen (
end end
end end
dffr #(32) u_phase_dffr ( dffr #(
.DATA_WIDTH(32)
) u_phase_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_phase_d), .dat_i (s_phase_d),
.dat_o (s_phase_q) .dat_o (s_phase_q)
); );
dffr #(4) u_sample_count_dffr ( dffr #(
.DATA_WIDTH(4)
) u_sample_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_sample_count_d), .dat_i (s_sample_count_d),
rtl/ip/ribp/serial/uart_flow_ctrl.sv
+3 -1
View File
@@ -53,7 +53,9 @@ module uart_flow_ctrl (
end end
end end
dffr #(1) u_rts_asserted_dffr ( dffr #(
.DATA_WIDTH(1)
) u_rts_asserted_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rts_asserted_d), .dat_i (s_rts_asserted_d),
rtl/ip/ribp/serial/uart_reg.sv
+130 -108
View File
@@ -58,7 +58,7 @@ module uart_reg #(
logic s_req; logic s_req;
logic s_write; logic s_write;
logic s_req_accept; logic s_req_accept;
logic s_access_error; logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q; logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q; logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q; logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
@@ -77,8 +77,8 @@ module uart_reg #(
logic [6:0] s_rx_watermark_d, s_rx_watermark_q; logic [6:0] s_rx_watermark_d, s_rx_watermark_q;
logic s_rx_timeout_en; logic s_rx_timeout_en;
logic [15:0] s_rx_timeout_d, s_rx_timeout_q; logic [15:0] s_rx_timeout_d, s_rx_timeout_q;
logic s_intr_enable_en; logic s_intr_en_en;
logic [6:0] s_intr_enable_d, s_intr_enable_q; logic [6:0] s_intr_en_d, s_intr_en_q;
logic s_dma_ctrl_en; logic s_dma_ctrl_en;
logic [1:0] s_dma_ctrl_d, s_dma_ctrl_q; logic [1:0] s_dma_ctrl_d, s_dma_ctrl_q;
logic s_flow_ctrl_en; logic s_flow_ctrl_en;
@@ -101,19 +101,19 @@ module uart_reg #(
logic [ 11:0] s_rx_pop_data; logic [ 11:0] s_rx_pop_data;
logic [RX_FIFO_LOG_DEPTH:0] s_rx_count; logic [RX_FIFO_LOG_DEPTH:0] s_rx_count;
logic [6:0] s_error_status_d, s_error_status_q; logic [6:0] s_err_stat_d, s_err_stat_q;
logic [6:0] s_intr_state_d, s_intr_state_q; logic [6:0] s_intr_state_d, s_intr_state_q;
logic [6:0] s_error_clear; logic [6:0] s_err_clear;
logic [6:0] s_intr_clear; logic [6:0] s_intr_clear;
logic [6:0] s_intr_test; logic [6:0] s_intr_test;
logic s_config_error_event; logic s_config_err_event;
logic s_command_error_event; logic s_cmd_err_event;
logic s_overrun_event; logic s_overrun_event;
logic s_rx_error_event; logic s_rx_err_event;
logic s_rx_timeout_event; logic s_rx_timeout_event;
logic [15:0] s_rx_timeout_count_d, s_rx_timeout_count_q; logic [15:0] s_rx_timeout_count_d, s_rx_timeout_count_q;
logic [31:0] s_status; logic [31:0] s_stat;
logic [31:0] s_fifo_level; logic [31:0] s_fifo_level;
logic [31:0] s_merge_value; logic [31:0] s_merge_value;
logic s_config_valid; logic s_config_valid;
@@ -174,33 +174,33 @@ module uart_reg #(
assign dma_rx_stall_o = !s_rx_dma_req; assign dma_rx_stall_o = !s_rx_dma_req;
assign s_tx_watermark_active = tx_enable_o && (s_tx_count <= s_tx_watermark_q); assign s_tx_watermark_active = tx_enable_o && (s_tx_count <= s_tx_watermark_q);
assign s_rx_watermark_active = rx_enable_o && (s_rx_count >= s_rx_watermark_q); assign s_rx_watermark_active = rx_enable_o && (s_rx_count >= s_rx_watermark_q);
assign irq_o = |(s_intr_state_q & s_intr_enable_q); assign irq_o = |(s_intr_state_q & s_intr_en_q);
always_comb begin always_comb begin
s_status = '0; s_stat = '0;
s_status[`UART_STATUS_TX_ENABLED] = tx_enable_o; s_stat[`UART_STATUS_TX_ENABLED] = tx_enable_o;
s_status[`UART_STATUS_RX_ENABLED] = rx_enable_o; s_stat[`UART_STATUS_RX_ENABLED] = rx_enable_o;
s_status[`UART_STATUS_TX_BUSY] = tx_busy_i; s_stat[`UART_STATUS_TX_BUSY] = tx_busy_i;
s_status[`UART_STATUS_RX_ACTIVE] = rx_active_i; s_stat[`UART_STATUS_RX_ACTIVE] = rx_active_i;
s_status[`UART_STATUS_TX_EMPTY] = s_tx_empty; s_stat[`UART_STATUS_TX_EMPTY] = s_tx_empty;
s_status[`UART_STATUS_TX_FULL] = s_tx_full; s_stat[`UART_STATUS_TX_FULL] = s_tx_full;
s_status[`UART_STATUS_RX_EMPTY] = s_rx_empty; s_stat[`UART_STATUS_RX_EMPTY] = s_rx_empty;
s_status[`UART_STATUS_RX_FULL] = s_rx_full; s_stat[`UART_STATUS_RX_FULL] = s_rx_full;
s_status[`UART_STATUS_CONFIG_VALID] = s_config_valid; s_stat[`UART_STATUS_CONFIG_VALID] = s_config_valid;
s_status[`UART_STATUS_BREAK_ACTIVE] = break_o; s_stat[`UART_STATUS_BREAK_ACTIVE] = break_o;
s_status[`UART_STATUS_TX_DMA_REQ] = s_tx_dma_req; s_stat[`UART_STATUS_TX_DMA_REQ] = s_tx_dma_req;
s_status[`UART_STATUS_RX_DMA_REQ] = s_rx_dma_req; s_stat[`UART_STATUS_RX_DMA_REQ] = s_rx_dma_req;
s_status[`UART_STATUS_CTS_ASSERTED] = cts_asserted_i; s_stat[`UART_STATUS_CTS_ASSERTED] = cts_asserted_i;
s_status[`UART_STATUS_RTS_ASSERTED] = rts_asserted_i; s_stat[`UART_STATUS_RTS_ASSERTED] = rts_asserted_i;
s_status[`UART_STATUS_TX_FLOW_BLOCKED] = tx_flow_blocked_i; s_stat[`UART_STATUS_TX_FLOW_BLOCKED] = tx_flow_blocked_i;
s_fifo_level = '0; s_fifo_level = '0;
s_fifo_level[6:0] = 7'(s_tx_count); s_fifo_level[6:0] = 7'(s_tx_count);
s_fifo_level[22:16] = 7'(s_rx_count); s_fifo_level[22:16] = 7'(s_rx_count);
end end
always_comb begin always_comb begin
s_req_accept = s_req; s_req_accept = s_req;
s_access_error = 1'b0; s_access_err = 1'b0;
s_baud_int_en = 1'b0; s_baud_int_en = 1'b0;
s_baud_frac_en = 1'b0; s_baud_frac_en = 1'b0;
s_line_ctrl_en = 1'b0; s_line_ctrl_en = 1'b0;
@@ -208,7 +208,7 @@ module uart_reg #(
s_tx_watermark_en = 1'b0; s_tx_watermark_en = 1'b0;
s_rx_watermark_en = 1'b0; s_rx_watermark_en = 1'b0;
s_rx_timeout_en = 1'b0; s_rx_timeout_en = 1'b0;
s_intr_enable_en = 1'b0; s_intr_en_en = 1'b0;
s_dma_ctrl_en = 1'b0; s_dma_ctrl_en = 1'b0;
s_flow_ctrl_en = 1'b0; s_flow_ctrl_en = 1'b0;
s_rts_watermark_en = 1'b0; s_rts_watermark_en = 1'b0;
@@ -219,7 +219,7 @@ module uart_reg #(
s_tx_watermark_d = s_tx_watermark_q; s_tx_watermark_d = s_tx_watermark_q;
s_rx_watermark_d = s_rx_watermark_q; s_rx_watermark_d = s_rx_watermark_q;
s_rx_timeout_d = s_rx_timeout_q; s_rx_timeout_d = s_rx_timeout_q;
s_intr_enable_d = s_intr_enable_q; s_intr_en_d = s_intr_en_q;
s_dma_ctrl_d = s_dma_ctrl_q; s_dma_ctrl_d = s_dma_ctrl_q;
s_flow_ctrl_d = s_flow_ctrl_q; s_flow_ctrl_d = s_flow_ctrl_q;
s_rts_assert_level_d = s_rts_assert_level_q; s_rts_assert_level_d = s_rts_assert_level_q;
@@ -228,25 +228,25 @@ module uart_reg #(
s_rx_flush = 1'b0; s_rx_flush = 1'b0;
s_tx_push = 1'b0; s_tx_push = 1'b0;
s_rx_pop = 1'b0; s_rx_pop = 1'b0;
s_error_clear = '0; s_err_clear = '0;
s_intr_clear = '0; s_intr_clear = '0;
s_intr_test = '0; s_intr_test = '0;
s_config_error_event = 1'b0; s_config_err_event = 1'b0;
s_command_error_event = 1'b0; s_cmd_err_event = 1'b0;
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
s_merge_value = '0; s_merge_value = '0;
if (s_req) begin if (s_req) begin
if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else if (s_write) begin end else if (s_write) begin
unique case (ribp.addr[7:0]) unique case (ribp.addr[7:0])
`RIBP_UART_BAUD_INT: begin `RIBP_UART_BAUD_INT: begin
s_merge_value = merge_wstrb({8'd0, s_baud_int_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({8'd0, s_baud_int_q}, ribp.wdata, ribp.wstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i || if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:24] != 8'd0) || (s_merge_value[23:0] < 24'd16)) begin (s_merge_value[31:24] != 8'd0) || (s_merge_value[23:0] < 24'd16)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_baud_int_en = 1'b1; s_baud_int_en = 1'b1;
s_baud_int_d = s_merge_value[23:0]; s_baud_int_d = s_merge_value[23:0];
@@ -256,8 +256,8 @@ module uart_reg #(
s_merge_value = merge_wstrb({24'd0, s_baud_frac_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({24'd0, s_baud_frac_q}, ribp.wdata, ribp.wstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i || if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:8] != 24'd0)) begin (s_merge_value[31:8] != 24'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_baud_frac_en = 1'b1; s_baud_frac_en = 1'b1;
s_baud_frac_d = s_merge_value[7:0]; s_baud_frac_d = s_merge_value[7:0];
@@ -267,8 +267,8 @@ module uart_reg #(
s_merge_value = merge_wstrb({27'd0, s_line_ctrl_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({27'd0, s_line_ctrl_q}, ribp.wdata, ribp.wstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i || if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:5] != 27'd0) || (s_merge_value[4:3] == 2'd3)) begin (s_merge_value[31:5] != 27'd0) || (s_merge_value[4:3] == 2'd3)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_line_ctrl_en = 1'b1; s_line_ctrl_en = 1'b1;
s_line_ctrl_d = s_merge_value[4:0]; s_line_ctrl_d = s_merge_value[4:0];
@@ -281,8 +281,8 @@ module uart_reg #(
(s_merge_value[`UART_CTRL_TX_BREAK] && tx_busy_i) || (s_merge_value[`UART_CTRL_TX_BREAK] && tx_busy_i) ||
((s_merge_value[`UART_CTRL_LOOPBACK] != loopback_o) && ((s_merge_value[`UART_CTRL_LOOPBACK] != loopback_o) &&
(tx_busy_i || rx_active_i))) begin (tx_busy_i || rx_active_i))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_ctrl_en = 1'b1; s_ctrl_en = 1'b1;
s_ctrl_d = s_merge_value[3:0]; s_ctrl_d = s_merge_value[3:0];
@@ -292,13 +292,13 @@ module uart_reg #(
if (!ribp.wstrb[0] || if (!ribp.wstrb[0] ||
(|(ribp.wdata[31:8] & {{8{ribp.wstrb[3]}}, {8{ribp.wstrb[2]}}, (|(ribp.wdata[31:8] & {{8{ribp.wstrb[3]}}, {8{ribp.wstrb[2]}},
{8{ribp.wstrb[1]}}}))) begin {8{ribp.wstrb[1]}}}))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else if (s_tx_full && tx_enable_o && s_config_valid) begin end else if (s_tx_full && tx_enable_o && s_config_valid) begin
s_req_accept = 1'b0; s_req_accept = 1'b0;
end else if (s_tx_full) begin end else if (s_tx_full) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_tx_push = 1'b1; s_tx_push = 1'b1;
end end
@@ -308,8 +308,8 @@ module uart_reg #(
(ribp.wdata[1:0] == 2'd0) || (ribp.wdata[1:0] == 2'd0) ||
(ribp.wdata[`UART_FIFO_CTRL_TX_FLUSH] && (tx_enable_o || tx_busy_i)) || (ribp.wdata[`UART_FIFO_CTRL_TX_FLUSH] && (tx_enable_o || tx_busy_i)) ||
(ribp.wdata[`UART_FIFO_CTRL_RX_FLUSH] && (rx_enable_o || rx_active_i))) begin (ribp.wdata[`UART_FIFO_CTRL_RX_FLUSH] && (rx_enable_o || rx_active_i))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_tx_flush = ribp.wdata[`UART_FIFO_CTRL_TX_FLUSH]; s_tx_flush = ribp.wdata[`UART_FIFO_CTRL_TX_FLUSH];
s_rx_flush = ribp.wdata[`UART_FIFO_CTRL_RX_FLUSH]; s_rx_flush = ribp.wdata[`UART_FIFO_CTRL_RX_FLUSH];
@@ -318,8 +318,8 @@ module uart_reg #(
`RIBP_UART_TX_WATERMARK: begin `RIBP_UART_TX_WATERMARK: begin
s_merge_value = merge_wstrb({25'd0, s_tx_watermark_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({25'd0, s_tx_watermark_q}, ribp.wdata, ribp.wstrb);
if ((s_merge_value[31:7] != 25'd0) || (s_merge_value[6:0] >= 7'(TX_FIFO_DEPTH))) begin if ((s_merge_value[31:7] != 25'd0) || (s_merge_value[6:0] >= 7'(TX_FIFO_DEPTH))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_tx_watermark_en = 1'b1; s_tx_watermark_en = 1'b1;
s_tx_watermark_d = s_merge_value[6:0]; s_tx_watermark_d = s_merge_value[6:0];
@@ -329,8 +329,8 @@ module uart_reg #(
s_merge_value = merge_wstrb({25'd0, s_rx_watermark_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({25'd0, s_rx_watermark_q}, ribp.wdata, ribp.wstrb);
if ((s_merge_value[31:7] != 25'd0) || (s_merge_value[6:0] == 7'd0) || if ((s_merge_value[31:7] != 25'd0) || (s_merge_value[6:0] == 7'd0) ||
(s_merge_value[6:0] > 7'(RX_FIFO_DEPTH))) begin (s_merge_value[6:0] > 7'(RX_FIFO_DEPTH))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_rx_watermark_en = 1'b1; s_rx_watermark_en = 1'b1;
s_rx_watermark_d = s_merge_value[6:0]; s_rx_watermark_d = s_merge_value[6:0];
@@ -339,8 +339,8 @@ module uart_reg #(
`RIBP_UART_RX_TIMEOUT_BITS: begin `RIBP_UART_RX_TIMEOUT_BITS: begin
s_merge_value = merge_wstrb({16'd0, s_rx_timeout_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({16'd0, s_rx_timeout_q}, ribp.wdata, ribp.wstrb);
if (s_merge_value[31:16] != 16'd0) begin if (s_merge_value[31:16] != 16'd0) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_rx_timeout_en = 1'b1; s_rx_timeout_en = 1'b1;
s_rx_timeout_d = s_merge_value[15:0]; s_rx_timeout_d = s_merge_value[15:0];
@@ -348,30 +348,30 @@ module uart_reg #(
end end
`RIBP_UART_ERROR_STATUS: begin `RIBP_UART_ERROR_STATUS: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_error_clear = ribp.wdata[6:0]; s_err_clear = ribp.wdata[6:0];
end end
end end
`RIBP_UART_INTR_STATE: begin `RIBP_UART_INTR_STATE: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_clear = ribp.wdata[6:0]; s_intr_clear = ribp.wdata[6:0];
end end
end end
`RIBP_UART_INTR_ENABLE: begin `RIBP_UART_INTR_ENABLE: begin
s_merge_value = merge_wstrb({25'd0, s_intr_enable_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({25'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb);
if (s_merge_value[31:7] != 25'd0) begin if (s_merge_value[31:7] != 25'd0) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = s_merge_value[6:0]; s_intr_en_d = s_merge_value[6:0];
end end
end end
`RIBP_UART_INTR_TEST: begin `RIBP_UART_INTR_TEST: begin
if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin if (!ribp.wstrb[0] || (ribp.wdata[31:7] != 25'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_test = ribp.wdata[6:0]; s_intr_test = ribp.wdata[6:0];
end end
@@ -379,8 +379,8 @@ module uart_reg #(
`RIBP_UART_DMA_CTRL: begin `RIBP_UART_DMA_CTRL: begin
s_merge_value = merge_wstrb({30'd0, s_dma_ctrl_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({30'd0, s_dma_ctrl_q}, ribp.wdata, ribp.wstrb);
if (s_merge_value[31:2] != 30'd0) begin if (s_merge_value[31:2] != 30'd0) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_dma_ctrl_en = 1'b1; s_dma_ctrl_en = 1'b1;
s_dma_ctrl_d = s_merge_value[1:0]; s_dma_ctrl_d = s_merge_value[1:0];
@@ -390,8 +390,8 @@ module uart_reg #(
s_merge_value = merge_wstrb({30'd0, s_flow_ctrl_q}, ribp.wdata, ribp.wstrb); s_merge_value = merge_wstrb({30'd0, s_flow_ctrl_q}, ribp.wdata, ribp.wstrb);
if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i || if (tx_enable_o || rx_enable_o || tx_busy_i || rx_active_i ||
(s_merge_value[31:2] != 30'd0)) begin (s_merge_value[31:2] != 30'd0)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_flow_ctrl_en = 1'b1; s_flow_ctrl_en = 1'b1;
s_flow_ctrl_d = s_merge_value[1:0]; s_flow_ctrl_d = s_merge_value[1:0];
@@ -404,15 +404,15 @@ module uart_reg #(
(s_merge_value[31:23] != 9'd0) || (s_merge_value[15:7] != 9'd0) || (s_merge_value[31:23] != 9'd0) || (s_merge_value[15:7] != 9'd0) ||
(s_merge_value[22:16] > 7'(RX_FIFO_DEPTH)) || (s_merge_value[22:16] > 7'(RX_FIFO_DEPTH)) ||
(s_merge_value[6:0] >= s_merge_value[22:16])) begin (s_merge_value[6:0] >= s_merge_value[22:16])) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
s_rts_watermark_en = 1'b1; s_rts_watermark_en = 1'b1;
s_rts_assert_level_d = s_merge_value[6:0]; s_rts_assert_level_d = s_merge_value[6:0];
s_rts_deassert_level_d = s_merge_value[22:16]; s_rts_deassert_level_d = s_merge_value[22:16];
end end
end end
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end else begin end else begin
unique case (ribp.addr[7:0]) unique case (ribp.addr[7:0])
@@ -422,22 +422,22 @@ module uart_reg #(
`RIBP_UART_CTRL: s_ribp_rdata_d = {28'd0, s_ctrl_q}; `RIBP_UART_CTRL: s_ribp_rdata_d = {28'd0, s_ctrl_q};
`RIBP_UART_RXDATA: begin `RIBP_UART_RXDATA: begin
if (s_rx_empty) begin if (s_rx_empty) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_ribp_rdata_d = {20'd0, s_rx_pop_data}; s_ribp_rdata_d = {20'd0, s_rx_pop_data};
s_rx_pop = 1'b1; s_rx_pop = 1'b1;
end end
end end
`RIBP_UART_STATUS: s_ribp_rdata_d = s_status; `RIBP_UART_STATUS: s_ribp_rdata_d = s_stat;
`RIBP_UART_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level; `RIBP_UART_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level;
`RIBP_UART_TX_WATERMARK: s_ribp_rdata_d = {25'd0, s_tx_watermark_q}; `RIBP_UART_TX_WATERMARK: s_ribp_rdata_d = {25'd0, s_tx_watermark_q};
`RIBP_UART_RX_WATERMARK: s_ribp_rdata_d = {25'd0, s_rx_watermark_q}; `RIBP_UART_RX_WATERMARK: s_ribp_rdata_d = {25'd0, s_rx_watermark_q};
`RIBP_UART_RX_TIMEOUT_BITS: s_ribp_rdata_d = {16'd0, s_rx_timeout_q}; `RIBP_UART_RX_TIMEOUT_BITS: s_ribp_rdata_d = {16'd0, s_rx_timeout_q};
`RIBP_UART_ERROR_STATUS: s_ribp_rdata_d = {25'd0, s_error_status_q}; `RIBP_UART_ERROR_STATUS: s_ribp_rdata_d = {25'd0, s_err_stat_q};
`RIBP_UART_INTR_STATE: s_ribp_rdata_d = {25'd0, s_intr_state_q}; `RIBP_UART_INTR_STATE: s_ribp_rdata_d = {25'd0, s_intr_state_q};
`RIBP_UART_INTR_ENABLE: s_ribp_rdata_d = {25'd0, s_intr_enable_q}; `RIBP_UART_INTR_ENABLE: s_ribp_rdata_d = {25'd0, s_intr_en_q};
`RIBP_UART_INTR_STATUS: s_ribp_rdata_d = {25'd0, (s_intr_state_q & s_intr_enable_q)}; `RIBP_UART_INTR_STATUS: s_ribp_rdata_d = {25'd0, (s_intr_state_q & s_intr_en_q)};
`RIBP_UART_DMA_CTRL: s_ribp_rdata_d = {30'd0, s_dma_ctrl_q}; `RIBP_UART_DMA_CTRL: s_ribp_rdata_d = {30'd0, s_dma_ctrl_q};
`RIBP_UART_FLOW_CTRL: s_ribp_rdata_d = {30'd0, s_flow_ctrl_q}; `RIBP_UART_FLOW_CTRL: s_ribp_rdata_d = {30'd0, s_flow_ctrl_q};
`RIBP_UART_RTS_WATERMARK: `RIBP_UART_RTS_WATERMARK:
@@ -445,7 +445,7 @@ module uart_reg #(
`RIBP_UART_IP_VERSION: s_ribp_rdata_d = IP_VERSION; `RIBP_UART_IP_VERSION: s_ribp_rdata_d = IP_VERSION;
`RIBP_UART_CAPABILITY: s_ribp_rdata_d = CAPABILITY; `RIBP_UART_CAPABILITY: s_ribp_rdata_d = CAPABILITY;
default: begin default: begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
end end
endcase endcase
@@ -454,25 +454,31 @@ module uart_reg #(
end end
assign s_ribp_ready_d = s_req_accept; assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_error; assign s_ribp_resp_err_d = s_access_err;
assign s_rx_push = rx_data_valid_i && !s_rx_full; assign s_rx_push = rx_data_valid_i && !s_rx_full;
assign s_overrun_event = rx_data_valid_i && s_rx_full; assign s_overrun_event = rx_data_valid_i && s_rx_full;
assign s_rx_error_event = s_rx_push && (|rx_data_i[11:8]); assign s_rx_err_event = s_rx_push && (|rx_data_i[11:8]);
dffr #(1) u_ribp_ready_dffr ( dffr #(
.DATA_WIDTH(1)
) u_ribp_ready_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d), .dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q) .dat_o (s_ribp_ready_q)
); );
dffer #(1) u_ribp_resp_err_dffer ( dffer #(
.DATA_WIDTH(1)
) u_ribp_resp_err_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d), .dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q) .dat_o (s_ribp_resp_err_q)
); );
dffer #(32) u_ribp_rdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_ribp_rdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_req_accept), .en_i (s_req_accept),
@@ -480,14 +486,18 @@ module uart_reg #(
.dat_o (s_ribp_rdata_q) .dat_o (s_ribp_rdata_q)
); );
dffer #(24) u_baud_int_dffer ( dffer #(
.DATA_WIDTH(24)
) u_baud_int_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_baud_int_en), .en_i (s_baud_int_en),
.dat_i (s_baud_int_d), .dat_i (s_baud_int_d),
.dat_o (s_baud_int_q) .dat_o (s_baud_int_q)
); );
dffer #(8) u_baud_frac_dffer ( dffer #(
.DATA_WIDTH(8)
) u_baud_frac_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_baud_frac_en), .en_i (s_baud_frac_en),
@@ -504,7 +514,9 @@ module uart_reg #(
.dat_i (s_line_ctrl_d), .dat_i (s_line_ctrl_d),
.dat_o (s_line_ctrl_q) .dat_o (s_line_ctrl_q)
); );
dffer #(4) u_ctrl_dffer ( dffer #(
.DATA_WIDTH(4)
) u_ctrl_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_ctrl_en), .en_i (s_ctrl_en),
@@ -541,21 +553,27 @@ module uart_reg #(
.dat_i (s_rx_timeout_d), .dat_i (s_rx_timeout_d),
.dat_o (s_rx_timeout_q) .dat_o (s_rx_timeout_q)
); );
dffer #(7) u_intr_enable_dffer ( dffer #(
.DATA_WIDTH(7)
) u_intr_enable_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_intr_enable_en), .en_i (s_intr_en_en),
.dat_i (s_intr_enable_d), .dat_i (s_intr_en_d),
.dat_o (s_intr_enable_q) .dat_o (s_intr_en_q)
); );
dffer #(2) u_dma_ctrl_dffer ( dffer #(
.DATA_WIDTH(2)
) u_dma_ctrl_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_dma_ctrl_en), .en_i (s_dma_ctrl_en),
.dat_i (s_dma_ctrl_d), .dat_i (s_dma_ctrl_d),
.dat_o (s_dma_ctrl_q) .dat_o (s_dma_ctrl_q)
); );
dffer #(2) u_flow_ctrl_dffer ( dffer #(
.DATA_WIDTH(2)
) u_flow_ctrl_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_flow_ctrl_en), .en_i (s_flow_ctrl_en),
@@ -631,7 +649,9 @@ module uart_reg #(
end end
end end
end end
dffr #(16) u_rx_timeout_count_dffr ( dffr #(
.DATA_WIDTH(16)
) u_rx_timeout_count_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rx_timeout_count_d), .dat_i (s_rx_timeout_count_d),
@@ -639,22 +659,22 @@ module uart_reg #(
); );
always_comb begin always_comb begin
s_error_status_d = s_error_status_q & ~s_error_clear; s_err_stat_d = s_err_stat_q & ~s_err_clear;
if (s_overrun_event) s_error_status_d[`UART_ERROR_OVERRUN] = 1'b1; if (s_overrun_event) s_err_stat_d[`UART_ERROR_OVERRUN] = 1'b1;
if (s_rx_push && rx_data_i[`UART_RXDATA_PARITY_ERROR]) if (s_rx_push && rx_data_i[`UART_RXDATA_PARITY_ERROR]) s_err_stat_d[`UART_ERROR_PARITY] = 1'b1;
s_error_status_d[`UART_ERROR_PARITY] = 1'b1; if (s_rx_push && rx_data_i[`UART_RXDATA_FRAME_ERROR]) s_err_stat_d[`UART_ERROR_FRAME] = 1'b1;
if (s_rx_push && rx_data_i[`UART_RXDATA_FRAME_ERROR]) if (s_rx_push && rx_data_i[`UART_RXDATA_BREAK]) s_err_stat_d[`UART_ERROR_BREAK] = 1'b1;
s_error_status_d[`UART_ERROR_FRAME] = 1'b1; if (s_rx_push && rx_data_i[`UART_RXDATA_NOISE]) s_err_stat_d[`UART_ERROR_NOISE] = 1'b1;
if (s_rx_push && rx_data_i[`UART_RXDATA_BREAK]) s_error_status_d[`UART_ERROR_BREAK] = 1'b1; if (s_config_err_event) s_err_stat_d[`UART_ERROR_CONFIG] = 1'b1;
if (s_rx_push && rx_data_i[`UART_RXDATA_NOISE]) s_error_status_d[`UART_ERROR_NOISE] = 1'b1; if (s_cmd_err_event) s_err_stat_d[`UART_ERROR_COMMAND] = 1'b1;
if (s_config_error_event) s_error_status_d[`UART_ERROR_CONFIG] = 1'b1;
if (s_command_error_event) s_error_status_d[`UART_ERROR_COMMAND] = 1'b1;
end end
dffr #(7) u_error_status_dffr ( dffr #(
.DATA_WIDTH(7)
) u_error_status_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_error_status_d), .dat_i (s_err_stat_d),
.dat_o (s_error_status_q) .dat_o (s_err_stat_q)
); );
always_comb begin always_comb begin
@@ -663,11 +683,13 @@ module uart_reg #(
if (s_rx_timeout_event) s_intr_state_d[`UART_INTR_RX_TIMEOUT] = 1'b1; if (s_rx_timeout_event) s_intr_state_d[`UART_INTR_RX_TIMEOUT] = 1'b1;
if (s_tx_watermark_active) s_intr_state_d[`UART_INTR_TX_WATERMARK] = 1'b1; if (s_tx_watermark_active) s_intr_state_d[`UART_INTR_TX_WATERMARK] = 1'b1;
if (tx_done_i && s_tx_empty) s_intr_state_d[`UART_INTR_TX_DONE] = 1'b1; if (tx_done_i && s_tx_empty) s_intr_state_d[`UART_INTR_TX_DONE] = 1'b1;
if (s_rx_error_event || s_overrun_event) s_intr_state_d[`UART_INTR_RX_ERROR] = 1'b1; if (s_rx_err_event || s_overrun_event) s_intr_state_d[`UART_INTR_RX_ERROR] = 1'b1;
if (s_rx_push && rx_data_i[`UART_RXDATA_BREAK]) s_intr_state_d[`UART_INTR_BREAK] = 1'b1; if (s_rx_push && rx_data_i[`UART_RXDATA_BREAK]) s_intr_state_d[`UART_INTR_BREAK] = 1'b1;
if (cts_change_i) s_intr_state_d[`UART_INTR_CTS_CHANGE] = 1'b1; if (cts_change_i) s_intr_state_d[`UART_INTR_CTS_CHANGE] = 1'b1;
end end
dffr #(7) u_intr_state_dffr ( dffr #(
.DATA_WIDTH(7)
) u_intr_state_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_intr_state_d), .dat_i (s_intr_state_d),
rtl/ip/ribp/serial/ws2812_core.sv
+98 -70
View File
@@ -191,89 +191,117 @@ module ws2812_core (
.dat_o (s_state_q) .dat_o (s_state_q)
); );
dffr #(16) u_bit_cycles_dffr ( dffr #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_bit_cycles_dffr (
s_bit_cycles_d, .clk_i (clk_i),
s_bit_cycles_q .rst_n_i(rst_n_i),
.dat_i (s_bit_cycles_d),
.dat_o (s_bit_cycles_q)
); );
dffr #(16) u_t0h_cycles_dffr ( dffr #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_t0h_cycles_dffr (
s_t0h_cycles_d, .clk_i (clk_i),
s_t0h_cycles_q .rst_n_i(rst_n_i),
.dat_i (s_t0h_cycles_d),
.dat_o (s_t0h_cycles_q)
); );
dffr #(16) u_t1h_cycles_dffr ( dffr #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_t1h_cycles_dffr (
s_t1h_cycles_d, .clk_i (clk_i),
s_t1h_cycles_q .rst_n_i(rst_n_i),
.dat_i (s_t1h_cycles_d),
.dat_o (s_t1h_cycles_q)
); );
dffr #(32) u_reset_cycles_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_reset_cycles_dffr (
s_reset_cycles_d, .clk_i (clk_i),
s_reset_cycles_q .rst_n_i(rst_n_i),
.dat_i (s_reset_cycles_d),
.dat_o (s_reset_cycles_q)
); );
dffr #(16) u_bit_cycle_dffr ( dffr #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_bit_cycle_dffr (
s_bit_cycle_d, .clk_i (clk_i),
s_bit_cycle_q .rst_n_i(rst_n_i),
.dat_i (s_bit_cycle_d),
.dat_o (s_bit_cycle_q)
); );
dffr #(5) u_bit_index_dffr ( dffr #(
clk_i, .DATA_WIDTH(5)
rst_n_i, ) u_bit_index_dffr (
s_bit_index_d, .clk_i (clk_i),
s_bit_index_q .rst_n_i(rst_n_i),
.dat_i (s_bit_index_d),
.dat_o (s_bit_index_q)
); );
dffr #(32) u_reset_cycle_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_reset_cycle_dffr (
s_reset_cycle_d, .clk_i (clk_i),
s_reset_cycle_q .rst_n_i(rst_n_i),
.dat_i (s_reset_cycle_d),
.dat_o (s_reset_cycle_q)
); );
dffr #(32) u_remaining_words_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_remaining_words_dffr (
s_remaining_words_d, .clk_i (clk_i),
s_remaining_words_q .rst_n_i(rst_n_i),
.dat_i (s_remaining_words_d),
.dat_o (s_remaining_words_q)
); );
dffr #(24) u_xfer_data_dffr ( dffr #(
clk_i, .DATA_WIDTH(24)
rst_n_i, ) u_xfer_data_dffr (
s_xfer_data_d, .clk_i (clk_i),
s_xfer_data_q .rst_n_i(rst_n_i),
.dat_i (s_xfer_data_d),
.dat_o (s_xfer_data_q)
); );
dffr #(1) u_success_pending_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_success_pending_dffr (
s_success_pending_d, .clk_i (clk_i),
s_success_pending_q .rst_n_i(rst_n_i),
.dat_i (s_success_pending_d),
.dat_o (s_success_pending_q)
); );
dffr #(1) u_abort_pending_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_abort_pending_dffr (
s_abort_pending_d, .clk_i (clk_i),
s_abort_pending_q .rst_n_i(rst_n_i),
.dat_i (s_abort_pending_d),
.dat_o (s_abort_pending_q)
); );
dffr #(1) u_done_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_done_dffr (
s_done_d, .clk_i (clk_i),
s_done_q .rst_n_i(rst_n_i),
.dat_i (s_done_d),
.dat_o (s_done_q)
); );
dffr #(1) u_underflow_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_underflow_dffr (
s_underflow_d, .clk_i (clk_i),
s_underflow_q .rst_n_i(rst_n_i),
.dat_i (s_underflow_d),
.dat_o (s_underflow_q)
); );
dffr #(1) u_aborted_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_aborted_dffr (
s_aborted_d, .clk_i (clk_i),
s_aborted_q .rst_n_i(rst_n_i),
.dat_i (s_aborted_d),
.dat_o (s_aborted_q)
); );
endmodule endmodule
rtl/ip/ribp/serial/ws2812_reg.sv
+172 -148
View File
@@ -46,7 +46,7 @@ module ws2812_reg #(
logic s_req; logic s_req;
logic s_write; logic s_write;
logic s_req_accept; logic s_req_accept;
logic s_access_error; logic s_access_err;
logic s_ribp_ready_d, s_ribp_ready_q; logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_resp_err_d, s_ribp_resp_err_q; logic s_ribp_resp_err_d, s_ribp_resp_err_q;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q; logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
@@ -63,8 +63,8 @@ module ws2812_reg #(
logic [31:0] s_frame_words_d, s_frame_words_q; logic [31:0] s_frame_words_d, s_frame_words_q;
logic s_fifo_watermark_en; logic s_fifo_watermark_en;
logic [31:0] s_fifo_watermark_d, s_fifo_watermark_q; logic [31:0] s_fifo_watermark_d, s_fifo_watermark_q;
logic s_intr_enable_en; logic s_intr_en_en;
logic [3:0] s_intr_enable_d, s_intr_enable_q; logic [3:0] s_intr_en_d, s_intr_en_q;
logic s_fifo_flush_cmd; logic s_fifo_flush_cmd;
logic s_tx_push; logic s_tx_push;
@@ -74,16 +74,16 @@ module ws2812_reg #(
logic [TX_FIFO_LOG_DEPTH:0] s_tx_count; logic [TX_FIFO_LOG_DEPTH:0] s_tx_count;
logic [31:0] s_load_remaining_d, s_load_remaining_q; logic [31:0] s_load_remaining_d, s_load_remaining_q;
logic [2:0] s_error_status_d, s_error_status_q; logic [2:0] s_err_stat_d, s_err_stat_q;
logic [3:0] s_intr_state_d, s_intr_state_q; logic [3:0] s_intr_state_d, s_intr_state_q;
logic [ 2:0] s_error_clear; logic [ 2:0] s_err_clear;
logic [ 3:0] s_intr_clear; logic [ 3:0] s_intr_clear;
logic [ 3:0] s_intr_test; logic [ 3:0] s_intr_test;
logic s_config_error_event; logic s_config_err_event;
logic s_command_error_event; logic s_cmd_err_event;
logic s_fifo_low; logic s_fifo_low;
logic s_config_valid; logic s_config_valid;
logic [31:0] s_status; logic [31:0] s_stat;
logic [31:0] s_fifo_level; logic [31:0] s_fifo_level;
logic [31:0] s_watermark_write_value; logic [31:0] s_watermark_write_value;
@@ -114,7 +114,7 @@ module ws2812_reg #(
assign frame_words_o = s_frame_words_q; assign frame_words_o = s_frame_words_q;
assign data_valid_o = !s_tx_empty; assign data_valid_o = !s_tx_empty;
assign data_o = s_tx_pop_data; assign data_o = s_tx_pop_data;
assign irq_o = |(s_intr_state_q & s_intr_enable_q); assign irq_o = |(s_intr_state_q & s_intr_en_q);
assign s_fifo_level = {{(31 - TX_FIFO_LOG_DEPTH) {1'b0}}, s_tx_count}; assign s_fifo_level = {{(31 - TX_FIFO_LOG_DEPTH) {1'b0}}, s_tx_count};
assign s_watermark_write_value = merge_wstrb(s_fifo_watermark_q, ribp.wdata, ribp.wstrb); assign s_watermark_write_value = merge_wstrb(s_fifo_watermark_q, ribp.wdata, ribp.wstrb);
assign s_config_valid = (s_bit_cycles_q != 16'd0) && assign s_config_valid = (s_bit_cycles_q != 16'd0) &&
@@ -127,46 +127,46 @@ module ws2812_reg #(
(s_fifo_level <= s_fifo_watermark_q); (s_fifo_level <= s_fifo_watermark_q);
always_comb begin always_comb begin
s_status = '0; s_stat = '0;
s_status[`WS2812_STATUS_BUSY] = core_busy_i; s_stat[`WS2812_STATUS_BUSY] = core_busy_i;
s_status[`WS2812_STATUS_FIFO_EMPTY] = s_tx_empty; s_stat[`WS2812_STATUS_FIFO_EMPTY] = s_tx_empty;
s_status[`WS2812_STATUS_FIFO_FULL] = s_tx_full; s_stat[`WS2812_STATUS_FIFO_FULL] = s_tx_full;
s_status[`WS2812_STATUS_CONFIG_VALID] = s_config_valid; s_stat[`WS2812_STATUS_CONFIG_VALID] = s_config_valid;
s_status[`WS2812_STATUS_RESET_ACTIVE] = core_reset_active_i; s_stat[`WS2812_STATUS_RESET_ACTIVE] = core_reset_active_i;
end end
always_comb begin always_comb begin
s_req_accept = s_req; s_req_accept = s_req;
s_access_error = 1'b0; s_access_err = 1'b0;
s_bit_cycles_en = 1'b0; s_bit_cycles_en = 1'b0;
s_t0h_cycles_en = 1'b0; s_t0h_cycles_en = 1'b0;
s_t1h_cycles_en = 1'b0; s_t1h_cycles_en = 1'b0;
s_reset_cycles_en = 1'b0; s_reset_cycles_en = 1'b0;
s_frame_words_en = 1'b0; s_frame_words_en = 1'b0;
s_fifo_watermark_en = 1'b0; s_fifo_watermark_en = 1'b0;
s_intr_enable_en = 1'b0; s_intr_en_en = 1'b0;
s_bit_cycles_d = s_bit_cycles_q; s_bit_cycles_d = s_bit_cycles_q;
s_t0h_cycles_d = s_t0h_cycles_q; s_t0h_cycles_d = s_t0h_cycles_q;
s_t1h_cycles_d = s_t1h_cycles_q; s_t1h_cycles_d = s_t1h_cycles_q;
s_reset_cycles_d = s_reset_cycles_q; s_reset_cycles_d = s_reset_cycles_q;
s_frame_words_d = s_frame_words_q; s_frame_words_d = s_frame_words_q;
s_fifo_watermark_d = s_fifo_watermark_q; s_fifo_watermark_d = s_fifo_watermark_q;
s_intr_enable_d = s_intr_enable_q; s_intr_en_d = s_intr_en_q;
s_fifo_flush_cmd = 1'b0; s_fifo_flush_cmd = 1'b0;
s_tx_push = 1'b0; s_tx_push = 1'b0;
s_tx_push_data = ribp.wdata[23:0]; s_tx_push_data = ribp.wdata[23:0];
start_o = 1'b0; start_o = 1'b0;
abort_o = 1'b0; abort_o = 1'b0;
s_error_clear = '0; s_err_clear = '0;
s_intr_clear = '0; s_intr_clear = '0;
s_intr_test = '0; s_intr_test = '0;
s_config_error_event = 1'b0; s_config_err_event = 1'b0;
s_command_error_event = 1'b0; s_cmd_err_event = 1'b0;
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
if (s_req) begin if (s_req) begin
if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin if ((ribp.addr[11:8] != 4'd0) || (ribp.addr[1:0] != 2'b00)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else if (s_write) begin end else if (s_write) begin
unique case (ribp.addr[7:0]) unique case (ribp.addr[7:0])
`RIBP_WS2812_BIT_CYCLES: begin `RIBP_WS2812_BIT_CYCLES: begin
@@ -187,54 +187,54 @@ module ws2812_reg #(
end end
`RIBP_WS2812_TXDATA: begin `RIBP_WS2812_TXDATA: begin
if (ribp.wstrb != 4'hF || (core_busy_i && (s_load_remaining_q == 32'd0))) begin if (ribp.wstrb != 4'hF || (core_busy_i && (s_load_remaining_q == 32'd0))) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else if (s_tx_full && core_busy_i) begin end else if (s_tx_full && core_busy_i) begin
s_req_accept = 1'b0; s_req_accept = 1'b0;
end else if (s_tx_full && !core_busy_i) begin end else if (s_tx_full && !core_busy_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_tx_push = 1'b1; s_tx_push = 1'b1;
end end
end end
`RIBP_WS2812_CTRL: begin `RIBP_WS2812_CTRL: begin
if (!ribp.wstrb[0]) begin if (!ribp.wstrb[0]) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
unique case (ribp.wdata[2:0]) unique case (ribp.wdata[2:0])
3'b001: begin 3'b001: begin
if (core_busy_i || (s_frame_words_q == 32'd0) || s_tx_empty || if (core_busy_i || (s_frame_words_q == 32'd0) || s_tx_empty ||
(s_fifo_level > s_frame_words_q)) begin (s_fifo_level > s_frame_words_q)) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else if (!s_config_valid) begin end else if (!s_config_valid) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_config_error_event = 1'b1; s_config_err_event = 1'b1;
end else begin end else begin
start_o = 1'b1; start_o = 1'b1;
end end
end end
3'b010: begin 3'b010: begin
if (!core_busy_i) begin if (!core_busy_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
abort_o = 1'b1; abort_o = 1'b1;
end end
end end
3'b100: begin 3'b100: begin
if (core_busy_i) begin if (core_busy_i) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_fifo_flush_cmd = 1'b1; s_fifo_flush_cmd = 1'b1;
end end
end end
default: begin default: begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end end
endcase endcase
end end
@@ -245,8 +245,8 @@ module ws2812_reg #(
end end
`RIBP_WS2812_FIFO_WATERMARK: begin `RIBP_WS2812_FIFO_WATERMARK: begin
if (s_watermark_write_value >= TX_FIFO_DEPTH) begin if (s_watermark_write_value >= TX_FIFO_DEPTH) begin
s_access_error = 1'b1; s_access_err = 1'b1;
s_command_error_event = 1'b1; s_cmd_err_event = 1'b1;
end else begin end else begin
s_fifo_watermark_en = 1'b1; s_fifo_watermark_en = 1'b1;
s_fifo_watermark_d = s_watermark_write_value; s_fifo_watermark_d = s_watermark_write_value;
@@ -254,30 +254,30 @@ module ws2812_reg #(
end end
`RIBP_WS2812_ERROR_STATUS: begin `RIBP_WS2812_ERROR_STATUS: begin
if (!ribp.wstrb[0]) begin if (!ribp.wstrb[0]) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_error_clear = ribp.wdata[2:0]; s_err_clear = ribp.wdata[2:0];
end end
end end
`RIBP_WS2812_INTR_STATE: begin `RIBP_WS2812_INTR_STATE: begin
if (!ribp.wstrb[0]) begin if (!ribp.wstrb[0]) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_clear = ribp.wdata[3:0]; s_intr_clear = ribp.wdata[3:0];
end end
end end
`RIBP_WS2812_INTR_ENABLE: begin `RIBP_WS2812_INTR_ENABLE: begin
s_intr_enable_en = 1'b1; s_intr_en_en = 1'b1;
s_intr_enable_d = 4'(merge_wstrb({28'd0, s_intr_enable_q}, ribp.wdata, ribp.wstrb)); s_intr_en_d = 4'(merge_wstrb({28'd0, s_intr_en_q}, ribp.wdata, ribp.wstrb));
end end
`RIBP_WS2812_INTR_TEST: begin `RIBP_WS2812_INTR_TEST: begin
if (!ribp.wstrb[0]) begin if (!ribp.wstrb[0]) begin
s_access_error = 1'b1; s_access_err = 1'b1;
end else begin end else begin
s_intr_test = ribp.wdata[3:0]; s_intr_test = ribp.wdata[3:0];
end end
end end
default: s_access_error = 1'b1; default: s_access_err = 1'b1;
endcase endcase
end else begin end else begin
unique case (ribp.addr[7:0]) unique case (ribp.addr[7:0])
@@ -285,18 +285,18 @@ module ws2812_reg #(
`RIBP_WS2812_T0H_CYCLES: s_ribp_rdata_d = {16'd0, s_t0h_cycles_q}; `RIBP_WS2812_T0H_CYCLES: s_ribp_rdata_d = {16'd0, s_t0h_cycles_q};
`RIBP_WS2812_T1H_CYCLES: s_ribp_rdata_d = {16'd0, s_t1h_cycles_q}; `RIBP_WS2812_T1H_CYCLES: s_ribp_rdata_d = {16'd0, s_t1h_cycles_q};
`RIBP_WS2812_RESET_CYCLES: s_ribp_rdata_d = s_reset_cycles_q; `RIBP_WS2812_RESET_CYCLES: s_ribp_rdata_d = s_reset_cycles_q;
`RIBP_WS2812_STATUS: s_ribp_rdata_d = s_status; `RIBP_WS2812_STATUS: s_ribp_rdata_d = s_stat;
`RIBP_WS2812_FRAME_WORDS: s_ribp_rdata_d = s_frame_words_q; `RIBP_WS2812_FRAME_WORDS: s_ribp_rdata_d = s_frame_words_q;
`RIBP_WS2812_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level; `RIBP_WS2812_FIFO_LEVEL: s_ribp_rdata_d = s_fifo_level;
`RIBP_WS2812_FIFO_WATERMARK: s_ribp_rdata_d = s_fifo_watermark_q; `RIBP_WS2812_FIFO_WATERMARK: s_ribp_rdata_d = s_fifo_watermark_q;
`RIBP_WS2812_REMAINING_WORDS: s_ribp_rdata_d = core_remaining_words_i; `RIBP_WS2812_REMAINING_WORDS: s_ribp_rdata_d = core_remaining_words_i;
`RIBP_WS2812_ERROR_STATUS: s_ribp_rdata_d = {29'd0, s_error_status_q}; `RIBP_WS2812_ERROR_STATUS: s_ribp_rdata_d = {29'd0, s_err_stat_q};
`RIBP_WS2812_INTR_STATE: s_ribp_rdata_d = {28'd0, s_intr_state_q}; `RIBP_WS2812_INTR_STATE: s_ribp_rdata_d = {28'd0, s_intr_state_q};
`RIBP_WS2812_INTR_ENABLE: s_ribp_rdata_d = {28'd0, s_intr_enable_q}; `RIBP_WS2812_INTR_ENABLE: s_ribp_rdata_d = {28'd0, s_intr_en_q};
`RIBP_WS2812_IP_INFO: s_ribp_rdata_d = IP_INFO; `RIBP_WS2812_IP_INFO: s_ribp_rdata_d = IP_INFO;
default: begin default: begin
s_ribp_rdata_d = '0; s_ribp_rdata_d = '0;
s_access_error = 1'b1; s_access_err = 1'b1;
end end
endcase endcase
end end
@@ -304,63 +304,79 @@ module ws2812_reg #(
end end
assign s_ribp_ready_d = s_req_accept; assign s_ribp_ready_d = s_req_accept;
assign s_ribp_resp_err_d = s_access_error; assign s_ribp_resp_err_d = s_access_err;
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
dffer #(1) u_ribp_resp_err_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_resp_err_dffer (
s_req_accept, .clk_i (clk_i),
s_ribp_resp_err_d, .rst_n_i(rst_n_i),
s_ribp_resp_err_q .en_i (s_req_accept),
.dat_i (s_ribp_resp_err_d),
.dat_o (s_ribp_resp_err_q)
); );
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_req_accept, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_req_accept),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
dffer #(16) u_bit_cycles_dffer ( dffer #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_bit_cycles_dffer (
s_bit_cycles_en, .clk_i (clk_i),
s_bit_cycles_d, .rst_n_i(rst_n_i),
s_bit_cycles_q .en_i (s_bit_cycles_en),
.dat_i (s_bit_cycles_d),
.dat_o (s_bit_cycles_q)
); );
dffer #(16) u_t0h_cycles_dffer ( dffer #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_t0h_cycles_dffer (
s_t0h_cycles_en, .clk_i (clk_i),
s_t0h_cycles_d, .rst_n_i(rst_n_i),
s_t0h_cycles_q .en_i (s_t0h_cycles_en),
.dat_i (s_t0h_cycles_d),
.dat_o (s_t0h_cycles_q)
); );
dffer #(16) u_t1h_cycles_dffer ( dffer #(
clk_i, .DATA_WIDTH(16)
rst_n_i, ) u_t1h_cycles_dffer (
s_t1h_cycles_en, .clk_i (clk_i),
s_t1h_cycles_d, .rst_n_i(rst_n_i),
s_t1h_cycles_q .en_i (s_t1h_cycles_en),
.dat_i (s_t1h_cycles_d),
.dat_o (s_t1h_cycles_q)
); );
dffer #(32) u_reset_cycles_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_reset_cycles_dffer (
s_reset_cycles_en, .clk_i (clk_i),
s_reset_cycles_d, .rst_n_i(rst_n_i),
s_reset_cycles_q .en_i (s_reset_cycles_en),
.dat_i (s_reset_cycles_d),
.dat_o (s_reset_cycles_q)
); );
dffer #(32) u_frame_words_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_frame_words_dffer (
s_frame_words_en, .clk_i (clk_i),
s_frame_words_d, .rst_n_i(rst_n_i),
s_frame_words_q .en_i (s_frame_words_en),
.dat_i (s_frame_words_d),
.dat_o (s_frame_words_q)
); );
dfferc #( dfferc #(
.DATA_WIDTH(32), .DATA_WIDTH(32),
@@ -372,12 +388,14 @@ module ws2812_reg #(
.dat_i (s_fifo_watermark_d), .dat_i (s_fifo_watermark_d),
.dat_o (s_fifo_watermark_q) .dat_o (s_fifo_watermark_q)
); );
dffer #(4) u_intr_enable_dffer ( dffer #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_intr_enable_dffer (
s_intr_enable_en, .clk_i (clk_i),
s_intr_enable_d, .rst_n_i(rst_n_i),
s_intr_enable_q .en_i (s_intr_en_en),
.dat_i (s_intr_en_d),
.dat_o (s_intr_en_q)
); );
fifo #( fifo #(
@@ -407,30 +425,34 @@ module ws2812_reg #(
s_load_remaining_d = s_load_remaining_q - 1'b1; s_load_remaining_d = s_load_remaining_q - 1'b1;
end end
end end
dffr #(32) u_load_remaining_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_load_remaining_dffr (
s_load_remaining_d, .clk_i (clk_i),
s_load_remaining_q .rst_n_i(rst_n_i),
.dat_i (s_load_remaining_d),
.dat_o (s_load_remaining_q)
); );
always_comb begin always_comb begin
s_error_status_d = s_error_status_q & ~s_error_clear; s_err_stat_d = s_err_stat_q & ~s_err_clear;
if (s_config_error_event) begin if (s_config_err_event) begin
s_error_status_d[`WS2812_ERROR_CONFIG] = 1'b1; s_err_stat_d[`WS2812_ERROR_CONFIG] = 1'b1;
end end
if (core_underflow_i) begin if (core_underflow_i) begin
s_error_status_d[`WS2812_ERROR_UNDERFLOW] = 1'b1; s_err_stat_d[`WS2812_ERROR_UNDERFLOW] = 1'b1;
end end
if (s_command_error_event) begin if (s_cmd_err_event) begin
s_error_status_d[`WS2812_ERROR_COMMAND] = 1'b1; s_err_stat_d[`WS2812_ERROR_COMMAND] = 1'b1;
end end
end end
dffr #(3) u_error_status_dffr ( dffr #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_error_status_dffr (
s_error_status_d, .clk_i (clk_i),
s_error_status_q .rst_n_i(rst_n_i),
.dat_i (s_err_stat_d),
.dat_o (s_err_stat_q)
); );
always_comb begin always_comb begin
@@ -441,18 +463,20 @@ module ws2812_reg #(
if (s_fifo_low) begin if (s_fifo_low) begin
s_intr_state_d[`WS2812_INTR_FIFO_LOW] = 1'b1; s_intr_state_d[`WS2812_INTR_FIFO_LOW] = 1'b1;
end end
if (s_config_error_event || s_command_error_event || core_underflow_i) begin if (s_config_err_event || s_cmd_err_event || core_underflow_i) begin
s_intr_state_d[`WS2812_INTR_ERROR] = 1'b1; s_intr_state_d[`WS2812_INTR_ERROR] = 1'b1;
end end
if (core_aborted_i) begin if (core_aborted_i) begin
s_intr_state_d[`WS2812_INTR_ABORTED] = 1'b1; s_intr_state_d[`WS2812_INTR_ABORTED] = 1'b1;
end end
end end
dffr #(4) u_intr_state_dffr ( dffr #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_intr_state_dffr (
s_intr_state_d, .clk_i (clk_i),
s_intr_state_q .rst_n_i(rst_n_i),
.dat_i (s_intr_state_d),
.dat_o (s_intr_state_q)
); );
endmodule endmodule
rtl/ip/ribp/storage/sdio.sv
+5 -2
View File
@@ -40,8 +40,11 @@ module ribp_sdio (
// verilog_format: on // verilog_format: on
); );
wire dummy0 = clk_i; logic dummy0;
wire dummy1 = rst_n_i; logic dummy1;
assign dummy0 = clk_i;
assign dummy1 = rst_n_i;
// ribp // ribp
assign ribp.rdata = '0; assign ribp.rdata = '0;
assign ribp.ready = '0; assign ribp.ready = '0;
rtl/ip/ribp/storage/spisd_cache.sv
+63 -45
View File
@@ -173,60 +173,76 @@ module spisd_cache (
endcase endcase
end end
dffr #(2) u_cache_fsm_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_cache_fsm_dffr (
s_cache_fsm_d, .clk_i (clk_i),
s_cache_fsm_q .rst_n_i(rst_n_i),
.dat_i (s_cache_fsm_d),
.dat_o (s_cache_fsm_q)
); );
dffr #(1) u_cache_valid_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_cache_valid_dffr (
s_cache_valid_d, .clk_i (clk_i),
s_cache_valid_q .rst_n_i(rst_n_i),
.dat_i (s_cache_valid_d),
.dat_o (s_cache_valid_q)
); );
dffr #(1) u_cache_dirty_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_cache_dirty_dffr (
s_cache_dirty_d, .clk_i (clk_i),
s_cache_dirty_q .rst_n_i(rst_n_i),
.dat_i (s_cache_dirty_d),
.dat_o (s_cache_dirty_q)
); );
dffr #(32) u_cache_tag_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_cache_tag_dffr (
s_cache_tag_d, .clk_i (clk_i),
s_cache_tag_q .rst_n_i(rst_n_i),
.dat_i (s_cache_tag_d),
.dat_o (s_cache_tag_q)
); );
dffr #(7) u_line_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(7)
rst_n_i, ) u_line_cnt_dffr (
s_line_cnt_d, .clk_i (clk_i),
s_line_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_line_cnt_d),
.dat_o (s_line_cnt_q)
); );
dffr #(2) u_word_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_word_cnt_dffr (
s_word_cnt_d, .clk_i (clk_i),
s_word_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_word_cnt_d),
.dat_o (s_word_cnt_q)
); );
dffr #(8) u_s_sd_wr_data_dffr ( dffr #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_s_sd_wr_data_dffr (
s_sd_wr_data_d, .clk_i (clk_i),
s_sd_wr_data_q .rst_n_i(rst_n_i),
.dat_i (s_sd_wr_data_d),
.dat_o (s_sd_wr_data_q)
); );
dffr #(32) u_word_data_dffr ( dffr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_word_data_dffr (
s_word_data_d, .clk_i (clk_i),
s_word_data_q .rst_n_i(rst_n_i),
.dat_i (s_word_data_d),
.dat_o (s_word_data_q)
); );
always_ff @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i or negedge rst_n_i) begin
@@ -241,11 +257,13 @@ module spisd_cache (
if (wr_sync_i) s_wr_sync_d = 1'b1; if (wr_sync_i) s_wr_sync_d = 1'b1;
else if (wr_sync_done_o) s_wr_sync_d = 1'b0; else if (wr_sync_done_o) s_wr_sync_d = 1'b0;
end end
dffr #(1) u_wr_sync_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_wr_sync_dffr (
s_wr_sync_d, .clk_i (clk_i),
s_wr_sync_q .rst_n_i(rst_n_i),
.dat_i (s_wr_sync_d),
.dat_o (s_wr_sync_q)
); );
endmodule endmodule
rtl/ip/ribp/storage/spisd_core.sv
+14 -10
View File
@@ -69,18 +69,22 @@ module spisd_core (
s_nor_clkdiv_cnt_d = s_nor_clkdiv_cnt_q + 1'b1; s_nor_clkdiv_cnt_d = s_nor_clkdiv_cnt_q + 1'b1;
end end
end end
dffr #(2) u_nor_clkdiv_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_nor_clkdiv_dffr (
s_nor_clkdiv_cnt_d, .clk_i (clk_i),
s_nor_clkdiv_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_nor_clkdiv_cnt_d),
.dat_o (s_nor_clkdiv_cnt_q)
); );
dffrh #(1) u_nor_clk_dffrh ( dffrh #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_nor_clk_dffrh (
s_nor_clk_d, .clk_i (clk_i),
s_nor_clk_q .rst_n_i(rst_n_i),
.dat_i (s_nor_clk_d),
.dat_o (s_nor_clk_q)
); );
rtl/ip/ribp/storage/spisd_data.sv
+12 -12
View File
@@ -33,13 +33,13 @@ module spisd_data (
input logic wr_busy_i input logic wr_busy_i
); );
reg sd_init_done_d0; logic sd_init_done_d0;
reg sd_init_done_d1; logic sd_init_done_d1;
reg wr_busy_d0; logic wr_busy_d0;
reg wr_busy_d1; logic wr_busy_d1;
reg [ 7:0] wr_data_t; logic [ 7:0] wr_data_t;
reg [ 7:0] rd_comp_data; logic [ 7:0] rd_comp_data;
reg [ 8:0] rd_right_cnt; logic [ 8:0] rd_right_cnt;
logic s_pos_init_done; logic s_pos_init_done;
logic s_neg_wr_busy; logic s_neg_wr_busy;
@@ -57,7 +57,7 @@ module spisd_data (
assign s_neg_wr_busy = wr_busy_d1 & (~wr_busy_d0); assign s_neg_wr_busy = wr_busy_d1 & (~wr_busy_d0);
assign wr_data_o = wr_data_t; assign wr_data_o = wr_data_t;
always @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin if (!rst_n_i) begin
sd_init_done_d0 <= 1'b0; sd_init_done_d0 <= 1'b0;
sd_init_done_d1 <= 1'b0; sd_init_done_d1 <= 1'b0;
@@ -69,7 +69,7 @@ module spisd_data (
end end
end end
always @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin if (!rst_n_i) begin
r_wr_req <= 1'b0; r_wr_req <= 1'b0;
r_rd_req <= 1'b0; r_rd_req <= 1'b0;
@@ -90,13 +90,13 @@ module spisd_data (
end end
end end
always @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) wr_data_t <= '1; if (!rst_n_i) wr_data_t <= '1;
else if (fir_clk_edge_i && wr_data_req_i) wr_data_t <= wr_data_t + 1'b1; else if (fir_clk_edge_i && wr_data_req_i) wr_data_t <= wr_data_t + 1'b1;
end end
always @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin if (!rst_n_i) begin
wr_busy_d0 <= 1'b0; wr_busy_d0 <= 1'b0;
wr_busy_d1 <= 1'b0; wr_busy_d1 <= 1'b0;
@@ -108,7 +108,7 @@ module spisd_data (
end end
end end
always @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin if (!rst_n_i) begin
rd_comp_data <= '0; rd_comp_data <= '0;
rd_right_cnt <= '0; rd_right_cnt <= '0;
rtl/ip/ribp/storage/spisd_init.sv
+31 -23
View File
@@ -79,18 +79,22 @@ module spisd_init (
s_div_cnt_d = s_div_cnt_q - 1'b1; s_div_cnt_d = s_div_cnt_q - 1'b1;
end end
end end
dffrh #(8) u_div_cnt_dffrh ( dffrh #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_div_cnt_dffrh (
s_div_cnt_d, .clk_i (clk_i),
s_div_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_div_cnt_d),
.dat_o (s_div_cnt_q)
); );
dffrh #(1) u_div_clk_dffrh ( dffrh #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_div_clk_dffrh (
s_div_clk_d, .clk_i (clk_i),
s_div_clk_q .rst_n_i(rst_n_i),
.dat_i (s_div_clk_d),
.dat_o (s_div_clk_q)
); );
always_comb begin always_comb begin
@@ -103,12 +107,14 @@ module spisd_init (
end end
end end
end end
dfferh #(7) u_boot_cnt_dfferh ( dfferh #(
clk_i, .DATA_WIDTH(7)
rst_n_i, ) u_boot_cnt_dfferh (
s_fir_clk_edge, .clk_i (clk_i),
s_boot_cnt_d, .rst_n_i(rst_n_i),
s_boot_cnt_q .en_i (s_fir_clk_edge),
.dat_i (s_boot_cnt_d),
.dat_o (s_boot_cnt_q)
); );
@@ -175,15 +181,17 @@ module spisd_init (
default: s_fsm_d = FSM_IDLE; default: s_fsm_d = FSM_IDLE;
endcase endcase
end end
dffer #(3) u_fsm_dffer ( dffer #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_fsm_dffer (
s_fir_clk_edge, .clk_i (clk_i),
s_fsm_d, .rst_n_i(rst_n_i),
s_fsm_q .en_i (s_fir_clk_edge),
.dat_i (s_fsm_d),
.dat_o (s_fsm_q)
); );
always @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin if (!rst_n_i) begin
r_init_done <= '0; r_init_done <= '0;
r_spisd_cs <= '1; r_spisd_cs <= '1;
rtl/ip/ribp/storage/spisd_reg.sv
+54 -42
View File
@@ -48,7 +48,7 @@ module spisd_reg (
logic [1:0] s_spisd_clkdiv_d, s_spisd_clkdiv_q; logic [1:0] s_spisd_clkdiv_d, s_spisd_clkdiv_q;
logic s_spisd_addr_en; logic s_spisd_addr_en;
logic [31:0] s_spisd_addr_d, s_spisd_addr_q; logic [31:0] s_spisd_addr_d, s_spisd_addr_q;
logic [1:0] s_spisd_status_d, s_spisd_status_q; logic [1:0] s_spisd_stat_d, s_spisd_stat_q;
// common // common
logic s_wr_byp, s_rd_byp; logic s_wr_byp, s_rd_byp;
@@ -72,22 +72,26 @@ module spisd_reg (
assign s_spisd_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_MODE; assign s_spisd_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_MODE;
assign s_spisd_mode_d = ribp.wdata[0]; assign s_spisd_mode_d = ribp.wdata[0];
dffer #(1) u_spisd_mode_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_spisd_mode_dffer (
s_spisd_mode_en, .clk_i (clk_i),
s_spisd_mode_d, .rst_n_i(rst_n_i),
s_spisd_mode_q .en_i (s_spisd_mode_en),
.dat_i (s_spisd_mode_d),
.dat_o (s_spisd_mode_q)
); );
assign s_spisd_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_CLKDIV; assign s_spisd_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = ribp.wdata[1:0]; assign s_spisd_clkdiv_d = ribp.wdata[1:0];
dffer #(2) u_spisd_clkdiv_dffer ( dffer #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_spisd_clkdiv_dffer (
s_spisd_clkdiv_en, .clk_i (clk_i),
s_spisd_clkdiv_d, .rst_n_i(rst_n_i),
s_spisd_clkdiv_q .en_i (s_spisd_clkdiv_en),
.dat_i (s_spisd_clkdiv_d),
.dat_o (s_spisd_clkdiv_q)
); );
assign s_spisd_addr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_ADDR; assign s_spisd_addr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_ADDR;
@@ -98,30 +102,34 @@ module spisd_reg (
if (ribp.wstrb[2]) s_spisd_addr_d[23:16] = ribp.wdata[23:16]; if (ribp.wstrb[2]) s_spisd_addr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_spisd_addr_d[31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_spisd_addr_d[31:24] = ribp.wdata[31:24];
end end
dffer #(32) u_spisd_addr_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_spisd_addr_dffer (
s_spisd_addr_en, .clk_i (clk_i),
s_spisd_addr_d, .rst_n_i(rst_n_i),
s_spisd_addr_q .en_i (s_spisd_addr_en),
.dat_i (s_spisd_addr_d),
.dat_o (s_spisd_addr_q)
); );
// 0: init done // 0: init done
// 1: wr sync done // 1: wr sync done
always_comb begin always_comb begin
s_spisd_status_d = s_spisd_status_q; s_spisd_stat_d = s_spisd_stat_q;
s_spisd_status_d[0] = init_done_i; s_spisd_stat_d[0] = init_done_i;
if (wr_sync_done_i && ~s_spisd_status_q[1]) begin if (wr_sync_done_i && ~s_spisd_stat_q[1]) begin
s_spisd_status_d[1] = 1'b1; s_spisd_stat_d[1] = 1'b1;
end else if (s_spisd_status_q[1] && s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_STATUS) begin end else if (s_spisd_stat_q[1] && s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_STATUS) begin
s_spisd_status_d[1] = 1'b0; s_spisd_stat_d[1] = 1'b0;
end end
end end
dffr #(2) u_spisd_status_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_spisd_status_dffr (
s_spisd_status_d, .clk_i (clk_i),
s_spisd_status_q .rst_n_i(rst_n_i),
.dat_i (s_spisd_stat_d),
.dat_o (s_spisd_stat_q)
); );
// software wr sync // software wr sync
@@ -129,11 +137,13 @@ module spisd_reg (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
assign s_ribp_rdata_en = s_ribp_rd_hdshk; assign s_ribp_rdata_en = s_ribp_rd_hdshk;
@@ -143,16 +153,18 @@ module spisd_reg (
`RIBP_SPISD_MODE: s_ribp_rdata_d = {31'd0, s_spisd_mode_q}; `RIBP_SPISD_MODE: s_ribp_rdata_d = {31'd0, s_spisd_mode_q};
`RIBP_SPISD_CLKDIV: s_ribp_rdata_d = {30'd0, s_spisd_clkdiv_q}; `RIBP_SPISD_CLKDIV: s_ribp_rdata_d = {30'd0, s_spisd_clkdiv_q};
`RIBP_SPISD_ADDR: s_ribp_rdata_d = s_spisd_addr_q; `RIBP_SPISD_ADDR: s_ribp_rdata_d = s_spisd_addr_q;
`RIBP_SPISD_STATUS: s_ribp_rdata_d = {30'd0, s_spisd_status_q}; `RIBP_SPISD_STATUS: s_ribp_rdata_d = {30'd0, s_spisd_stat_q};
default: s_ribp_rdata_d = s_ribp_rdata_q; default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase endcase
end end
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
endmodule endmodule
rtl/ip/ribp/storage/xpi_clkgen.sv
+14 -10
View File
@@ -41,18 +41,22 @@ module xpi_clkgen (
s_sclk_d = '0; s_sclk_d = '0;
end end
end end
dffr #(8) u_clkdiv_cnt_dffr ( dffr #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_clkdiv_cnt_dffr (
s_clkdiv_cnt_d, .clk_i (clk_i),
s_clkdiv_cnt_q .rst_n_i(rst_n_i),
.dat_i (s_clkdiv_cnt_d),
.dat_o (s_clkdiv_cnt_q)
); );
dffr #(1) u_sclk_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_sclk_dffr (
s_sclk_d, .clk_i (clk_i),
s_sclk_q .rst_n_i(rst_n_i),
.dat_i (s_sclk_d),
.dat_o (s_sclk_q)
); );
rtl/ip/ribp/storage/xpi_core.sv
+65 -49
View File
@@ -497,73 +497,89 @@ module xpi_core (
end end
endcase endcase
end end
dffer #(3) u_fsm_dffer ( dffer #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_fsm_dffer (
s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg, .clk_i (clk_i),
s_fsm_d, .rst_n_i(rst_n_i),
s_fsm_q .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg),
.dat_i (s_fsm_d),
.dat_o (s_fsm_q)
); );
dfferh #(1) u_nss_dfferh ( dfferh #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_nss_dfferh (
s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg, .clk_i (clk_i),
s_nss_d, .rst_n_i(rst_n_i),
s_nss_q .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg),
.dat_i (s_nss_d),
.dat_o (s_nss_q)
); );
dffer #(1) u_sclk_en_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_sclk_en_dffer (
s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg, .clk_i (clk_i),
s_sclk_en_d, .rst_n_i(rst_n_i),
s_sclk_en_q .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg),
.dat_i (s_sclk_en_d),
.dat_o (s_sclk_en_q)
); );
dffer #(8) u_xfer_bit_cnt_dffer ( dffer #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_xfer_bit_cnt_dffer (
s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg, .clk_i (clk_i),
s_xfer_bit_cnt_d, .rst_n_i(rst_n_i),
s_xfer_bit_cnt_q .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg),
.dat_i (s_xfer_bit_cnt_d),
.dat_o (s_xfer_bit_cnt_q)
); );
dffer #(8) u_xfer_byte_cnt_dffer ( dffer #(
clk_i, .DATA_WIDTH(8)
rst_n_i, ) u_xfer_byte_cnt_dffer (
s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg, .clk_i (clk_i),
s_xfer_byte_cnt_d, .rst_n_i(rst_n_i),
s_xfer_byte_cnt_q .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg),
.dat_i (s_xfer_byte_cnt_d),
.dat_o (s_xfer_byte_cnt_q)
); );
dffer #(32) u_xfer_data_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_xfer_data_dffer (
s_xfer_sta_trg | .clk_i(clk_i),
.rst_n_i(rst_n_i),
.en_i(s_xfer_sta_trg |
(s_fsm_q != FSM_RXDATA && s_sec_clk_edge) | (s_fsm_q != FSM_RXDATA && s_sec_clk_edge) |
(s_fsm_q == FSM_RXDATA && s_fir_clk_edge) | (s_fsm_q == FSM_RXDATA && s_fir_clk_edge) |
s_xfer_end_trg, s_xfer_end_trg),
s_xfer_data_d, .dat_i(s_xfer_data_d),
s_xfer_data_q .dat_o(s_xfer_data_q)
); );
dffer #(1) u_tx_data_req_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_tx_data_req_dffer (
s_xfer_sta_trg | s_sec_clk_edge | s_tx_data_req_q, .clk_i (clk_i),
s_tx_data_req_d, .rst_n_i(rst_n_i),
s_tx_data_req_q .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_tx_data_req_q),
.dat_i (s_tx_data_req_d),
.dat_o (s_tx_data_req_q)
); );
dffer #(1) u_rx_data_req_dffer ( dffer #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_rx_data_req_dffer (
(s_fsm_q == FSM_RXDATA && s_fir_clk_edge) | s_rx_data_req_q, .clk_i (clk_i),
s_rx_data_req_d, .rst_n_i(rst_n_i),
s_rx_data_req_q .en_i ((s_fsm_q == FSM_RXDATA && s_fir_clk_edge) | s_rx_data_req_q),
.dat_i (s_rx_data_req_d),
.dat_o (s_rx_data_req_q)
); );
`ifndef SV_ASSRT_DISABLE `ifndef SV_ASSRT_DISABLE
rtl/ip/ribp/storage/xpi_mm.sv
+30 -22
View File
@@ -74,23 +74,27 @@ module xpi_mm (
else if (s_ribp_wr_hdshk) s_ribp_ready_d = xfer_done_i; else if (s_ribp_wr_hdshk) s_ribp_ready_d = xfer_done_i;
else s_ribp_ready_d = 1'b0; else s_ribp_ready_d = 1'b0;
end end
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
assign rx_pop_valid_o = s_ribp_rd_hdshk; assign rx_pop_valid_o = s_ribp_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk; assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_ribp_rdata_d = (ribp.valid && rx_pop_ready_i) ? rx_pop_data_i : s_ribp_rdata_q; assign s_ribp_rdata_d = (ribp.valid && rx_pop_ready_i) ? rx_pop_data_i : s_ribp_rdata_q;
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
@@ -116,21 +120,25 @@ module xpi_mm (
end end
end end
end end
dffer #(`XPI_LNS_NUM) u_accid_dffer ( dffer #(
clk_i, .DATA_WIDTH(`XPI_LNS_NUM)
rst_n_i, ) u_accid_dffer (
s_mem_valid_re, .clk_i (clk_i),
s_nss_d, .rst_n_i(rst_n_i),
s_nss_q .en_i (s_mem_valid_re),
.dat_i (s_nss_d),
.dat_o (s_nss_q)
); );
// memory-mapped mode // memory-mapped mode
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re ( edge_det_sync_re #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_mem_valid_edge_det_sync_re (
ribp.valid, .clk_i (clk_i),
s_mem_valid_re .rst_n_i(rst_n_i),
.dat_i (ribp.valid),
.re_o (s_mem_valid_re)
); );
always_ff @(posedge clk_i, negedge rst_n_i) begin always_ff @(posedge clk_i, negedge rst_n_i) begin
rtl/ip/ribp/storage/xpi_reg.sv
+325 -207
View File
@@ -182,9 +182,9 @@ module xpi_reg (
logic [ 7:0] s_xpi_hlvlen_d [0:`XPI_NSS_NUM-1]; logic [ 7:0] s_xpi_hlvlen_d [0:`XPI_NSS_NUM-1];
logic [ 7:0] s_xpi_hlvlen_q [0:`XPI_NSS_NUM-1]; logic [ 7:0] s_xpi_hlvlen_q [0:`XPI_NSS_NUM-1];
// status // status
logic s_xpi_status_en; logic s_xpi_stat_en;
logic [ 20:0] s_xpi_status_d; logic [ 20:0] s_xpi_stat_d;
logic [ 20:0] s_xpi_status_q; logic [ 20:0] s_xpi_stat_q;
// flow ctrl // flow ctrl
logic s_tx_fifo_stall_d, s_tx_fifo_stall_q; logic s_tx_fifo_stall_d, s_tx_fifo_stall_q;
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q; logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
@@ -228,12 +228,14 @@ module xpi_reg (
assign s_xpi_cfgidx_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CFGIDX; assign s_xpi_cfgidx_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CFGIDX;
assign s_xpi_cfgidx_d = ribp.wdata[`XPI_LNS_NUM-1:0]; assign s_xpi_cfgidx_d = ribp.wdata[`XPI_LNS_NUM-1:0];
dffer #(`XPI_LNS_NUM) u_xpi_cfgidx_dffer ( dffer #(
clk_i, .DATA_WIDTH(`XPI_LNS_NUM)
rst_n_i, ) u_xpi_cfgidx_dffer (
s_xpi_cfgidx_en, .clk_i (clk_i),
s_xpi_cfgidx_d, .rst_n_i(rst_n_i),
s_xpi_cfgidx_q .en_i (s_xpi_cfgidx_en),
.dat_i (s_xpi_cfgidx_d),
.dat_o (s_xpi_cfgidx_q)
); );
@@ -241,12 +243,16 @@ module xpi_reg (
assign s_xpi_accmd_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ACCMD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_accmd_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ACCMD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_accmd_d[i] = ribp.wdata[0]; assign s_xpi_accmd_d[i] = ribp.wdata[0];
end end
dfferm #(`XPI_NSS_NUM, 1, 1'b1) u_xpi_accmd_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(1),
s_xpi_accmd_en, .INIT_VAL (1'b1)
s_xpi_accmd_d, ) u_xpi_accmd_dfferm (
s_xpi_accmd_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_accmd_en),
.dat_i (s_xpi_accmd_d),
.dat_o (s_xpi_accmd_q)
); );
@@ -261,12 +267,16 @@ module xpi_reg (
if (ribp.wstrb[3]) s_xpi_mmstad_d[i][31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_xpi_mmstad_d[i][31:24] = ribp.wdata[31:24];
end end
end end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_mmdstad_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(32),
s_xpi_mmstad_en, .INIT_VAL (32'd0)
s_xpi_mmstad_d, ) u_xpi_mmdstad_dfferm (
s_xpi_mmstad_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_mmstad_en),
.dat_i (s_xpi_mmstad_d),
.dat_o (s_xpi_mmstad_q)
); );
@@ -280,12 +290,16 @@ module xpi_reg (
if (ribp.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = ribp.wdata[31:24];
end end
end end
dfferm #(`XPI_NSS_NUM, 32, 32'h0200_0000) u_xpi_mmoffst_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(32),
s_xpi_mmoffst_en, .INIT_VAL (32'h0200_0000)
s_xpi_mmoffst_d, ) u_xpi_mmoffst_dfferm (
s_xpi_mmoffst_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_mmoffst_en),
.dat_i (s_xpi_mmoffst_d),
.dat_o (s_xpi_mmoffst_q)
); );
@@ -293,23 +307,29 @@ module xpi_reg (
assign s_xpi_mode_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_MODE && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_mode_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_MODE && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mode_d[i] = ribp.wdata[0]; assign s_xpi_mode_d[i] = ribp.wdata[0];
end end
dfferm #(`XPI_NSS_NUM, 1, 1'b0) u_xpi_mode_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(1),
s_xpi_mode_en, .INIT_VAL (1'b0)
s_xpi_mode_d, ) u_xpi_mode_dfferm (
s_xpi_mode_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_mode_en),
.dat_i (s_xpi_mode_d),
.dat_o (s_xpi_mode_q)
); );
assign s_xpi_nss_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_NSS; assign s_xpi_nss_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_NSS;
assign s_xpi_nss_d = ribp.wdata[`XPI_LNS_NUM-1:0]; assign s_xpi_nss_d = ribp.wdata[`XPI_LNS_NUM-1:0];
dffer #(`XPI_LNS_NUM) u_xpi_nss_dffer ( dffer #(
clk_i, .DATA_WIDTH(`XPI_LNS_NUM)
rst_n_i, ) u_xpi_nss_dffer (
s_xpi_nss_en, .clk_i (clk_i),
s_xpi_nss_d, .rst_n_i(rst_n_i),
s_xpi_nss_q .en_i (s_xpi_nss_en),
.dat_i (s_xpi_nss_d),
.dat_o (s_xpi_nss_q)
); );
@@ -317,12 +337,16 @@ module xpi_reg (
assign s_xpi_clkdiv_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CLKDIV && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_clkdiv_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CLKDIV && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_clkdiv_d[i] = ribp.wdata[7:0]; assign s_xpi_clkdiv_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_clkdiv_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_clkdiv_en, .INIT_VAL (8'd0)
s_xpi_clkdiv_d, ) u_xpi_clkdiv_dfferm (
s_xpi_clkdiv_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_clkdiv_en),
.dat_i (s_xpi_clkdiv_d),
.dat_o (s_xpi_clkdiv_q)
); );
@@ -330,12 +354,16 @@ module xpi_reg (
assign s_xpi_rdwr_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RDWR && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_rdwr_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RDWR && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdwr_d[i] = ribp.wdata[0]; assign s_xpi_rdwr_d[i] = ribp.wdata[0];
end end
dfferm #(`XPI_NSS_NUM, 1, 1'b1) u_xpi_rdwr_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(1),
s_xpi_rdwr_en, .INIT_VAL (1'b1)
s_xpi_rdwr_d, ) u_xpi_rdwr_dfferm (
s_xpi_rdwr_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_rdwr_en),
.dat_i (s_xpi_rdwr_d),
.dat_o (s_xpi_rdwr_q)
); );
@@ -343,12 +371,16 @@ module xpi_reg (
assign s_xpi_revdat_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_REVDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_revdat_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_REVDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_revdat_d[i] = ribp.wdata[0]; assign s_xpi_revdat_d[i] = ribp.wdata[0];
end end
dfferm #(`XPI_NSS_NUM, 1, 1'b0) u_xpi_revdat_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(1),
s_xpi_revdat_en, .INIT_VAL (1'b0)
s_xpi_revdat_d, ) u_xpi_revdat_dfferm (
s_xpi_revdat_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_revdat_en),
.dat_i (s_xpi_revdat_d),
.dat_o (s_xpi_revdat_q)
); );
@@ -356,12 +388,16 @@ module xpi_reg (
assign s_xpi_txupb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_txupb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txupb_d[i] = ribp.wdata[7:0]; assign s_xpi_txupb_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_txupb_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_txupb_en, .INIT_VAL (8'd0)
s_xpi_txupb_d, ) u_xpi_txupb_dfferm (
s_xpi_txupb_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_txupb_en),
.dat_i (s_xpi_txupb_d),
.dat_o (s_xpi_txupb_q)
); );
@@ -369,12 +405,16 @@ module xpi_reg (
assign s_xpi_txlowb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_txlowb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txlowb_d[i] = ribp.wdata[7:0]; assign s_xpi_txlowb_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_txlowb_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_txlowb_en, .INIT_VAL (8'd0)
s_xpi_txlowb_d, ) u_xpi_txlowb_dfferm (
s_xpi_txlowb_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_txlowb_en),
.dat_i (s_xpi_txlowb_d),
.dat_o (s_xpi_txlowb_q)
); );
@@ -382,12 +422,16 @@ module xpi_reg (
assign s_xpi_rxupb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_rxupb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxupb_d[i] = ribp.wdata[5:0]; assign s_xpi_rxupb_d[i] = ribp.wdata[5:0];
end end
dfferm #(`XPI_NSS_NUM, 6, 6'd0) u_xpi_rxupb_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(6),
s_xpi_rxupb_en, .INIT_VAL (6'd0)
s_xpi_rxupb_d, ) u_xpi_rxupb_dfferm (
s_xpi_rxupb_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_rxupb_en),
.dat_i (s_xpi_rxupb_d),
.dat_o (s_xpi_rxupb_q)
); );
@@ -395,12 +439,16 @@ module xpi_reg (
assign s_xpi_rxlowb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_rxlowb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxlowb_d[i] = ribp.wdata[5:0]; assign s_xpi_rxlowb_d[i] = ribp.wdata[5:0];
end end
dfferm #(`XPI_NSS_NUM, 6, 6'd0) u_xpi_rxlowb_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(6),
s_xpi_rxlowb_en, .INIT_VAL (6'd0)
s_xpi_rxlowb_d, ) u_xpi_rxlowb_dfferm (
s_xpi_rxlowb_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_rxlowb_en),
.dat_i (s_xpi_rxlowb_d),
.dat_o (s_xpi_rxlowb_q)
); );
@@ -412,12 +460,16 @@ module xpi_reg (
assign s_xpi_cmdtyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_cmdtyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdtyp_d[i] = ribp.wdata[1:0]; assign s_xpi_cmdtyp_d[i] = ribp.wdata[1:0];
end end
dfferm #(`XPI_NSS_NUM, 2, 2'd1) u_xpi_cmdtyp_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(2),
s_xpi_cmdtyp_en, .INIT_VAL (2'd1)
s_xpi_cmdtyp_d, ) u_xpi_cmdtyp_dfferm (
s_xpi_cmdtyp_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_cmdtyp_en),
.dat_i (s_xpi_cmdtyp_d),
.dat_o (s_xpi_cmdtyp_q)
); );
@@ -425,12 +477,16 @@ module xpi_reg (
assign s_xpi_cmdlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_cmdlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdlen_d[i] = ribp.wdata[2:0]; assign s_xpi_cmdlen_d[i] = ribp.wdata[2:0];
end end
dfferm #(`XPI_NSS_NUM, 3, 3'd1) u_xpi_cmdlen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(3),
s_xpi_cmdlen_en, .INIT_VAL (3'd1)
s_xpi_cmdlen_d, ) u_xpi_cmdlen_dfferm (
s_xpi_cmdlen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_cmdlen_en),
.dat_i (s_xpi_cmdlen_d),
.dat_o (s_xpi_cmdlen_q)
); );
@@ -444,12 +500,16 @@ module xpi_reg (
if (ribp.wstrb[3]) s_xpi_cmddat_d[i][31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_xpi_cmddat_d[i][31:24] = ribp.wdata[31:24];
end end
end end
dfferm #(`XPI_NSS_NUM, 32, 32'hEB00_0000) u_xpi_cmddat_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(32),
s_xpi_cmddat_en, .INIT_VAL (32'hEB00_0000)
s_xpi_cmddat_d, ) u_xpi_cmddat_dfferm (
s_xpi_cmddat_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_cmddat_en),
.dat_i (s_xpi_cmddat_d),
.dat_o (s_xpi_cmddat_q)
); );
@@ -457,12 +517,16 @@ module xpi_reg (
assign s_xpi_adrtyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_adrtyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrtyp_d[i] = ribp.wdata[1:0]; assign s_xpi_adrtyp_d[i] = ribp.wdata[1:0];
end end
dfferm #(`XPI_NSS_NUM, 2, 2'd3) u_xpi_adrtyp_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(2),
s_xpi_adrtyp_en, .INIT_VAL (2'd3)
s_xpi_adrtyp_d, ) u_xpi_adrtyp_dfferm (
s_xpi_adrtyp_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_adrtyp_en),
.dat_i (s_xpi_adrtyp_d),
.dat_o (s_xpi_adrtyp_q)
); );
@@ -470,12 +534,16 @@ module xpi_reg (
assign s_xpi_adrlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_adrlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrlen_d[i] = ribp.wdata[2:0]; assign s_xpi_adrlen_d[i] = ribp.wdata[2:0];
end end
dfferm #(`XPI_NSS_NUM, 3, 3'd4) u_xpi_adrlen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(3),
s_xpi_adrlen_en, .INIT_VAL (3'd4)
s_xpi_adrlen_d, ) u_xpi_adrlen_dfferm (
s_xpi_adrlen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_adrlen_en),
.dat_i (s_xpi_adrlen_d),
.dat_o (s_xpi_adrlen_q)
); );
@@ -489,12 +557,16 @@ module xpi_reg (
if (ribp.wstrb[3]) s_xpi_adrdat_d[i][31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_xpi_adrdat_d[i][31:24] = ribp.wdata[31:24];
end end
end end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_adrdat_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(32),
s_xpi_adrdat_en, .INIT_VAL (32'd0)
s_xpi_adrdat_d, ) u_xpi_adrdat_dfferm (
s_xpi_adrdat_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_adrdat_en),
.dat_i (s_xpi_adrdat_d),
.dat_o (s_xpi_adrdat_q)
); );
@@ -502,12 +574,16 @@ module xpi_reg (
assign s_xpi_alttyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_alttyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_alttyp_d[i] = ribp.wdata[1:0]; assign s_xpi_alttyp_d[i] = ribp.wdata[1:0];
end end
dfferm #(`XPI_NSS_NUM, 2, 2'd0) u_xpi_alttyp_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(2),
s_xpi_alttyp_en, .INIT_VAL (2'd0)
s_xpi_alttyp_d, ) u_xpi_alttyp_dfferm (
s_xpi_alttyp_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_alttyp_en),
.dat_i (s_xpi_alttyp_d),
.dat_o (s_xpi_alttyp_q)
); );
@@ -515,12 +591,16 @@ module xpi_reg (
assign s_xpi_altlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_altlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altlen_d[i] = ribp.wdata[2:0]; assign s_xpi_altlen_d[i] = ribp.wdata[2:0];
end end
dfferm #(`XPI_NSS_NUM, 3, 3'd0) u_xpi_altlen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(3),
s_xpi_altlen_en, .INIT_VAL (3'd0)
s_xpi_altlen_d, ) u_xpi_altlen_dfferm (
s_xpi_altlen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_altlen_en),
.dat_i (s_xpi_altlen_d),
.dat_o (s_xpi_altlen_q)
); );
@@ -534,12 +614,16 @@ module xpi_reg (
if (ribp.wstrb[3]) s_xpi_altdat_d[i][31:24] = ribp.wdata[31:24]; if (ribp.wstrb[3]) s_xpi_altdat_d[i][31:24] = ribp.wdata[31:24];
end end
end end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_altdat_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(32),
s_xpi_altdat_en, .INIT_VAL (32'd0)
s_xpi_altdat_d, ) u_xpi_altdat_dfferm (
s_xpi_altdat_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_altdat_en),
.dat_i (s_xpi_altdat_d),
.dat_o (s_xpi_altdat_q)
); );
@@ -547,12 +631,16 @@ module xpi_reg (
assign s_xpi_tdulen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_tdulen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_tdulen_d[i] = ribp.wdata[7:0]; assign s_xpi_tdulen_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd4) u_xpi_tdulen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_tdulen_en, .INIT_VAL (8'd4)
s_xpi_tdulen_d, ) u_xpi_tdulen_dfferm (
s_xpi_tdulen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_tdulen_en),
.dat_i (s_xpi_tdulen_d),
.dat_o (s_xpi_tdulen_q)
); );
@@ -560,12 +648,16 @@ module xpi_reg (
assign s_xpi_rdulen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_rdulen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdulen_d[i] = ribp.wdata[7:0]; assign s_xpi_rdulen_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd4) u_xpi_rdulen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_rdulen_en, .INIT_VAL (8'd4)
s_xpi_rdulen_d, ) u_xpi_rdulen_dfferm (
s_xpi_rdulen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_rdulen_en),
.dat_i (s_xpi_rdulen_d),
.dat_o (s_xpi_rdulen_q)
); );
@@ -573,12 +665,16 @@ module xpi_reg (
assign s_xpi_dattyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_dattyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_dattyp_d[i] = ribp.wdata[1:0]; assign s_xpi_dattyp_d[i] = ribp.wdata[1:0];
end end
dfferm #(`XPI_NSS_NUM, 2, 2'd3) u_xpi_dattyp_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(2),
s_xpi_dattyp_en, .INIT_VAL (2'd3)
s_xpi_dattyp_d, ) u_xpi_dattyp_dfferm (
s_xpi_dattyp_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_dattyp_en),
.dat_i (s_xpi_dattyp_d),
.dat_o (s_xpi_dattyp_q)
); );
@@ -586,12 +682,16 @@ module xpi_reg (
assign s_xpi_datlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_datlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datlen_d[i] = ribp.wdata[7:0]; assign s_xpi_datlen_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd1) u_xpi_datlen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_datlen_en, .INIT_VAL (8'd1)
s_xpi_datlen_d, ) u_xpi_datlen_dfferm (
s_xpi_datlen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_datlen_en),
.dat_i (s_xpi_datlen_d),
.dat_o (s_xpi_datlen_q)
); );
@@ -599,12 +699,16 @@ module xpi_reg (
assign s_xpi_datbit_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATBIT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_datbit_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATBIT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datbit_d[i] = ribp.wdata[2:0]; assign s_xpi_datbit_d[i] = ribp.wdata[2:0];
end end
dfferm #(`XPI_NSS_NUM, 3, 3'd4) u_xpi_datbit_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(3),
s_xpi_datbit_en, .INIT_VAL (3'd4)
s_xpi_datbit_d, ) u_xpi_datbit_dfferm (
s_xpi_datbit_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_datbit_en),
.dat_i (s_xpi_datbit_d),
.dat_o (s_xpi_datbit_q)
); );
@@ -612,12 +716,16 @@ module xpi_reg (
assign s_xpi_hlvlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_HLVLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q; assign s_xpi_hlvlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_HLVLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_hlvlen_d[i] = ribp.wdata[7:0]; assign s_xpi_hlvlen_d[i] = ribp.wdata[7:0];
end end
dfferm #(`XPI_NSS_NUM, 8, 8'd2) u_xpi_hlvlen_dfferm ( dfferm #(
clk_i, .DATA_NUM (`XPI_NSS_NUM),
rst_n_i, .DATA_WIDTH(8),
s_xpi_hlvlen_en, .INIT_VAL (8'd2)
s_xpi_hlvlen_d, ) u_xpi_hlvlen_dfferm (
s_xpi_hlvlen_q .clk_i (clk_i),
.rst_n_i(rst_n_i),
.en_i (s_xpi_hlvlen_en),
.dat_i (s_xpi_hlvlen_d),
.dat_o (s_xpi_hlvlen_q)
); );
@@ -646,24 +754,26 @@ module xpi_reg (
// [1] tx fifo full // [1] tx fifo full
// [0] xfer done // [0] xfer done
always_comb begin always_comb begin
s_xpi_status_d = s_xpi_status_q; s_xpi_stat_d = s_xpi_stat_q;
s_xpi_status_d[1] = tx_full_i; s_xpi_stat_d[1] = tx_full_i;
s_xpi_status_d[2] = tx_empty_i; s_xpi_stat_d[2] = tx_empty_i;
s_xpi_status_d[3] = rx_full_i; s_xpi_stat_d[3] = rx_full_i;
s_xpi_status_d[4] = rx_empty_i; s_xpi_stat_d[4] = rx_empty_i;
s_xpi_status_d[13:5] = tx_elem_num_i; s_xpi_stat_d[13:5] = tx_elem_num_i;
s_xpi_status_d[20:14] = rx_elem_num_i; s_xpi_stat_d[20:14] = rx_elem_num_i;
if (xfer_done_i) begin if (xfer_done_i) begin
s_xpi_status_d[0] = 1'b1; s_xpi_stat_d[0] = 1'b1;
end else if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_XPI_STATUS) begin end else if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_XPI_STATUS) begin
s_xpi_status_d[0] = 1'b0; s_xpi_stat_d[0] = 1'b0;
end end
end end
dffr #(21) u_xpi_status_dffr ( dffr #(
clk_i, .DATA_WIDTH(21)
rst_n_i, ) u_xpi_status_dffr (
s_xpi_status_d, .clk_i (clk_i),
s_xpi_status_q .rst_n_i(rst_n_i),
.dat_i (s_xpi_stat_d),
.dat_o (s_xpi_stat_q)
); );
@@ -676,11 +786,13 @@ module xpi_reg (
s_tx_fifo_stall_d = 1'b0; s_tx_fifo_stall_d = 1'b0;
end end
end end
dffr #(1) u_tx_fifo_stall_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_tx_fifo_stall_dffr (
s_tx_fifo_stall_d, .clk_i (clk_i),
s_tx_fifo_stall_q .rst_n_i(rst_n_i),
.dat_i (s_tx_fifo_stall_d),
.dat_o (s_tx_fifo_stall_q)
); );
// dma rx flow ctrl // dma rx flow ctrl
@@ -692,21 +804,25 @@ module xpi_reg (
s_rx_fifo_stall_d = 1'b0; s_rx_fifo_stall_d = 1'b0;
end end
end end
dffr #(1) u_rx_fifo_stall_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_rx_fifo_stall_dffr (
s_rx_fifo_stall_d, .clk_i (clk_i),
s_rx_fifo_stall_q .rst_n_i(rst_n_i),
.dat_i (s_rx_fifo_stall_d),
.dat_o (s_rx_fifo_stall_q)
); );
// ribp rd // ribp rd
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q); assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_ribp_ready_dffr (
s_ribp_ready_d, .clk_i (clk_i),
s_ribp_ready_q .rst_n_i(rst_n_i),
.dat_i (s_ribp_ready_d),
.dat_o (s_ribp_ready_q)
); );
// verilog_format: off // verilog_format: off
@@ -750,17 +866,19 @@ module xpi_reg (
else s_ribp_rdata_d = '0; else s_ribp_rdata_d = '0;
end end
end end
`RIBP_XPI_STATUS: s_ribp_rdata_d = {11'd0, s_xpi_status_q}; `RIBP_XPI_STATUS: s_ribp_rdata_d = {11'd0, s_xpi_stat_q};
default: s_ribp_rdata_d = s_ribp_rdata_q; default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase endcase
end end
// verilog_format: on // verilog_format: on
dffer #(32) u_ribp_rdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_ribp_rdata_dffer (
s_ribp_rdata_en, .clk_i (clk_i),
s_ribp_rdata_d, .rst_n_i(rst_n_i),
s_ribp_rdata_q .en_i (s_ribp_rdata_en),
.dat_i (s_ribp_rdata_d),
.dat_o (s_ribp_rdata_q)
); );
endmodule endmodule
rtl/mini/formal/rib2apb_formal.sv
+1 -1
View File
@@ -128,7 +128,7 @@ module rib2apb_formal_design (
assign psel_comb = u_dut.s_psel_comb; assign psel_comb = u_dut.s_psel_comb;
assign psel_q = u_dut.s_psel_q; assign psel_q = u_dut.s_psel_q;
assign xfer_ready = u_dut.s_xfer_ready; assign xfer_ready = u_dut.s_xfer_ready;
assign xfer_error = u_dut.s_xfer_error; assign xfer_error = u_dut.s_xfer_err;
assign rsp_input_valid = u_dut.s_rsp_input_valid; assign rsp_input_valid = u_dut.s_rsp_input_valid;
assign rsp_input_ready = u_dut.s_rsp_input_ready; assign rsp_input_ready = u_dut.s_rsp_input_ready;
assign rsp_input_data = u_dut.s_rsp_input_data; assign rsp_input_data = u_dut.s_rsp_input_data;
rtl/mini/integration/generate_soc_topology.py
+1 -1
View File
@@ -696,7 +696,7 @@ def render_apb_response_mux(targets: list[ApbTarget]) -> str:
for signal, expression, width in ( for signal, expression, width in (
("s_rd_data", "prdata", "32"), ("s_rd_data", "prdata", "32"),
("s_xfer_ready", "pready", "1"), ("s_xfer_ready", "pready", "1"),
("s_xfer_error", "pslverr", "1"), ("s_xfer_err", "pslverr", "1"),
): ):
terms = [ terms = [
f"({{{width}{{s_psel_q[{target.slot}]}}}} & " f"({{{width}{{s_psel_q[{target.slot}]}}}} & "
rtl/mini/top/ahbl2axi4.sv
+18 -6
View File
@@ -154,37 +154,49 @@ module ahbl2axi4 (
end end
end end
dffr #(3) u_fsm_dffr ( dffr #(
.DATA_WIDTH(3)
) u_fsm_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(1) u_write_dffr ( dffr #(
.DATA_WIDTH(1)
) u_write_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_write_d), .dat_i (s_write_d),
.dat_o (s_write_q) .dat_o (s_write_q)
); );
dffr #(3) u_size_dffr ( dffr #(
.DATA_WIDTH(3)
) u_size_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_size_d), .dat_i (s_size_d),
.dat_o (s_size_q) .dat_o (s_size_q)
); );
dffr #(1) u_aw_done_dffr ( dffr #(
.DATA_WIDTH(1)
) u_aw_done_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_aw_done_d), .dat_i (s_aw_done_d),
.dat_o (s_aw_done_q) .dat_o (s_aw_done_q)
); );
dffr #(1) u_w_done_dffr ( dffr #(
.DATA_WIDTH(1)
) u_w_done_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_w_done_d), .dat_i (s_w_done_d),
rtl/mini/top/ahbl2ribp.sv
+12 -4
View File
@@ -121,25 +121,33 @@ module ahbl2ribp (
endcase endcase
end end
dffr #(2) u_fsm_dffr ( dffr #(
.DATA_WIDTH(2)
) u_fsm_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_haddr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_haddr_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_haddr_d), .dat_i (s_haddr_d),
.dat_o (s_haddr_q) .dat_o (s_haddr_q)
); );
dffr #(1) u_hwrite_dffr ( dffr #(
.DATA_WIDTH(1)
) u_hwrite_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_hwrite_d), .dat_i (s_hwrite_d),
.dat_o (s_hwrite_q) .dat_o (s_hwrite_q)
); );
dffr #(3) u_hsize_dffr ( dffr #(
.DATA_WIDTH(3)
) u_hsize_dffr (
.clk_i (ahbl.hclk), .clk_i (ahbl.hclk),
.rst_n_i(ahbl.hresetn), .rst_n_i(ahbl.hresetn),
.dat_i (s_hsize_d), .dat_i (s_hsize_d),
rtl/mini/top/axi42apb.sv
+35 -13
View File
@@ -33,7 +33,7 @@ module axi42apb (
logic [31:0] s_rdata_d, s_rdata_q; logic [31:0] s_rdata_d, s_rdata_q;
logic [1:0] s_resp_d, s_resp_q; logic [1:0] s_resp_d, s_resp_q;
logic [31:0] s_rd_data; logic [31:0] s_rd_data;
logic s_xfer_valid, s_xfer_ready, s_xfer_error; logic s_xfer_valid, s_xfer_ready, s_xfer_err;
logic s_psel_valid; logic s_psel_valid;
`include "soc_apb_declarations.svh" `include "soc_apb_declarations.svh"
@@ -123,7 +123,7 @@ module axi42apb (
FSM_SETP: s_fsm_d = FSM_ENAB; FSM_SETP: s_fsm_d = FSM_ENAB;
FSM_ENAB: begin FSM_ENAB: begin
if (s_xfer_ready) begin if (s_xfer_ready) begin
s_resp_d = s_xfer_error ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY; s_resp_d = s_xfer_err ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY;
if (s_write_q) begin if (s_write_q) begin
s_fsm_d = FSM_WR_RESP; s_fsm_d = FSM_WR_RESP;
end else begin end else begin
@@ -163,67 +163,89 @@ module axi42apb (
endcase endcase
end end
dffr #(4) u_fsm_dffr ( dffr #(
.DATA_WIDTH(4)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(32) u_wdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_wdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wdata_d), .dat_i (s_wdata_d),
.dat_o (s_wdata_q) .dat_o (s_wdata_q)
); );
dffr #(4) u_wstrb_dffr ( dffr #(
.DATA_WIDTH(4)
) u_wstrb_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wstrb_d), .dat_i (s_wstrb_d),
.dat_o (s_wstrb_q) .dat_o (s_wstrb_q)
); );
dffr #(1) u_write_dffr ( dffr #(
.DATA_WIDTH(1)
) u_write_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_write_d), .dat_i (s_write_d),
.dat_o (s_write_q) .dat_o (s_write_q)
); );
dffr #(1) u_id_dffr ( dffr #(
.DATA_WIDTH(1)
) u_id_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_id_d), .dat_i (s_id_d),
.dat_o (s_id_q) .dat_o (s_id_q)
); );
dffr #(8) u_len_dffr ( dffr #(
.DATA_WIDTH(8)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(8) u_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_beat_d), .dat_i (s_beat_d),
.dat_o (s_beat_q) .dat_o (s_beat_q)
); );
dffr #(32) u_rdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_rdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rdata_d), .dat_i (s_rdata_d),
.dat_o (s_rdata_q) .dat_o (s_rdata_q)
); );
dffr #(2) u_resp_dffr ( dffr #(
.DATA_WIDTH(2)
) u_resp_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_resp_d), .dat_i (s_resp_d),
.dat_o (s_resp_q) .dat_o (s_resp_q)
); );
dffr #(NSLV) u_psel_dffr ( dffr #(
.DATA_WIDTH(NSLV)
) u_psel_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i ((s_fsm_q == FSM_DECODE) ? s_psel_comb : s_psel_q), .dat_i ((s_fsm_q == FSM_DECODE) ? s_psel_comb : s_psel_q),
rtl/mini/top/axi42ram.sv
+42 -14
View File
@@ -151,85 +151,113 @@ module axi42ram (
end end
end end
dffr #(1) u_active_dffr ( dffr #(
.DATA_WIDTH(1)
) u_active_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_active_d), .dat_i (s_active_d),
.dat_o (s_active_q) .dat_o (s_active_q)
); );
dffr #(1) u_write_dffr ( dffr #(
.DATA_WIDTH(1)
) u_write_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_write_d), .dat_i (s_write_d),
.dat_o (s_write_q) .dat_o (s_write_q)
); );
dffr #(1) u_id_dffr ( dffr #(
.DATA_WIDTH(1)
) u_id_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_id_d), .dat_i (s_id_d),
.dat_o (s_id_q) .dat_o (s_id_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(8) u_len_dffr ( dffr #(
.DATA_WIDTH(8)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(3) u_size_dffr ( dffr #(
.DATA_WIDTH(3)
) u_size_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_size_d), .dat_i (s_size_d),
.dat_o (s_size_q) .dat_o (s_size_q)
); );
dffr #(8) u_issue_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_issue_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_issue_beat_d), .dat_i (s_issue_beat_d),
.dat_o (s_issue_beat_q) .dat_o (s_issue_beat_q)
); );
dffr #(1) u_issue_valid_dffr ( dffr #(
.DATA_WIDTH(1)
) u_issue_valid_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_issue_valid_d), .dat_i (s_issue_valid_d),
.dat_o (s_issue_valid_q) .dat_o (s_issue_valid_q)
); );
dffr #(8) u_write_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_write_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_write_beat_d), .dat_i (s_write_beat_d),
.dat_o (s_write_beat_q) .dat_o (s_write_beat_q)
); );
dffr #(1) u_bvalid_dffr ( dffr #(
.DATA_WIDTH(1)
) u_bvalid_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bvalid_d), .dat_i (s_bvalid_d),
.dat_o (s_bvalid_q) .dat_o (s_bvalid_q)
); );
dffr #(2) u_bresp_dffr ( dffr #(
.DATA_WIDTH(2)
) u_bresp_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_bresp_d), .dat_i (s_bresp_d),
.dat_o (s_bresp_q) .dat_o (s_bresp_q)
); );
dffr #(1) u_read_pending_dffr ( dffr #(
.DATA_WIDTH(1)
) u_read_pending_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_pending_d), .dat_i (s_read_pending_d),
.dat_o (s_read_pending_q) .dat_o (s_read_pending_q)
); );
dffr #(8) u_read_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_read_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_beat_d), .dat_i (s_read_beat_d),
.dat_o (s_read_beat_q) .dat_o (s_read_beat_q)
); );
dffr #(1) u_read_last_dffr ( dffr #(
.DATA_WIDTH(1)
) u_read_last_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_last_d), .dat_i (s_read_last_d),
rtl/mini/top/axi42ribp.sv
+27 -9
View File
@@ -155,55 +155,73 @@ module axi42ribp (
endcase endcase
end end
dffr #(4) u_fsm_dffr ( dffr #(
.DATA_WIDTH(4)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(32) u_wdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_wdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wdata_d), .dat_i (s_wdata_d),
.dat_o (s_wdata_q) .dat_o (s_wdata_q)
); );
dffr #(4) u_wstrb_dffr ( dffr #(
.DATA_WIDTH(4)
) u_wstrb_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wstrb_d), .dat_i (s_wstrb_d),
.dat_o (s_wstrb_q) .dat_o (s_wstrb_q)
); );
dffr #(1) u_id_dffr ( dffr #(
.DATA_WIDTH(1)
) u_id_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_id_d), .dat_i (s_id_d),
.dat_o (s_id_q) .dat_o (s_id_q)
); );
dffr #(8) u_len_dffr ( dffr #(
.DATA_WIDTH(8)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(8) u_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_beat_d), .dat_i (s_beat_d),
.dat_o (s_beat_q) .dat_o (s_beat_q)
); );
dffr #(32) u_rdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_rdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rdata_d), .dat_i (s_rdata_d),
.dat_o (s_rdata_q) .dat_o (s_rdata_q)
); );
dffr #(2) u_resp_dffr ( dffr #(
.DATA_WIDTH(2)
) u_resp_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_resp_d), .dat_i (s_resp_d),
rtl/mini/top/axi42ribp_burst.sv
+30 -10
View File
@@ -159,61 +159,81 @@ module axi42ribp_burst (
endcase endcase
end end
dffr #(4) u_fsm_dffr ( dffr #(
.DATA_WIDTH(4)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(32) u_wdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_wdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wdata_d), .dat_i (s_wdata_d),
.dat_o (s_wdata_q) .dat_o (s_wdata_q)
); );
dffr #(4) u_wstrb_dffr ( dffr #(
.DATA_WIDTH(4)
) u_wstrb_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wstrb_d), .dat_i (s_wstrb_d),
.dat_o (s_wstrb_q) .dat_o (s_wstrb_q)
); );
dffr #(8) u_len_dffr ( dffr #(
.DATA_WIDTH(8)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(8) u_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_beat_d), .dat_i (s_beat_d),
.dat_o (s_beat_q) .dat_o (s_beat_q)
); );
dffr #(3) u_size_dffr ( dffr #(
.DATA_WIDTH(3)
) u_size_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_size_d), .dat_i (s_size_d),
.dat_o (s_size_q) .dat_o (s_size_q)
); );
dffr #(1) u_id_dffr ( dffr #(
.DATA_WIDTH(1)
) u_id_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_id_d), .dat_i (s_id_d),
.dat_o (s_id_q) .dat_o (s_id_q)
); );
dffr #(32) u_rdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_rdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rdata_d), .dat_i (s_rdata_d),
.dat_o (s_rdata_q) .dat_o (s_rdata_q)
); );
dffr #(2) u_resp_dffr ( dffr #(
.DATA_WIDTH(2)
) u_resp_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_resp_d), .dat_i (s_resp_d),
rtl/mini/top/axi4_error_slave.sv
+12 -4
View File
@@ -78,25 +78,33 @@ module axi4_error_slave #(
endcase endcase
end end
dffr #(2) u_fsm_dffr ( dffr #(
.DATA_WIDTH(2)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(1) u_id_dffr ( dffr #(
.DATA_WIDTH(1)
) u_id_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_id_d), .dat_i (s_id_d),
.dat_o (s_id_q) .dat_o (s_id_q)
); );
dffr #(8) u_len_dffr ( dffr #(
.DATA_WIDTH(8)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(8) u_beat_dffr ( dffr #(
.DATA_WIDTH(8)
) u_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_beat_d), .dat_i (s_beat_d),
rtl/mini/top/axi4_interconnect.sv
+63 -64
View File
@@ -123,12 +123,12 @@ module axi4_interconnect #(
logic [NUM_MASTERS-1:0][ 2:0] r_master_prot; logic [NUM_MASTERS-1:0][ 2:0] r_master_prot;
logic [NUM_MASTERS-1:0][3:0] r_master_qos, r_master_region; logic [NUM_MASTERS-1:0][3:0] r_master_qos, r_master_region;
logic [NUM_MASTERS-1:0] r_master_id, r_master_user; logic [NUM_MASTERS-1:0] r_master_id, r_master_user;
logic [NUM_MASTERS-1:0] r_master_access_error; logic [NUM_MASTERS-1:0] r_master_access_err;
logic [NUM_MASTERS-1:0][3:0] r_master_first_wstrb; logic [NUM_MASTERS-1:0][3:0] r_master_first_wstrb;
logic [NUM_TARGETS-1:0] r_target_valid, r_target_addr_sent; logic [NUM_TARGETS-1:0] r_target_valid, r_target_addr_sent;
logic [NUM_TARGETS-1:0][MASTER_WIDTH-1:0] r_target_owner; logic [NUM_TARGETS-1:0][MASTER_WIDTH-1:0] r_target_owner;
logic [NUM_TARGETS-1:0][ NUM_MASTERS-1:0] s_target_request; logic [NUM_TARGETS-1:0][ NUM_MASTERS-1:0] s_target_req;
logic [NUM_TARGETS-1:0][ NUM_MASTERS-1:0] s_target_grant; logic [NUM_TARGETS-1:0][ NUM_MASTERS-1:0] s_target_grant;
logic [NUM_TARGETS-1:0][MASTER_WIDTH-1:0] s_target_selected; logic [NUM_TARGETS-1:0][MASTER_WIDTH-1:0] s_target_selected;
logic [NUM_TARGETS-1:0] s_target_grant_valid, s_target_advance; logic [NUM_TARGETS-1:0] s_target_grant_valid, s_target_advance;
@@ -252,7 +252,7 @@ module axi4_interconnect #(
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.advance_i (s_target_advance[target]), .advance_i (s_target_advance[target]),
.request_i (s_target_request[target]), .request_i (s_target_req[target]),
.grant_o (s_target_grant[target]), .grant_o (s_target_grant[target]),
.selected_o(s_target_selected[target]), .selected_o(s_target_selected[target]),
.valid_o (s_target_grant_valid[target]) .valid_o (s_target_grant_valid[target])
@@ -304,7 +304,7 @@ module axi4_interconnect #(
t_arid = '0; t_arid = '0;
t_aruser = '0; t_aruser = '0;
t_rready = '0; t_rready = '0;
s_target_request = '0; s_target_req = '0;
s_target_advance = '0; s_target_advance = '0;
s_target_terminal = '0; s_target_terminal = '0;
s_master_terminal = '0; s_master_terminal = '0;
@@ -317,11 +317,11 @@ module axi4_interconnect #(
m_awready[master] = ((master != 1) || user_bus_enable_i) && !m_arvalid[master]; m_awready[master] = ((master != 1) || user_bus_enable_i) && !m_arvalid[master];
if ((m_arvalid[master] && m_arready[master]) || if ((m_arvalid[master] && m_arready[master]) ||
(m_awvalid[master] && m_awready[master])) begin (m_awvalid[master] && m_awready[master])) begin
s_target_request[s_capture_target[master]][master] = 1'b1; s_target_req[s_capture_target[master]][master] = 1'b1;
end end
end end
if (r_master_state[master] == MASTER_PENDING) begin if (r_master_state[master] == MASTER_PENDING) begin
s_target_request[r_master_target[master]][master] = 1'b1; s_target_req[r_master_target[master]][master] = 1'b1;
end end
end end
@@ -388,7 +388,7 @@ module axi4_interconnect #(
s_master_fault_code[owner] = s_master_fault_code[owner] =
(TARGET_WIDTH'(target) == TARGET_DECERR) ? `RIB_RESP_DECERR : (TARGET_WIDTH'(target) == TARGET_DECERR) ? `RIB_RESP_DECERR :
(TARGET_WIDTH'(target) == TARGET_SLVERR) ? (TARGET_WIDTH'(target) == TARGET_SLVERR) ?
(r_master_access_error[owner] ? `RIB_RESP_PROTERR : `RIB_RESP_BURSTERR) : (r_master_access_err[owner] ? `RIB_RESP_PROTERR : `RIB_RESP_BURSTERR) :
`RIB_RESP_SLVERR; `RIB_RESP_SLVERR;
end end
end end
@@ -398,35 +398,34 @@ module axi4_interconnect #(
always_comb begin always_comb begin
for (int master = 0; master < NUM_MASTERS; master++) begin for (int master = 0; master < NUM_MASTERS; master++) begin
automatic logic read_request = m_arvalid[master]; automatic logic read_req = m_arvalid[master];
automatic logic write_request = !read_request && m_awvalid[master]; automatic logic write_req = !read_req && m_awvalid[master];
automatic logic [31:0] address = read_request ? m_araddr[master] : m_awaddr[master]; automatic logic [31:0] addr = read_req ? m_araddr[master] : m_awaddr[master];
automatic logic [ 7:0] length = read_request ? m_arlen[master] : m_awlen[master]; automatic logic [ 7:0] len = read_req ? m_arlen[master] : m_awlen[master];
automatic logic [ 2:0] size = read_request ? m_arsize[master] : m_awsize[master]; automatic logic [ 2:0] size = read_req ? m_arsize[master] : m_awsize[master];
automatic logic [ 1:0] burst = read_request ? m_arburst[master] : m_awburst[master]; automatic logic [ 1:0] burst = read_req ? m_arburst[master] : m_awburst[master];
automatic logic lock = read_request ? m_arlock[master] : m_awlock[master]; automatic logic lock = read_req ? m_arlock[master] : m_awlock[master];
automatic logic [32:0] bytes = 33'(length + 1'b1) << size; automatic logic [32:0] bytes = 33'(len + 1'b1) << size;
s_last_addr[master] = {1'b0, address} + bytes - 1'b1; s_last_addr[master] = {1'b0, addr} + bytes - 1'b1;
s_protocol_legal[master] = (length <= 8'd15) && s_protocol_legal[master] = (len <= 8'd15) &&
(burst == `AXI4_BURST_TYPE_INCR) && !lock && (size <= 3'd2) && (burst == `AXI4_BURST_TYPE_INCR) && !lock && (size <= 3'd2) &&
((address & ((32'd1 << size) - 1'b1)) == '0) && ((addr & ((32'd1 << size) - 1'b1)) == '0) &&
(s_last_addr[master][32] == 1'b0) && (s_last_addr[master][32] == 1'b0) &&
(address[31:12] == s_last_addr[master][31:12]) && (addr[31:12] == s_last_addr[master][31:12]) &&
(decode_target(address) == (decode_target(addr) == decode_target(s_last_addr[master][31:0]));
decode_target(s_last_addr[master][31:0])); s_access_allowed[master] = (master != 1) || ((read_req &&
s_access_allowed[master] = (master != 1) || ((read_request && `SOC_USER_ADDR_READABLE(addr)
`SOC_USER_ADDR_READABLE(address)
&& &&
`SOC_USER_ADDR_READABLE(s_last_addr[master][31:0]) `SOC_USER_ADDR_READABLE(s_last_addr[master][31:0])
) || (write_request && ) || (write_req &&
`SOC_USER_ADDR_WRITABLE(address) `SOC_USER_ADDR_WRITABLE(addr)
&& &&
`SOC_USER_ADDR_WRITABLE(s_last_addr[master][31:0]) `SOC_USER_ADDR_WRITABLE(s_last_addr[master][31:0])
)); ));
s_capture_target[master] = decode_target(address); s_capture_target[master] = decode_target(addr);
if (!s_protocol_legal[master] || if (!s_protocol_legal[master] ||
((s_capture_target[master] == TARGET_CFG || s_capture_target[master] == TARGET_APB) && ((s_capture_target[master] == TARGET_CFG || s_capture_target[master] == TARGET_APB) &&
(length != 8'd0))) begin (len != 8'd0))) begin
s_capture_target[master] = TARGET_SLVERR; s_capture_target[master] = TARGET_SLVERR;
end else if (!s_access_allowed[master]) begin end else if (!s_access_allowed[master]) begin
s_capture_target[master] = TARGET_SLVERR; s_capture_target[master] = TARGET_SLVERR;
@@ -450,7 +449,7 @@ module axi4_interconnect #(
fault_addr_o = r_master_addr[master]; fault_addr_o = r_master_addr[master];
fault_wstrb_o = r_master_first_wstrb[master]; fault_wstrb_o = r_master_first_wstrb[master];
fault_reserved_o = `SOC_ADDR_IS_RESERVED(r_master_addr[master]); fault_reserved_o = `SOC_ADDR_IS_RESERVED(r_master_addr[master]);
fault_access_o = r_master_access_error[master]; fault_access_o = r_master_access_err[master];
fault_master_o = 2'(master); fault_master_o = 2'(master);
fault_code_o = s_master_fault_code[master]; fault_code_o = s_master_fault_code[master];
end end
@@ -459,47 +458,47 @@ module axi4_interconnect #(
always_ff @(posedge clk_i or negedge rst_n_i) begin always_ff @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin if (!rst_n_i) begin
r_master_state <= '0; r_master_state <= '0;
r_master_write <= '0; r_master_write <= '0;
r_master_target <= '0; r_master_target <= '0;
r_master_addr <= '0; r_master_addr <= '0;
r_master_len <= '0; r_master_len <= '0;
r_master_size <= '0; r_master_size <= '0;
r_master_burst <= '0; r_master_burst <= '0;
r_master_lock <= '0; r_master_lock <= '0;
r_master_cache <= '0; r_master_cache <= '0;
r_master_prot <= '0; r_master_prot <= '0;
r_master_qos <= '0; r_master_qos <= '0;
r_master_region <= '0; r_master_region <= '0;
r_master_id <= '0; r_master_id <= '0;
r_master_user <= '0; r_master_user <= '0;
r_master_access_error <= '0; r_master_access_err <= '0;
r_master_first_wstrb <= '0; r_master_first_wstrb <= '0;
r_target_valid <= '0; r_target_valid <= '0;
r_target_addr_sent <= '0; r_target_addr_sent <= '0;
r_target_owner <= '0; r_target_owner <= '0;
end else begin end else begin
for (int master = 0; master < NUM_MASTERS; master++) begin for (int master = 0; master < NUM_MASTERS; master++) begin
if (r_master_state[master] == MASTER_IDLE && if (r_master_state[master] == MASTER_IDLE &&
((m_arvalid[master] && m_arready[master]) || ((m_arvalid[master] && m_arready[master]) ||
(m_awvalid[master] && m_awready[master]))) begin (m_awvalid[master] && m_awready[master]))) begin
automatic logic read_request = m_arvalid[master] && m_arready[master]; automatic logic read_req = m_arvalid[master] && m_arready[master];
r_master_state[master] <= MASTER_PENDING; r_master_state[master] <= MASTER_PENDING;
r_master_write[master] <= !read_request; r_master_write[master] <= !read_req;
r_master_target[master] <= s_capture_target[master]; r_master_target[master] <= s_capture_target[master];
r_master_addr[master] <= read_request ? m_araddr[master] : m_awaddr[master]; r_master_addr[master] <= read_req ? m_araddr[master] : m_awaddr[master];
r_master_len[master] <= read_request ? m_arlen[master] : m_awlen[master]; r_master_len[master] <= read_req ? m_arlen[master] : m_awlen[master];
r_master_size[master] <= read_request ? m_arsize[master] : m_awsize[master]; r_master_size[master] <= read_req ? m_arsize[master] : m_awsize[master];
r_master_burst[master] <= read_request ? m_arburst[master] : m_awburst[master]; r_master_burst[master] <= read_req ? m_arburst[master] : m_awburst[master];
r_master_lock[master] <= read_request ? m_arlock[master] : m_awlock[master]; r_master_lock[master] <= read_req ? m_arlock[master] : m_awlock[master];
r_master_cache[master] <= read_request ? m_arcache[master] : m_awcache[master]; r_master_cache[master] <= read_req ? m_arcache[master] : m_awcache[master];
r_master_prot[master] <= read_request ? m_arprot[master] : m_awprot[master]; r_master_prot[master] <= read_req ? m_arprot[master] : m_awprot[master];
r_master_qos[master] <= read_request ? m_arqos[master] : m_awqos[master]; r_master_qos[master] <= read_req ? m_arqos[master] : m_awqos[master];
r_master_region[master] <= read_request ? m_arregion[master] : m_awregion[master]; r_master_region[master] <= read_req ? m_arregion[master] : m_awregion[master];
r_master_id[master] <= read_request ? m_arid[master] : m_awid[master]; r_master_id[master] <= read_req ? m_arid[master] : m_awid[master];
r_master_user[master] <= read_request ? m_aruser[master] : m_awuser[master]; r_master_user[master] <= read_req ? m_aruser[master] : m_awuser[master];
r_master_access_error[master] <= !s_access_allowed[master]; r_master_access_err[master] <= !s_access_allowed[master];
r_master_first_wstrb[master] <= '0; r_master_first_wstrb[master] <= '0;
end end
if ((r_master_state[master] == MASTER_ACTIVE) && r_master_write[master] && if ((r_master_state[master] == MASTER_ACTIVE) && r_master_write[master] &&
m_wvalid[master] && m_wready[master] && (r_master_first_wstrb[master] == '0)) begin m_wvalid[master] && m_wready[master] && (r_master_first_wstrb[master] == '0)) begin
rtl/mini/top/bus.sv
+138 -102
View File
@@ -64,10 +64,10 @@ module rib_bus (
logic [1:0] s_mstr_id_d, s_mstr_id_q; logic [1:0] s_mstr_id_d, s_mstr_id_q;
logic [1:0] s_mstr_rr_d, s_mstr_rr_q; logic [1:0] s_mstr_rr_d, s_mstr_rr_q;
logic [1:0] s_target_d, s_target_q; logic [1:0] s_target_d, s_target_q;
logic s_user_request; logic s_user_req;
logic s_terminal_rsp; logic s_terminal_rsp;
logic s_ribp_sel, s_apb_sel, s_ram_sel, s_fault_sel; logic s_ribp_sel, s_apb_sel, s_ram_sel, s_fault_sel;
logic s_access_denied, s_burst_legal, s_length_legal; logic s_access_denied, s_burst_legal, s_len_legal;
logic s_user_access_allowed; logic s_user_access_allowed;
logic [31:0] s_last_addr; logic [31:0] s_last_addr;
logic [ 2:0] s_fault_code; logic [ 2:0] s_fault_code;
@@ -121,7 +121,7 @@ module rib_bus (
assign u_ram_rib_if.rsp_last = 1'b0; assign u_ram_rib_if.rsp_last = 1'b0;
`endif `endif
assign s_user_request = user_bus_enable_i && user_rib.cmd_valid; assign s_user_req = user_bus_enable_i && user_rib.cmd_valid;
assign user_bus_idle_o = ~s_mstr_lock_q || (s_mstr_id_q != MSTR_USER); assign user_bus_idle_o = ~s_mstr_lock_q || (s_mstr_id_q != MSTR_USER);
assign s_terminal_rsp = s_cmd_accepted_q && u_mstr_rib_if.rsp_valid && assign s_terminal_rsp = s_cmd_accepted_q && u_mstr_rib_if.rsp_valid &&
u_mstr_rib_if.rsp_ready && u_mstr_rib_if.rsp_ready &&
@@ -137,7 +137,7 @@ module rib_bus (
if (u_mgmt_rib_if.cmd_valid) begin if (u_mgmt_rib_if.cmd_valid) begin
s_mstr_lock_d = 1'b1; s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT; s_mstr_id_d = MSTR_MGMT;
end else if (s_user_request) begin end else if (s_user_req) begin
s_mstr_lock_d = 1'b1; s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_USER; s_mstr_id_d = MSTR_USER;
end else if (dma_rib.cmd_valid) begin end else if (dma_rib.cmd_valid) begin
@@ -146,7 +146,7 @@ module rib_bus (
end end
end end
MSTR_USER: begin MSTR_USER: begin
if (s_user_request) begin if (s_user_req) begin
s_mstr_lock_d = 1'b1; s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_USER; s_mstr_id_d = MSTR_USER;
end else if (dma_rib.cmd_valid) begin end else if (dma_rib.cmd_valid) begin
@@ -164,7 +164,7 @@ module rib_bus (
end else if (u_mgmt_rib_if.cmd_valid) begin end else if (u_mgmt_rib_if.cmd_valid) begin
s_mstr_lock_d = 1'b1; s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT; s_mstr_id_d = MSTR_MGMT;
end else if (s_user_request) begin end else if (s_user_req) begin
s_mstr_lock_d = 1'b1; s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_USER; s_mstr_id_d = MSTR_USER;
end end
@@ -180,23 +180,29 @@ module rib_bus (
end end
end end
dffr #(1) u_mstr_lock_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_mstr_lock_dffr (
s_mstr_lock_d, .clk_i (clk_i),
s_mstr_lock_q .rst_n_i(rst_n_i),
.dat_i (s_mstr_lock_d),
.dat_o (s_mstr_lock_q)
); );
dffr #(2) u_mstr_id_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_mstr_id_dffr (
s_mstr_id_d, .clk_i (clk_i),
s_mstr_id_q .rst_n_i(rst_n_i),
.dat_i (s_mstr_id_d),
.dat_o (s_mstr_id_q)
); );
dffr #(2) u_mstr_rr_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_mstr_rr_dffr (
s_mstr_rr_d, .clk_i (clk_i),
s_mstr_rr_q .rst_n_i(rst_n_i),
.dat_i (s_mstr_rr_d),
.dat_o (s_mstr_rr_q)
); );
always_comb begin always_comb begin
@@ -207,11 +213,13 @@ module rib_bus (
s_cmd_accepted_d = 1'b0; s_cmd_accepted_d = 1'b0;
end end
end end
dffr #(1) u_cmd_accepted_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_cmd_accepted_dffr (
s_cmd_accepted_d, .clk_i (clk_i),
s_cmd_accepted_q .rst_n_i(rst_n_i),
.dat_i (s_cmd_accepted_d),
.dat_o (s_cmd_accepted_q)
); );
// Master mux. The grant is held until the terminal response is consumed. // Master mux. The grant is held until the terminal response is consumed.
@@ -304,11 +312,11 @@ module rib_bus (
// verilog_format: off // verilog_format: off
assign s_last_addr = u_mstr_rib_if.cmd_addr + assign s_last_addr = u_mstr_rib_if.cmd_addr +
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4 ? 32'd12 : 32'd0); (u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4 ? 32'd12 : 32'd0);
assign s_length_legal = assign s_len_legal =
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) || (u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) ||
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4); (u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4);
assign s_burst_legal = assign s_burst_legal =
s_length_legal && s_len_legal &&
((u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) || ((u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) ||
((u_mstr_rib_if.cmd_addr[3:0] == 4'b0000) && ((u_mstr_rib_if.cmd_addr[3:0] == 4'b0000) &&
`SOC_ADDR_SUPPORTS_INCR4(u_mstr_rib_if.cmd_addr) && `SOC_ADDR_SUPPORTS_INCR4(u_mstr_rib_if.cmd_addr) &&
@@ -400,11 +408,13 @@ module rib_bus (
end end
end end
end end
dffr #(2) u_target_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_target_dffr (
s_target_d, .clk_i (clk_i),
s_target_q .rst_n_i(rst_n_i),
.dat_i (s_target_d),
.dat_o (s_target_q)
); );
// Write-data and response routing uses the captured target. // Write-data and response routing uses the captured target.
@@ -503,39 +513,49 @@ module rib_bus (
s_fault_wstrb_d = u_fault_rib_if.wstrb; s_fault_wstrb_d = u_fault_rib_if.wstrb;
end end
end end
dffr #(4) u_fault_wstrb_dffr ( dffr #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_fault_wstrb_dffr (
s_fault_wstrb_d, .clk_i (clk_i),
s_fault_wstrb_q .rst_n_i(rst_n_i),
.dat_i (s_fault_wstrb_d),
.dat_o (s_fault_wstrb_q)
); );
dffer #(32) u_fault_addr_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_fault_addr_dffer (
s_fault_cmd_hdshk, .clk_i (clk_i),
u_mstr_rib_if.cmd_addr, .rst_n_i(rst_n_i),
s_fault_addr_q .en_i (s_fault_cmd_hdshk),
.dat_i (u_mstr_rib_if.cmd_addr),
.dat_o (s_fault_addr_q)
); );
dffer #(2) u_fault_master_dffer ( dffer #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_fault_master_dffer (
s_fault_cmd_hdshk, .clk_i (clk_i),
s_mstr_id_q, .rst_n_i(rst_n_i),
s_fault_master_q .en_i (s_fault_cmd_hdshk),
.dat_i (s_mstr_id_q),
.dat_o (s_fault_master_q)
); );
dffer #(3) u_fault_code_dffer ( dffer #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_fault_code_dffer (
s_fault_cmd_hdshk, .clk_i (clk_i),
s_fault_code, .rst_n_i(rst_n_i),
s_fault_code_q .en_i (s_fault_cmd_hdshk),
.dat_i (s_fault_code),
.dat_o (s_fault_code_q)
); );
dffer #(32) u_xfer_addr_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_xfer_addr_dffer (
u_mstr_rib_if.cmd_valid && u_mstr_rib_if.cmd_ready, .clk_i (clk_i),
u_mstr_rib_if.cmd_addr, .rst_n_i(rst_n_i),
s_xfer_addr_q .en_i (u_mstr_rib_if.cmd_valid && u_mstr_rib_if.cmd_ready),
.dat_i (u_mstr_rib_if.cmd_addr),
.dat_o (s_xfer_addr_q)
); );
assign fault_valid_o = s_cmd_accepted_q && (s_target_q == TARGET_FAULT) && assign fault_valid_o = s_cmd_accepted_q && (s_target_q == TARGET_FAULT) &&
@@ -591,53 +611,69 @@ module rib_bus (
end end
end end
dffr #(64) u_perf_mgmt_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_mgmt_wait_dffr (
s_perf_mgmt_wait_d, .clk_i (clk_i),
s_perf_mgmt_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_mgmt_wait_d),
.dat_o (s_perf_mgmt_wait_q)
); );
dffr #(64) u_perf_user_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_user_wait_dffr (
s_perf_user_wait_d, .clk_i (clk_i),
s_perf_user_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_user_wait_d),
.dat_o (s_perf_user_wait_q)
); );
dffr #(64) u_perf_dma_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_dma_wait_dffr (
s_perf_dma_wait_d, .clk_i (clk_i),
s_perf_dma_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_dma_wait_d),
.dat_o (s_perf_dma_wait_q)
); );
dffr #(64) u_perf_ribp_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_ribp_wait_dffr (
s_perf_ribp_wait_d, .clk_i (clk_i),
s_perf_ribp_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_ribp_wait_d),
.dat_o (s_perf_ribp_wait_q)
); );
dffr #(64) u_perf_apb_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_apb_wait_dffr (
s_perf_apb_wait_d, .clk_i (clk_i),
s_perf_apb_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_apb_wait_d),
.dat_o (s_perf_apb_wait_q)
); );
dffr #(64) u_perf_sdram_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_sdram_wait_dffr (
s_perf_sdram_wait_d, .clk_i (clk_i),
s_perf_sdram_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_sdram_wait_d),
.dat_o (s_perf_sdram_wait_q)
); );
dffr #(64) u_perf_psram_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_psram_wait_dffr (
s_perf_psram_wait_d, .clk_i (clk_i),
s_perf_psram_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_psram_wait_d),
.dat_o (s_perf_psram_wait_q)
); );
dffr #(64) u_perf_flash_wait_dffr ( dffr #(
clk_i, .DATA_WIDTH(64)
rst_n_i, ) u_perf_flash_wait_dffr (
s_perf_flash_wait_d, .clk_i (clk_i),
s_perf_flash_wait_q .rst_n_i(rst_n_i),
.dat_i (s_perf_flash_wait_d),
.dat_o (s_perf_flash_wait_q)
); );
assign perf_mgmt_wait_o = s_perf_mgmt_wait_q; assign perf_mgmt_wait_o = s_perf_mgmt_wait_q;
rtl/mini/top/ip_apb_wrapper.sv
+3 -3
View File
@@ -63,7 +63,7 @@ module ip_apb_wrapper (
32'h0000_FFF8 | {31'd0, ARCHINFO_HAVE_PLL} | 32'h0000_FFF8 | {31'd0, ARCHINFO_HAVE_PLL} |
({31'd0, ARCHINFO_HAVE_SRAM_IF} << 1) | ({31'd0, ARCHINFO_HAVE_SRAM_MACRO} << 2); ({31'd0, ARCHINFO_HAVE_SRAM_IF} << 1) | ({31'd0, ARCHINFO_HAVE_SRAM_MACRO} << 2);
logic s_rng_entropy_enable; logic s_rng_entropy_en;
logic s_rng_entropy_ready; logic s_rng_entropy_ready;
logic s_rng_entropy_valid; logic s_rng_entropy_valid;
logic [31:0] s_rng_entropy_data; logic [31:0] s_rng_entropy_data;
@@ -121,7 +121,7 @@ module ip_apb_wrapper (
rng_deterministic_source u_rng_deterministic_source ( rng_deterministic_source u_rng_deterministic_source (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i (rst_n_i), .rst_n_i (rst_n_i),
.enable_i (s_rng_entropy_enable), .enable_i (s_rng_entropy_en),
.ready_i (s_rng_entropy_ready), .ready_i (s_rng_entropy_ready),
.valid_o (s_rng_entropy_valid), .valid_o (s_rng_entropy_valid),
.data_o (s_rng_entropy_data), .data_o (s_rng_entropy_data),
@@ -132,7 +132,7 @@ module ip_apb_wrapper (
apb4_rng #( apb4_rng #(
.FIFO_DEPTH(8) .FIFO_DEPTH(8)
) u_apb4_rng ( ) u_apb4_rng (
.entropy_enable_o (s_rng_entropy_enable), .entropy_enable_o (s_rng_entropy_en),
.entropy_ready_o (s_rng_entropy_ready), .entropy_ready_o (s_rng_entropy_ready),
.entropy_valid_i (s_rng_entropy_valid), .entropy_valid_i (s_rng_entropy_valid),
.entropy_data_i (s_rng_entropy_data), .entropy_data_i (s_rng_entropy_data),
rtl/mini/top/mgmt_debug_reset.sv
+14 -10
View File
@@ -39,17 +39,21 @@ module mgmt_debug_reset (
end end
end end
dffr #(1) u_pending_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_pending_dffr (
s_pending_d, .clk_i (clk_i),
s_pending_q .rst_n_i(rst_n_i),
.dat_i (s_pending_d),
.dat_o (s_pending_q)
); );
dffr #(1) u_reset_active_dffr ( dffr #(
clk_i, .DATA_WIDTH(1)
rst_n_i, ) u_reset_active_dffr (
s_reset_active_d, .clk_i (clk_i),
s_reset_active_q .rst_n_i(rst_n_i),
.dat_i (s_reset_active_d),
.dat_o (s_reset_active_q)
); );
rst_sync u_core_rst_sync ( rst_sync u_core_rst_sync (
.clk_i (clk_i), .clk_i (clk_i),
rtl/mini/top/rcu.sv
+147 -112
View File
@@ -66,7 +66,7 @@ module rcu #(
logic s_pll_cfg_ready; logic s_pll_cfg_ready;
logic s_pll_cfg_req; logic s_pll_cfg_req;
logic s_pll_cfg_sent_d, s_pll_cfg_sent_q; logic s_pll_cfg_sent_d, s_pll_cfg_sent_q;
logic s_select_ext_clk; logic s_sel_ext_clk;
tc_clk_buf u_xtal_buf ( tc_clk_buf u_xtal_buf (
.clk_i(xtal_clk_i), .clk_i(xtal_clk_i),
@@ -97,11 +97,13 @@ module rcu #(
s_pll_cfg_sent_d = 1'b1; s_pll_cfg_sent_d = 1'b1;
end end
end end
dffr #(1) u_pll_cfg_sent_dffr ( dffr #(
s_ext_clk_buf, .DATA_WIDTH(1)
s_ext_rst_n_sync, ) u_pll_cfg_sent_dffr (
s_pll_cfg_sent_d, .clk_i (s_ext_clk_buf),
s_pll_cfg_sent_q .rst_n_i(s_ext_rst_n_sync),
.dat_i (s_pll_cfg_sent_d),
.dat_o (s_pll_cfg_sent_q)
); );
tc_pll u_tc_pll ( tc_pll u_tc_pll (
.fref_i (s_xtal_clk_buf), .fref_i (s_xtal_clk_buf),
@@ -119,7 +121,7 @@ module rcu #(
tc_clk_switch2 u_sys_clk_switch ( tc_clk_switch2 u_sys_clk_switch (
.clk0_i (s_pll_clk_buf), .clk0_i (s_pll_clk_buf),
.clk1_i (s_ext_clk_buf), .clk1_i (s_ext_clk_buf),
.clk_sel_i(s_select_ext_clk), .clk_sel_i(s_sel_ext_clk),
.clk_o (s_sys_clk) .clk_o (s_sys_clk)
); );
@@ -132,7 +134,7 @@ module rcu #(
.pll_capable_i (s_pll_capable), .pll_capable_i (s_pll_capable),
.pll_sel_o (s_pll_sel), .pll_sel_o (s_pll_sel),
.pll_apply_o (s_pll_apply), .pll_apply_o (s_pll_apply),
.select_ext_clk_o(s_select_ext_clk), .select_ext_clk_o(s_sel_ext_clk),
.pll_ctrl (pll_ctrl) .pll_ctrl (pll_ctrl)
); );
`else `else
@@ -157,11 +159,13 @@ module rcu #(
s_no_pll_rsp_valid_d = 1'b0; s_no_pll_rsp_valid_d = 1'b0;
end end
end end
dffr #(1) u_no_pll_rsp_valid_dffr ( dffr #(
s_ext_clk_buf, .DATA_WIDTH(1)
s_ext_rst_n_sync, ) u_no_pll_rsp_valid_dffr (
s_no_pll_rsp_valid_d, .clk_i (s_ext_clk_buf),
s_no_pll_rsp_valid_q .rst_n_i(s_ext_rst_n_sync),
.dat_i (s_no_pll_rsp_valid_d),
.dat_o (s_no_pll_rsp_valid_q)
); );
`endif `endif
@@ -202,18 +206,22 @@ module rcu #(
); );
assign s_div_cnt_d = (s_div_cnt_q == 4'd1) ? '0 : s_div_cnt_q + 1'b1; assign s_div_cnt_d = (s_div_cnt_q == 4'd1) ? '0 : s_div_cnt_q + 1'b1;
dffr #(4) u_div_cnt_dffr ( dffr #(
sys_clk_o, .DATA_WIDTH(4)
sys_rst_n_o, ) u_div_cnt_dffr (
s_div_cnt_d, .clk_i (sys_clk_o),
s_div_cnt_q .rst_n_i(sys_rst_n_o),
.dat_i (s_div_cnt_d),
.dat_o (s_div_cnt_q)
); );
assign s_sys_clkdiv4_d = (s_div_cnt_q == 4'd1) ? ~s_sys_clkdiv4_q : s_sys_clkdiv4_q; assign s_sys_clkdiv4_d = (s_div_cnt_q == 4'd1) ? ~s_sys_clkdiv4_q : s_sys_clkdiv4_q;
dffr #(1) u_sys_clkdiv4_dffr ( dffr #(
sys_clk_o, .DATA_WIDTH(1)
sys_rst_n_o, ) u_sys_clkdiv4_dffr (
s_sys_clkdiv4_d, .clk_i (sys_clk_o),
s_sys_clkdiv4_q .rst_n_i(sys_rst_n_o),
.dat_i (s_sys_clkdiv4_d),
.dat_o (s_sys_clkdiv4_q)
); );
endmodule endmodule
@@ -247,14 +255,14 @@ module pll_rcu_controller #(
logic [2:0] s_state_d, s_state_q; logic [2:0] s_state_d, s_state_q;
logic [2:0] s_pll_sel_d, s_pll_sel_q; logic [2:0] s_pll_sel_d, s_pll_sel_q;
logic s_pll_apply_d, s_pll_apply_q; logic s_pll_apply_d, s_pll_apply_q;
logic s_select_ext_clk_d, s_select_ext_clk_q; logic s_sel_ext_clk_d, s_sel_ext_clk_q;
logic [15:0] s_lock_count_d, s_lock_count_q; logic [15:0] s_lock_count_d, s_lock_count_q;
logic [2:0] s_active_sel_d, s_active_sel_q; logic [2:0] s_active_sel_d, s_active_sel_q;
logic s_active_valid_d, s_active_valid_q; logic s_active_valid_d, s_active_valid_q;
logic s_safe_clk_d, s_safe_clk_q; logic s_safe_clk_d, s_safe_clk_q;
logic s_lock_d, s_lock_q; logic s_lock_d, s_lock_q;
logic s_lock_seen_low_d, s_lock_seen_low_q; logic s_lock_seen_low_d, s_lock_seen_low_q;
logic [1:0] s_error_d, s_error_q; logic [1:0] s_err_d, s_err_q;
logic s_rsp_valid_d, s_rsp_valid_q; logic s_rsp_valid_d, s_rsp_valid_q;
cdc_2phase #( cdc_2phase #(
@@ -294,45 +302,45 @@ module pll_rcu_controller #(
assign pll_ctrl.rsp_valid_i = s_rsp_sys_valid; assign pll_ctrl.rsp_valid_i = s_rsp_sys_valid;
assign pll_ctrl.capable_i = pll_capable_i; assign pll_ctrl.capable_i = pll_capable_i;
assign s_req_ready = s_state_q == PLL_IDLE; assign s_req_ready = s_state_q == PLL_IDLE;
assign s_rsp_data = {s_error_q, s_lock_q, s_safe_clk_q, s_active_valid_q, s_active_sel_q}; assign s_rsp_data = {s_err_q, s_lock_q, s_safe_clk_q, s_active_valid_q, s_active_sel_q};
assign pll_sel_o = s_pll_sel_q; assign pll_sel_o = s_pll_sel_q;
assign pll_apply_o = s_pll_apply_q; assign pll_apply_o = s_pll_apply_q;
assign select_ext_clk_o = s_select_ext_clk_q; assign select_ext_clk_o = s_sel_ext_clk_q;
always_comb begin always_comb begin
s_state_d = s_state_q; s_state_d = s_state_q;
s_pll_sel_d = s_pll_sel_q; s_pll_sel_d = s_pll_sel_q;
s_pll_apply_d = (s_state_q == PLL_APPLY) || (s_state_q == PLL_WAIT_LOCK); s_pll_apply_d = (s_state_q == PLL_APPLY) || (s_state_q == PLL_WAIT_LOCK);
s_select_ext_clk_d = s_select_ext_clk_q; s_sel_ext_clk_d = s_sel_ext_clk_q;
s_lock_count_d = s_lock_count_q; s_lock_count_d = s_lock_count_q;
s_active_sel_d = s_active_sel_q; s_active_sel_d = s_active_sel_q;
s_active_valid_d = s_active_valid_q; s_active_valid_d = s_active_valid_q;
s_safe_clk_d = s_safe_clk_q; s_safe_clk_d = s_safe_clk_q;
s_lock_d = s_lock_q; s_lock_d = s_lock_q;
s_lock_seen_low_d = s_lock_seen_low_q; s_lock_seen_low_d = s_lock_seen_low_q;
s_error_d = s_error_q; s_err_d = s_err_q;
s_rsp_valid_d = s_rsp_valid_q; s_rsp_valid_d = s_rsp_valid_q;
unique case (s_state_q) unique case (s_state_q)
PLL_IDLE: begin PLL_IDLE: begin
s_lock_seen_low_d = 1'b0; s_lock_seen_low_d = 1'b0;
if (s_req_valid) begin if (s_req_valid) begin
s_pll_sel_d = s_req_sel; s_pll_sel_d = s_req_sel;
s_select_ext_clk_d = 1'b1; s_sel_ext_clk_d = 1'b1;
s_error_d = 2'd0; s_err_d = 2'd0;
s_state_d = PLL_SAFE; s_state_d = PLL_SAFE;
end end
end end
PLL_SAFE: begin PLL_SAFE: begin
s_lock_seen_low_d = 1'b0; s_lock_seen_low_d = 1'b0;
s_select_ext_clk_d = 1'b1; s_sel_ext_clk_d = 1'b1;
s_safe_clk_d = 1'b1; s_safe_clk_d = 1'b1;
s_lock_d = 1'b0; s_lock_d = 1'b0;
if (pll_capable_i) begin if (pll_capable_i) begin
s_state_d = PLL_APPLY; s_state_d = PLL_APPLY;
end else begin end else begin
s_active_valid_d = 1'b0; s_active_valid_d = 1'b0;
s_error_d = 2'd1; s_err_d = 2'd1;
s_state_d = PLL_RESPOND; s_state_d = PLL_RESPOND;
end end
end end
@@ -350,21 +358,21 @@ module pll_rcu_controller #(
s_active_valid_d = 1'b1; s_active_valid_d = 1'b1;
s_safe_clk_d = 1'b0; s_safe_clk_d = 1'b0;
s_lock_d = 1'b1; s_lock_d = 1'b1;
s_error_d = 2'd0; s_err_d = 2'd0;
s_state_d = PLL_SWITCH; s_state_d = PLL_SWITCH;
end else if (s_lock_count_q == LOCK_TIMEOUT - 1) begin end else if (s_lock_count_q == LOCK_TIMEOUT - 1) begin
s_active_valid_d = 1'b0; s_active_valid_d = 1'b0;
s_safe_clk_d = 1'b1; s_safe_clk_d = 1'b1;
s_lock_d = 1'b0; s_lock_d = 1'b0;
s_error_d = 2'd2; s_err_d = 2'd2;
s_state_d = PLL_RESPOND; s_state_d = PLL_RESPOND;
end else begin end else begin
s_lock_count_d = s_lock_count_q + 1'b1; s_lock_count_d = s_lock_count_q + 1'b1;
end end
end end
PLL_SWITCH: begin PLL_SWITCH: begin
s_select_ext_clk_d = 1'b0; s_sel_ext_clk_d = 1'b0;
s_state_d = PLL_RESPOND; s_state_d = PLL_RESPOND;
end end
PLL_RESPOND: begin PLL_RESPOND: begin
s_rsp_valid_d = 1'b1; s_rsp_valid_d = 1'b1;
@@ -379,76 +387,103 @@ module pll_rcu_controller #(
endcase endcase
end end
dffrc #(3, PLL_IDLE) u_state_dffrc ( dffrc #(
ext_clk_i, .DATA_WIDTH(3),
ext_rst_n_i, .RESET_VAL (PLL_IDLE)
s_state_d, ) u_state_dffrc (
s_state_q .clk_i (ext_clk_i),
.rst_n_i(ext_rst_n_i),
.dat_i (s_state_d),
.dat_o (s_state_q)
); );
dffr #(3) u_pll_sel_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(3)
ext_rst_n_i, ) u_pll_sel_dffr (
s_pll_sel_d, .clk_i (ext_clk_i),
s_pll_sel_q .rst_n_i(ext_rst_n_i),
.dat_i (s_pll_sel_d),
.dat_o (s_pll_sel_q)
); );
dffr #(1) u_pll_apply_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(1)
ext_rst_n_i, ) u_pll_apply_dffr (
s_pll_apply_d, .clk_i (ext_clk_i),
s_pll_apply_q .rst_n_i(ext_rst_n_i),
.dat_i (s_pll_apply_d),
.dat_o (s_pll_apply_q)
); );
dffrc #(1, 1'b1) u_select_ext_clk_dffrc ( dffrc #(
ext_clk_i, .DATA_WIDTH(1),
ext_rst_n_i, .RESET_VAL (1'b1)
s_select_ext_clk_d, ) u_select_ext_clk_dffrc (
s_select_ext_clk_q .clk_i (ext_clk_i),
.rst_n_i(ext_rst_n_i),
.dat_i (s_sel_ext_clk_d),
.dat_o (s_sel_ext_clk_q)
); );
dffr #(16) u_lock_count_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(16)
ext_rst_n_i, ) u_lock_count_dffr (
s_lock_count_d, .clk_i (ext_clk_i),
s_lock_count_q .rst_n_i(ext_rst_n_i),
.dat_i (s_lock_count_d),
.dat_o (s_lock_count_q)
); );
dffr #(3) u_active_sel_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(3)
ext_rst_n_i, ) u_active_sel_dffr (
s_active_sel_d, .clk_i (ext_clk_i),
s_active_sel_q .rst_n_i(ext_rst_n_i),
.dat_i (s_active_sel_d),
.dat_o (s_active_sel_q)
); );
dffr #(1) u_active_valid_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(1)
ext_rst_n_i, ) u_active_valid_dffr (
s_active_valid_d, .clk_i (ext_clk_i),
s_active_valid_q .rst_n_i(ext_rst_n_i),
.dat_i (s_active_valid_d),
.dat_o (s_active_valid_q)
); );
dffrc #(1, 1'b1) u_safe_clk_dffrc ( dffrc #(
ext_clk_i, .DATA_WIDTH(1),
ext_rst_n_i, .RESET_VAL (1'b1)
s_safe_clk_d, ) u_safe_clk_dffrc (
s_safe_clk_q .clk_i (ext_clk_i),
.rst_n_i(ext_rst_n_i),
.dat_i (s_safe_clk_d),
.dat_o (s_safe_clk_q)
); );
dffr #(1) u_lock_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(1)
ext_rst_n_i, ) u_lock_dffr (
s_lock_d, .clk_i (ext_clk_i),
s_lock_q .rst_n_i(ext_rst_n_i),
.dat_i (s_lock_d),
.dat_o (s_lock_q)
); );
dffr #(1) u_lock_seen_low_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(1)
ext_rst_n_i, ) u_lock_seen_low_dffr (
s_lock_seen_low_d, .clk_i (ext_clk_i),
s_lock_seen_low_q .rst_n_i(ext_rst_n_i),
.dat_i (s_lock_seen_low_d),
.dat_o (s_lock_seen_low_q)
); );
dffr #(2) u_error_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(2)
ext_rst_n_i, ) u_error_dffr (
s_error_d, .clk_i (ext_clk_i),
s_error_q .rst_n_i(ext_rst_n_i),
.dat_i (s_err_d),
.dat_o (s_err_q)
); );
dffr #(1) u_rsp_valid_dffr ( dffr #(
ext_clk_i, .DATA_WIDTH(1)
ext_rst_n_i, ) u_rsp_valid_dffr (
s_rsp_valid_d, .clk_i (ext_clk_i),
s_rsp_valid_q .rst_n_i(ext_rst_n_i),
.dat_i (s_rsp_valid_d),
.dat_o (s_rsp_valid_q)
); );
endmodule endmodule
rtl/mini/top/retrosoc.sv
+3 -3
View File
@@ -81,7 +81,7 @@ module retrosoc (
logic s_bus_fault_access; logic s_bus_fault_access;
logic [ 1:0] s_bus_fault_master; logic [ 1:0] s_bus_fault_master;
logic [ 2:0] s_bus_fault_code; logic [ 2:0] s_bus_fault_code;
logic s_perf_enable; logic s_perf_en;
logic s_perf_clear; logic s_perf_clear;
logic [ 63:0] s_perf_mgmt_wait; logic [ 63:0] s_perf_mgmt_wait;
logic [ 63:0] s_perf_user_wait; logic [ 63:0] s_perf_user_wait;
@@ -97,7 +97,7 @@ module retrosoc (
assign u_sysctrl_if.fault_access_i = s_bus_fault_access; assign u_sysctrl_if.fault_access_i = s_bus_fault_access;
assign u_sysctrl_if.fault_master_i = s_bus_fault_master; assign u_sysctrl_if.fault_master_i = s_bus_fault_master;
assign u_sysctrl_if.fault_code_i = s_bus_fault_code; assign u_sysctrl_if.fault_code_i = s_bus_fault_code;
assign s_perf_enable = u_sysctrl_if.perf_enable_o; assign s_perf_en = u_sysctrl_if.perf_enable_o;
assign s_perf_clear = u_sysctrl_if.perf_clear_o; assign s_perf_clear = u_sysctrl_if.perf_clear_o;
assign test_done_o = u_sysctrl_if.test_done_o; assign test_done_o = u_sysctrl_if.test_done_o;
assign test_pass_o = u_sysctrl_if.test_pass_o; assign test_pass_o = u_sysctrl_if.test_pass_o;
@@ -161,7 +161,7 @@ core_wrapper u_core_wrapper (
.psram_axi4 (u_psram_axi4_if), .psram_axi4 (u_psram_axi4_if),
.xpi_axi4 (u_xpi_axi4_if), .xpi_axi4 (u_xpi_axi4_if),
.spisd_axi4 (u_spisd_axi4_if), .spisd_axi4 (u_spisd_axi4_if),
.perf_enable_i (s_perf_enable), .perf_enable_i (s_perf_en),
.perf_clear_i (s_perf_clear), .perf_clear_i (s_perf_clear),
.fault_valid_o (s_bus_fault_valid), .fault_valid_o (s_bus_fault_valid),
.fault_addr_o (s_bus_fault_addr), .fault_addr_o (s_bus_fault_addr),
rtl/mini/top/rib2apb.sv
+35 -21
View File
@@ -29,13 +29,13 @@ module rib2apb (
localparam int RSP_WIDTH = 39; localparam int RSP_WIDTH = 39;
logic [31:0] s_rd_data; logic [31:0] s_rd_data;
logic s_xfer_valid, s_xfer_ready, s_xfer_error; logic s_xfer_valid, s_xfer_ready, s_xfer_err;
logic [2:0] s_fsm_d, s_fsm_q; logic [2:0] s_fsm_d, s_fsm_q;
logic [31:0] s_addr_q, s_wdata_q; logic [31:0] s_addr_q, s_wdata_q;
logic [31:0] s_decode_addr; logic [31:0] s_decode_addr;
logic [ 3:0] s_wstrb_q; logic [ 3:0] s_wstrb_q;
logic s_write_q; logic s_write_q;
logic [2:0] s_error_code_d, s_error_code_q; logic [2:0] s_err_code_d, s_err_code_q;
logic s_cmd_hdshk, s_w_hdshk, s_rsp_hdshk; logic s_cmd_hdshk, s_w_hdshk, s_rsp_hdshk;
logic s_psel_valid; logic s_psel_valid;
logic s_rsp_input_valid, s_rsp_input_ready; logic s_rsp_input_valid, s_rsp_input_ready;
@@ -62,9 +62,9 @@ module rib2apb (
assign s_rsp_input_valid = ((s_fsm_q == FSM_ENAB) && s_xfer_ready) || (s_fsm_q == FSM_ERR); assign s_rsp_input_valid = ((s_fsm_q == FSM_ENAB) && s_xfer_ready) || (s_fsm_q == FSM_ERR);
assign s_rsp_input_data = (s_fsm_q == FSM_ENAB) ? assign s_rsp_input_data = (s_fsm_q == FSM_ENAB) ?
{1'b1, 2'd0, s_xfer_error ? `RIB_RESP_SLVERR : `RIB_RESP_OK, s_xfer_error, {1'b1, 2'd0, s_xfer_err ? `RIB_RESP_SLVERR : `RIB_RESP_OK, s_xfer_err,
s_write_q ? 32'd0 : s_rd_data} : s_write_q ? 32'd0 : s_rd_data} :
{1'b1, 2'd0, s_error_code_q, 1'b1, 32'd0}; {1'b1, 2'd0, s_err_code_q, 1'b1, 32'd0};
assign s_rsp_hdshk = s_rsp_input_valid && s_rsp_input_ready; assign s_rsp_hdshk = s_rsp_input_valid && s_rsp_input_ready;
spill_register #( spill_register #(
@@ -89,17 +89,17 @@ module rib2apb (
assign rib.rsp_last = s_rsp_output_data[38]; assign rib.rsp_last = s_rsp_output_data[38];
always_comb begin always_comb begin
s_fsm_d = s_fsm_q; s_fsm_d = s_fsm_q;
s_error_code_d = s_error_code_q; s_err_code_d = s_err_code_q;
unique case (s_fsm_q) unique case (s_fsm_q)
FSM_CMD: begin FSM_CMD: begin
if (s_cmd_hdshk) begin if (s_cmd_hdshk) begin
if (rib.cmd_len != `RIB_LEN_INCR1) begin if (rib.cmd_len != `RIB_LEN_INCR1) begin
s_error_code_d = `RIB_RESP_BURSTERR; s_err_code_d = `RIB_RESP_BURSTERR;
s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_ERR; s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_ERR;
end else if (!s_psel_valid) begin end else if (!s_psel_valid) begin
s_error_code_d = `RIB_RESP_DECERR; s_err_code_d = `RIB_RESP_DECERR;
s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_ERR; s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_ERR;
end else begin end else begin
s_fsm_d = rib.cmd_write ? FSM_WDATA : FSM_SETP; s_fsm_d = rib.cmd_write ? FSM_WDATA : FSM_SETP;
end end
@@ -110,8 +110,8 @@ module rib2apb (
if (rib.wlast) begin if (rib.wlast) begin
s_fsm_d = FSM_SETP; s_fsm_d = FSM_SETP;
end else begin end else begin
s_error_code_d = `RIB_RESP_BURSTERR; s_err_code_d = `RIB_RESP_BURSTERR;
s_fsm_d = FSM_ERR; s_fsm_d = FSM_ERR;
end end
end end
end end
@@ -129,47 +129,61 @@ module rib2apb (
endcase endcase
end end
dffr #(3) u_fsm_dffr ( dffr #(
.DATA_WIDTH(3)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffer #(32) u_addr_dffer ( dffer #(
.DATA_WIDTH(32)
) u_addr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_cmd_hdshk), .en_i (s_cmd_hdshk),
.dat_i (rib.cmd_addr), .dat_i (rib.cmd_addr),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffer #(1) u_write_dffer ( dffer #(
.DATA_WIDTH(1)
) u_write_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_cmd_hdshk), .en_i (s_cmd_hdshk),
.dat_i (rib.cmd_write), .dat_i (rib.cmd_write),
.dat_o (s_write_q) .dat_o (s_write_q)
); );
dffer #(32) u_wdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_wdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_w_hdshk && (s_fsm_q == FSM_WDATA)), .en_i (s_w_hdshk && (s_fsm_q == FSM_WDATA)),
.dat_i (rib.wdata), .dat_i (rib.wdata),
.dat_o (s_wdata_q) .dat_o (s_wdata_q)
); );
dffer #(4) u_wstrb_dffer ( dffer #(
.DATA_WIDTH(4)
) u_wstrb_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_w_hdshk && (s_fsm_q == FSM_WDATA)), .en_i (s_w_hdshk && (s_fsm_q == FSM_WDATA)),
.dat_i (rib.wstrb), .dat_i (rib.wstrb),
.dat_o (s_wstrb_q) .dat_o (s_wstrb_q)
); );
dffr #(3) u_error_code_dffr ( dffr #(
.DATA_WIDTH(3)
) u_error_code_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_error_code_d), .dat_i (s_err_code_d),
.dat_o (s_error_code_q) .dat_o (s_err_code_q)
); );
dffr #(NSLV) u_psel_dffr ( dffr #(
.DATA_WIDTH(NSLV)
) u_psel_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_cmd_hdshk ? s_psel_comb : s_psel_q), .dat_i (s_cmd_hdshk ? s_psel_comb : s_psel_q),
rtl/mini/top/rib2axi4.sv
+15 -5
View File
@@ -124,31 +124,41 @@ module rib2axi4 (
endcase endcase
end end
dffr #(3) u_fsm_dffr ( dffr #(
.DATA_WIDTH(3)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(2) u_len_dffr ( dffr #(
.DATA_WIDTH(2)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(2) u_beat_dffr ( dffr #(
.DATA_WIDTH(2)
) u_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_beat_d), .dat_i (s_beat_d),
.dat_o (s_beat_q) .dat_o (s_beat_q)
); );
dffr #(1) u_aw_done_dffr ( dffr #(
.DATA_WIDTH(1)
) u_aw_done_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_aw_done_d), .dat_i (s_aw_done_d),
rtl/mini/top/rib2ram.sv
+38 -16
View File
@@ -34,7 +34,7 @@ module rib2ram (
logic [ 1:0] s_read_addr_beat; logic [ 1:0] s_read_addr_beat;
logic s_write_hdshk; logic s_write_hdshk;
logic s_write_rsp_valid; logic s_write_rsp_valid;
logic s_write_rsp_error; logic s_write_rsp_err;
logic s_rsp_input_valid; logic s_rsp_input_valid;
logic s_rsp_input_ready; logic s_rsp_input_ready;
logic [RSP_WIDTH-1:0] s_rsp_input_data; logic [RSP_WIDTH-1:0] s_rsp_input_data;
@@ -45,12 +45,12 @@ module rib2ram (
((s_write_beat_q != s_len_q) || s_rsp_input_ready); ((s_write_beat_q != s_len_q) || s_rsp_input_ready);
assign s_write_hdshk = rib.w_valid && rib.w_ready; assign s_write_hdshk = rib.w_valid && rib.w_ready;
assign s_write_rsp_valid = s_write_hdshk && ((s_write_beat_q == s_len_q) || rib.wlast); assign s_write_rsp_valid = s_write_hdshk && ((s_write_beat_q == s_len_q) || rib.wlast);
assign s_write_rsp_error = s_write_rsp_valid && (rib.wlast != (s_write_beat_q == s_len_q)); assign s_write_rsp_err = s_write_rsp_valid && (rib.wlast != (s_write_beat_q == s_len_q));
assign s_read_issue = s_active_q && ~s_write_q && s_issue_valid_q && assign s_read_issue = s_active_q && ~s_write_q && s_issue_valid_q &&
(~s_read_pending_q || s_rsp_input_ready); (~s_read_pending_q || s_rsp_input_ready);
// ram_if has no read enable. Keep the address on a blocked pending beat so // ram_if has no read enable. Keep the addr on a blocked pending beat so
// a synchronous RAM cannot overwrite ram.rdata before it enters the spill. // a synchronous RAM cannot overwrite ram.rdata before it enters the spill.
always_comb begin always_comb begin
s_read_addr_beat = s_issue_beat_q; s_read_addr_beat = s_issue_beat_q;
@@ -66,8 +66,8 @@ module rib2ram (
assign s_rsp_input_valid = s_write_q ? s_write_rsp_valid : s_read_pending_q; assign s_rsp_input_valid = s_write_q ? s_write_rsp_valid : s_read_pending_q;
assign s_rsp_input_data = s_write_q ? assign s_rsp_input_data = s_write_q ?
{1'b1, s_write_beat_q, {1'b1, s_write_beat_q,
s_write_rsp_error ? `RIB_RESP_BURSTERR : `RIB_RESP_OK, s_write_rsp_err ? `RIB_RESP_BURSTERR : `RIB_RESP_OK,
s_write_rsp_error, 32'd0} : s_write_rsp_err, 32'd0} :
{s_read_last_q, s_read_beat_q, `RIB_RESP_OK, 1'b0, ram.rdata}; {s_read_last_q, s_read_beat_q, `RIB_RESP_OK, 1'b0, ram.rdata};
spill_register #( spill_register #(
@@ -140,70 +140,92 @@ module rib2ram (
end end
end end
dffr #(1) u_active_dffr ( dffr #(
.DATA_WIDTH(1)
) u_active_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_active_d), .dat_i (s_active_d),
.dat_o (s_active_q) .dat_o (s_active_q)
); );
dffer #(1) u_write_dffer ( dffer #(
.DATA_WIDTH(1)
) u_write_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (rib.cmd_valid && rib.cmd_ready), .en_i (rib.cmd_valid && rib.cmd_ready),
.dat_i (rib.cmd_write), .dat_i (rib.cmd_write),
.dat_o (s_write_q) .dat_o (s_write_q)
); );
dffer #(32) u_addr_dffer ( dffer #(
.DATA_WIDTH(32)
) u_addr_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (rib.cmd_valid && rib.cmd_ready), .en_i (rib.cmd_valid && rib.cmd_ready),
.dat_i (rib.cmd_addr), .dat_i (rib.cmd_addr),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffer #(2) u_len_dffer ( dffer #(
.DATA_WIDTH(2)
) u_len_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (rib.cmd_valid && rib.cmd_ready), .en_i (rib.cmd_valid && rib.cmd_ready),
.dat_i (rib.cmd_len), .dat_i (rib.cmd_len),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(2) u_issue_beat_dffr ( dffr #(
.DATA_WIDTH(2)
) u_issue_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_issue_beat_d), .dat_i (s_issue_beat_d),
.dat_o (s_issue_beat_q) .dat_o (s_issue_beat_q)
); );
dffr #(1) u_issue_valid_dffr ( dffr #(
.DATA_WIDTH(1)
) u_issue_valid_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_issue_valid_d), .dat_i (s_issue_valid_d),
.dat_o (s_issue_valid_q) .dat_o (s_issue_valid_q)
); );
dffr #(2) u_write_beat_dffr ( dffr #(
.DATA_WIDTH(2)
) u_write_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_write_beat_d), .dat_i (s_write_beat_d),
.dat_o (s_write_beat_q) .dat_o (s_write_beat_q)
); );
dffr #(1) u_write_done_dffr ( dffr #(
.DATA_WIDTH(1)
) u_write_done_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_write_done_d), .dat_i (s_write_done_d),
.dat_o (s_write_done_q) .dat_o (s_write_done_q)
); );
dffr #(1) u_read_pending_dffr ( dffr #(
.DATA_WIDTH(1)
) u_read_pending_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_pending_d), .dat_i (s_read_pending_d),
.dat_o (s_read_pending_q) .dat_o (s_read_pending_q)
); );
dffr #(2) u_read_beat_dffr ( dffr #(
.DATA_WIDTH(2)
) u_read_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_beat_d), .dat_i (s_read_beat_d),
.dat_o (s_read_beat_q) .dat_o (s_read_beat_q)
); );
dffr #(1) u_read_last_dffr ( dffr #(
.DATA_WIDTH(1)
) u_read_last_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_read_last_d), .dat_i (s_read_last_d),
rtl/mini/top/rib2ribp.sv
+59 -39
View File
@@ -31,8 +31,8 @@ module rib2ribp (
logic [1:0] s_beat_d, s_beat_q; logic [1:0] s_beat_d, s_beat_q;
logic s_write_d, s_write_q; logic s_write_d, s_write_q;
logic [31:0] s_rdata_q; logic [31:0] s_rdata_q;
logic s_error_d, s_error_q; logic s_err_d, s_err_q;
logic [2:0] s_error_code_d, s_error_code_q; logic [2:0] s_err_code_d, s_err_code_q;
logic s_cmd_legal; logic s_cmd_legal;
logic s_cmd_hdshk, s_w_hdshk, s_ribp_hdshk, s_rsp_hdshk; logic s_cmd_hdshk, s_w_hdshk, s_ribp_hdshk, s_rsp_hdshk;
@@ -48,10 +48,10 @@ module rib2ribp (
assign rib.w_ready = (s_fsm_q == FSM_WDATA) || (s_fsm_q == FSM_DROP_WDATA); assign rib.w_ready = (s_fsm_q == FSM_WDATA) || (s_fsm_q == FSM_DROP_WDATA);
assign rib.rsp_valid = s_fsm_q == FSM_RESP; assign rib.rsp_valid = s_fsm_q == FSM_RESP;
assign rib.rdata = s_rdata_q; assign rib.rdata = s_rdata_q;
assign rib.resp_err = s_error_q; assign rib.resp_err = s_err_q;
assign rib.resp_code = s_error_q ? s_error_code_q : `RIB_RESP_OK; assign rib.resp_code = s_err_q ? s_err_code_q : `RIB_RESP_OK;
assign rib.rsp_beat = s_beat_q; assign rib.rsp_beat = s_beat_q;
assign rib.rsp_last = s_write_q || (s_beat_q == s_len_q) || s_error_q; assign rib.rsp_last = s_write_q || (s_beat_q == s_len_q) || s_err_q;
assign ribp.valid = s_fsm_q == FSM_RIBP; assign ribp.valid = s_fsm_q == FSM_RIBP;
assign ribp.addr = s_addr_q; assign ribp.addr = s_addr_q;
@@ -59,22 +59,22 @@ module rib2ribp (
assign ribp.wstrb = s_write_q ? s_wstrb_q : '0; assign ribp.wstrb = s_write_q ? s_wstrb_q : '0;
always_comb begin always_comb begin
s_fsm_d = s_fsm_q; s_fsm_d = s_fsm_q;
s_addr_d = s_addr_q; s_addr_d = s_addr_q;
s_len_d = s_len_q; s_len_d = s_len_q;
s_beat_d = s_beat_q; s_beat_d = s_beat_q;
s_write_d = s_write_q; s_write_d = s_write_q;
s_error_d = s_error_q; s_err_d = s_err_q;
s_error_code_d = s_error_code_q; s_err_code_d = s_err_code_q;
unique case (s_fsm_q) unique case (s_fsm_q)
FSM_CMD: begin FSM_CMD: begin
if (s_cmd_hdshk) begin if (s_cmd_hdshk) begin
s_addr_d = rib.cmd_addr; s_addr_d = rib.cmd_addr;
s_len_d = rib.cmd_len; s_len_d = rib.cmd_len;
s_beat_d = '0; s_beat_d = '0;
s_write_d = rib.cmd_write; s_write_d = rib.cmd_write;
s_error_d = ~s_cmd_legal; s_err_d = ~s_cmd_legal;
s_error_code_d = s_cmd_legal ? `RIB_RESP_OK : `RIB_RESP_BURSTERR; s_err_code_d = s_cmd_legal ? `RIB_RESP_OK : `RIB_RESP_BURSTERR;
if (~s_cmd_legal) begin if (~s_cmd_legal) begin
s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_RESP; s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_RESP;
end else begin end else begin
@@ -85,9 +85,9 @@ module rib2ribp (
FSM_WDATA: begin FSM_WDATA: begin
if (s_w_hdshk) begin if (s_w_hdshk) begin
if (rib.wlast != (s_beat_q == s_len_q)) begin if (rib.wlast != (s_beat_q == s_len_q)) begin
s_error_d = 1'b1; s_err_d = 1'b1;
s_error_code_d = `RIB_RESP_BURSTERR; s_err_code_d = `RIB_RESP_BURSTERR;
s_fsm_d = FSM_RESP; s_fsm_d = FSM_RESP;
end else begin end else begin
s_fsm_d = FSM_RIBP; s_fsm_d = FSM_RIBP;
end end
@@ -96,9 +96,9 @@ module rib2ribp (
FSM_RIBP: begin FSM_RIBP: begin
if (s_ribp_hdshk) begin if (s_ribp_hdshk) begin
if (ribp.resp_err) begin if (ribp.resp_err) begin
s_error_d = 1'b1; s_err_d = 1'b1;
s_error_code_d = `RIB_RESP_SLVERR; s_err_code_d = `RIB_RESP_SLVERR;
s_fsm_d = FSM_RESP; s_fsm_d = FSM_RESP;
end else if (s_write_q) begin end else if (s_write_q) begin
if (s_beat_q == s_len_q) begin if (s_beat_q == s_len_q) begin
s_fsm_d = FSM_RESP; s_fsm_d = FSM_RESP;
@@ -114,7 +114,7 @@ module rib2ribp (
end end
FSM_RESP: begin FSM_RESP: begin
if (s_rsp_hdshk) begin if (s_rsp_hdshk) begin
if (~s_write_q && ~s_error_q && (s_beat_q != s_len_q)) begin if (~s_write_q && ~s_err_q && (s_beat_q != s_len_q)) begin
s_addr_d = s_addr_q + 32'd4; s_addr_d = s_addr_q + 32'd4;
s_beat_d = s_beat_q + 1'b1; s_beat_d = s_beat_q + 1'b1;
s_fsm_d = FSM_RIBP; s_fsm_d = FSM_RIBP;
@@ -136,68 +136,88 @@ module rib2ribp (
endcase endcase
end end
dffr #(3) u_fsm_dffr ( dffr #(
.DATA_WIDTH(3)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(2) u_len_dffr ( dffr #(
.DATA_WIDTH(2)
) u_len_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_len_d), .dat_i (s_len_d),
.dat_o (s_len_q) .dat_o (s_len_q)
); );
dffr #(2) u_beat_dffr ( dffr #(
.DATA_WIDTH(2)
) u_beat_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_beat_d), .dat_i (s_beat_d),
.dat_o (s_beat_q) .dat_o (s_beat_q)
); );
dffr #(1) u_write_dffr ( dffr #(
.DATA_WIDTH(1)
) u_write_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_write_d), .dat_i (s_write_d),
.dat_o (s_write_q) .dat_o (s_write_q)
); );
dffer #(32) u_wdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_wdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_w_hdshk && s_fsm_q == FSM_WDATA), .en_i (s_w_hdshk && s_fsm_q == FSM_WDATA),
.dat_i (rib.wdata), .dat_i (rib.wdata),
.dat_o (s_wdata_q) .dat_o (s_wdata_q)
); );
dffer #(4) u_wstrb_dffer ( dffer #(
.DATA_WIDTH(4)
) u_wstrb_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_w_hdshk && s_fsm_q == FSM_WDATA), .en_i (s_w_hdshk && s_fsm_q == FSM_WDATA),
.dat_i (rib.wstrb), .dat_i (rib.wstrb),
.dat_o (s_wstrb_q) .dat_o (s_wstrb_q)
); );
dffer #(32) u_rdata_dffer ( dffer #(
.DATA_WIDTH(32)
) u_rdata_dffer (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.en_i (s_ribp_hdshk && ~s_write_q), .en_i (s_ribp_hdshk && ~s_write_q),
.dat_i (ribp.rdata), .dat_i (ribp.rdata),
.dat_o (s_rdata_q) .dat_o (s_rdata_q)
); );
dffr #(1) u_error_dffr ( dffr #(
.DATA_WIDTH(1)
) u_error_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_error_d), .dat_i (s_err_d),
.dat_o (s_error_q) .dat_o (s_err_q)
); );
dffr #(3) u_error_code_dffr ( dffr #(
.DATA_WIDTH(3)
) u_error_code_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_error_code_d), .dat_i (s_err_code_d),
.dat_o (s_error_code_q) .dat_o (s_err_code_q)
); );
endmodule endmodule
rtl/mini/top/rib_error_slave.sv
+32 -24
View File
@@ -22,14 +22,14 @@ module rib_error_slave (
logic [1:0] s_fsm_d, s_fsm_q; logic [1:0] s_fsm_d, s_fsm_q;
logic [1:0] s_len_q; logic [1:0] s_len_q;
logic [1:0] s_beat_d, s_beat_q; logic [1:0] s_beat_d, s_beat_q;
logic [2:0] s_error_code_q; logic [2:0] s_err_code_q;
assign rib.cmd_ready = s_fsm_q == FSM_CMD; assign rib.cmd_ready = s_fsm_q == FSM_CMD;
assign rib.w_ready = s_fsm_q == FSM_WDATA; assign rib.w_ready = s_fsm_q == FSM_WDATA;
assign rib.rsp_valid = s_fsm_q == FSM_RESP; assign rib.rsp_valid = s_fsm_q == FSM_RESP;
assign rib.rdata = '0; assign rib.rdata = '0;
assign rib.resp_err = 1'b1; assign rib.resp_err = 1'b1;
assign rib.resp_code = s_error_code_q; assign rib.resp_code = s_err_code_q;
assign rib.rsp_beat = s_beat_q; assign rib.rsp_beat = s_beat_q;
assign rib.rsp_last = 1'b1; assign rib.rsp_last = 1'b1;
@@ -61,31 +61,39 @@ module rib_error_slave (
endcase endcase
end end
dffr #(2) u_fsm_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_fsm_dffr (
s_fsm_d, .clk_i (clk_i),
s_fsm_q .rst_n_i(rst_n_i),
.dat_i (s_fsm_d),
.dat_o (s_fsm_q)
); );
dffer #(2) u_len_dffer ( dffer #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_len_dffer (
rib.cmd_valid && rib.cmd_ready, .clk_i (clk_i),
rib.cmd_len, .rst_n_i(rst_n_i),
s_len_q .en_i (rib.cmd_valid && rib.cmd_ready),
.dat_i (rib.cmd_len),
.dat_o (s_len_q)
); );
dffer #(3) u_error_code_dffer ( dffer #(
clk_i, .DATA_WIDTH(3)
rst_n_i, ) u_error_code_dffer (
rib.cmd_valid && rib.cmd_ready, .clk_i (clk_i),
error_code_i, .rst_n_i(rst_n_i),
s_error_code_q .en_i (rib.cmd_valid && rib.cmd_ready),
.dat_i (error_code_i),
.dat_o (s_err_code_q)
); );
dffr #(2) u_beat_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_beat_dffr (
s_beat_d, .clk_i (clk_i),
s_beat_q .rst_n_i(rst_n_i),
.dat_i (s_beat_d),
.dat_o (s_beat_q)
); );
endmodule endmodule
rtl/mini/top/ribp2axi4.sv
+33 -17
View File
@@ -23,7 +23,7 @@ module ribp2axi4 (
logic s_aw_done_d, s_aw_done_q; logic s_aw_done_d, s_aw_done_q;
logic s_w_done_d, s_w_done_q; logic s_w_done_d, s_w_done_q;
logic [31:0] s_rdata_d, s_rdata_q; logic [31:0] s_rdata_d, s_rdata_q;
logic s_error_d, s_error_q; logic s_err_d, s_err_q;
assign ribp.ready = ((s_fsm_q == FSM_WR_RESP) && axi4.bvalid) || assign ribp.ready = ((s_fsm_q == FSM_WR_RESP) && axi4.bvalid) ||
((s_fsm_q == FSM_RD_RESP) && axi4.rvalid); ((s_fsm_q == FSM_RD_RESP) && axi4.rvalid);
@@ -31,7 +31,7 @@ module ribp2axi4 (
assign ribp.resp_err = ((s_fsm_q == FSM_WR_RESP) && axi4.bvalid) ? assign ribp.resp_err = ((s_fsm_q == FSM_WR_RESP) && axi4.bvalid) ?
(axi4.bresp != `AXI4_RESP_OKAY) : (axi4.bresp != `AXI4_RESP_OKAY) :
((s_fsm_q == FSM_RD_RESP) && axi4.rvalid) ? ((s_fsm_q == FSM_RD_RESP) && axi4.rvalid) ?
(axi4.rresp != `AXI4_RESP_OKAY) : s_error_q; (axi4.rresp != `AXI4_RESP_OKAY) : s_err_q;
assign axi4.awid = '0; assign axi4.awid = '0;
assign axi4.awaddr = s_addr_q; assign axi4.awaddr = s_addr_q;
@@ -73,12 +73,12 @@ module ribp2axi4 (
s_aw_done_d = s_aw_done_q; s_aw_done_d = s_aw_done_q;
s_w_done_d = s_w_done_q; s_w_done_d = s_w_done_q;
s_rdata_d = s_rdata_q; s_rdata_d = s_rdata_q;
s_error_d = s_error_q; s_err_d = s_err_q;
unique case (s_fsm_q) unique case (s_fsm_q)
FSM_IDLE: begin FSM_IDLE: begin
s_aw_done_d = 1'b0; s_aw_done_d = 1'b0;
s_w_done_d = 1'b0; s_w_done_d = 1'b0;
s_error_d = 1'b0; s_err_d = 1'b0;
if (ribp.valid) begin if (ribp.valid) begin
s_addr_d = {ribp.addr[31:2], 2'b00}; s_addr_d = {ribp.addr[31:2], 2'b00};
s_wdata_d = ribp.wdata; s_wdata_d = ribp.wdata;
@@ -96,8 +96,8 @@ module ribp2axi4 (
end end
FSM_WR_RESP: begin FSM_WR_RESP: begin
if (axi4.bvalid && ribp.valid) begin if (axi4.bvalid && ribp.valid) begin
s_error_d = axi4.bresp != `AXI4_RESP_OKAY; s_err_d = axi4.bresp != `AXI4_RESP_OKAY;
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
end end
end end
FSM_RD_ADDR: begin FSM_RD_ADDR: begin
@@ -106,7 +106,7 @@ module ribp2axi4 (
FSM_RD_RESP: begin FSM_RD_RESP: begin
if (axi4.rvalid && ribp.valid) begin if (axi4.rvalid && ribp.valid) begin
s_rdata_d = axi4.rdata; s_rdata_d = axi4.rdata;
s_error_d = axi4.rresp != `AXI4_RESP_OKAY; s_err_d = axi4.rresp != `AXI4_RESP_OKAY;
s_fsm_d = FSM_IDLE; s_fsm_d = FSM_IDLE;
end end
end end
@@ -114,52 +114,68 @@ module ribp2axi4 (
endcase endcase
end end
dffr #(3) u_fsm_dffr ( dffr #(
.DATA_WIDTH(3)
) u_fsm_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_fsm_d), .dat_i (s_fsm_d),
.dat_o (s_fsm_q) .dat_o (s_fsm_q)
); );
dffr #(32) u_addr_dffr ( dffr #(
.DATA_WIDTH(32)
) u_addr_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_addr_d), .dat_i (s_addr_d),
.dat_o (s_addr_q) .dat_o (s_addr_q)
); );
dffr #(32) u_wdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_wdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wdata_d), .dat_i (s_wdata_d),
.dat_o (s_wdata_q) .dat_o (s_wdata_q)
); );
dffr #(4) u_wstrb_dffr ( dffr #(
.DATA_WIDTH(4)
) u_wstrb_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_wstrb_d), .dat_i (s_wstrb_d),
.dat_o (s_wstrb_q) .dat_o (s_wstrb_q)
); );
dffr #(1) u_aw_done_dffr ( dffr #(
.DATA_WIDTH(1)
) u_aw_done_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_aw_done_d), .dat_i (s_aw_done_d),
.dat_o (s_aw_done_q) .dat_o (s_aw_done_q)
); );
dffr #(1) u_w_done_dffr ( dffr #(
.DATA_WIDTH(1)
) u_w_done_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_w_done_d), .dat_i (s_w_done_d),
.dat_o (s_w_done_q) .dat_o (s_w_done_q)
); );
dffr #(32) u_rdata_dffr ( dffr #(
.DATA_WIDTH(32)
) u_rdata_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_rdata_d), .dat_i (s_rdata_d),
.dat_o (s_rdata_q) .dat_o (s_rdata_q)
); );
dffr #(1) u_error_dffr ( dffr #(
.DATA_WIDTH(1)
) u_error_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_error_d), .dat_i (s_err_d),
.dat_o (s_error_q) .dat_o (s_err_q)
); );
endmodule endmodule
rtl/mini/top/ribp2rib.sv
+46 -34
View File
@@ -67,46 +67,58 @@ module ribp2rib #(
end end
if (SYNC_RESET) begin : GEN_SYNC_RESET if (SYNC_RESET) begin : GEN_SYNC_RESET
dffsr #(2) u_fsm_dffsr ( dffsr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_fsm_dffsr (
s_fsm_d, .clk_i (clk_i),
s_fsm_q .rst_n_i(rst_n_i),
.dat_i (s_fsm_d),
.dat_o (s_fsm_q)
); );
dffesr #(32) u_wdata_dffesr ( dffesr #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_wdata_dffesr (
s_cmd_hdshk, .clk_i (clk_i),
ribp.wdata, .rst_n_i(rst_n_i),
s_wdata_q .en_i (s_cmd_hdshk),
.dat_i (ribp.wdata),
.dat_o (s_wdata_q)
); );
dffesr #(4) u_wstrb_dffesr ( dffesr #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_wstrb_dffesr (
s_cmd_hdshk, .clk_i (clk_i),
ribp.wstrb, .rst_n_i(rst_n_i),
s_wstrb_q .en_i (s_cmd_hdshk),
.dat_i (ribp.wstrb),
.dat_o (s_wstrb_q)
); );
end else begin : GEN_ASYNC_RESET end else begin : GEN_ASYNC_RESET
dffr #(2) u_fsm_dffr ( dffr #(
clk_i, .DATA_WIDTH(2)
rst_n_i, ) u_fsm_dffr (
s_fsm_d, .clk_i (clk_i),
s_fsm_q .rst_n_i(rst_n_i),
.dat_i (s_fsm_d),
.dat_o (s_fsm_q)
); );
dffer #(32) u_wdata_dffer ( dffer #(
clk_i, .DATA_WIDTH(32)
rst_n_i, ) u_wdata_dffer (
s_cmd_hdshk, .clk_i (clk_i),
ribp.wdata, .rst_n_i(rst_n_i),
s_wdata_q .en_i (s_cmd_hdshk),
.dat_i (ribp.wdata),
.dat_o (s_wdata_q)
); );
dffer #(4) u_wstrb_dffer ( dffer #(
clk_i, .DATA_WIDTH(4)
rst_n_i, ) u_wstrb_dffer (
s_cmd_hdshk, .clk_i (clk_i),
ribp.wstrb, .rst_n_i(rst_n_i),
s_wstrb_q .en_i (s_cmd_hdshk),
.dat_i (ribp.wstrb),
.dat_o (s_wstrb_q)
); );
end end
rtl/mini/top/ribp_arbiter2.sv
+15 -11
View File
@@ -11,19 +11,19 @@ module ribp_arbiter2 (
); );
logic s_locked_d, s_locked_q; logic s_locked_d, s_locked_q;
logic s_owner_d, s_owner_q; logic s_owner_d, s_owner_q;
logic s_select_data; logic s_sel_data;
assign s_select_data = s_locked_q ? s_owner_q : (!cfg.valid && data.valid); assign s_sel_data = s_locked_q ? s_owner_q : (!cfg.valid && data.valid);
assign target.valid = s_select_data ? data.valid : cfg.valid; assign target.valid = s_sel_data ? data.valid : cfg.valid;
assign target.addr = s_select_data ? data.addr : cfg.addr; assign target.addr = s_sel_data ? data.addr : cfg.addr;
assign target.wdata = s_select_data ? data.wdata : cfg.wdata; assign target.wdata = s_sel_data ? data.wdata : cfg.wdata;
assign target.wstrb = s_select_data ? data.wstrb : cfg.wstrb; assign target.wstrb = s_sel_data ? data.wstrb : cfg.wstrb;
assign cfg.ready = !s_select_data && target.ready; assign cfg.ready = !s_sel_data && target.ready;
assign cfg.rdata = target.rdata; assign cfg.rdata = target.rdata;
assign cfg.resp_err = target.resp_err; assign cfg.resp_err = target.resp_err;
assign data.ready = s_select_data && target.ready; assign data.ready = s_sel_data && target.ready;
assign data.rdata = target.rdata; assign data.rdata = target.rdata;
assign data.resp_err = target.resp_err; assign data.resp_err = target.resp_err;
@@ -32,20 +32,24 @@ module ribp_arbiter2 (
s_owner_d = s_owner_q; s_owner_d = s_owner_q;
if (!s_locked_q && target.valid && !target.ready) begin if (!s_locked_q && target.valid && !target.ready) begin
s_locked_d = 1'b1; s_locked_d = 1'b1;
s_owner_d = s_select_data; s_owner_d = s_sel_data;
end else if (s_locked_q && target.ready) begin end else if (s_locked_q && target.ready) begin
s_locked_d = 1'b0; s_locked_d = 1'b0;
end end
end end
dffr #(1) u_locked_dffr ( dffr #(
.DATA_WIDTH(1)
) u_locked_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_locked_d), .dat_i (s_locked_d),
.dat_o (s_locked_q) .dat_o (s_locked_q)
); );
dffr #(1) u_owner_dffr ( dffr #(
.DATA_WIDTH(1)
) u_owner_dffr (
.clk_i (clk_i), .clk_i (clk_i),
.rst_n_i(rst_n_i), .rst_n_i(rst_n_i),
.dat_i (s_owner_d), .dat_i (s_owner_d),
scripts/README.md
+12
View File
@@ -38,6 +38,18 @@ target checks changed self-owned RTL for positional module connections and
legacy constructs. Existing findings are migrated in module-sized batches and legacy constructs. Existing findings are migrated in module-sized batches and
must not be expanded by a new change. must not be expanded by a new change.
`migrate_rtl_connections.py` is the conservative migration helper for legacy
positional instances. It discovers ANSI-style module declarations in the
production RTL and locked technology/IP trees, rewrites only exact positional
parameter and port lists to named connections, and reports ambiguous instances
without modifying them. Run `make rtl-migrate-connections`, then
`make rtl-format rtl-style-check`; review the generated diff before committing.
`migrate_rtl_names.py` shortens only local identifiers beginning with `s_` or
`r_` (plus local automatic variables such as `read_request`). Public module
ports and interface fields are intentionally unchanged. Run
`make rtl-migrate-names`, then format and lint the resulting diff.
Update or add tests in [`../tests`](../tests) for script behavior. Run Update or add tests in [`../tests`](../tests) for script behavior. Run
`ruff check .` and `python3 -m pytest -q`; build-flow changes also require the `ruff check .` and `python3 -m pytest -q`; build-flow changes also require the
relevant dry-run or regression profile from [`AGENTS.md`](../AGENTS.md). relevant dry-run or regression profile from [`AGENTS.md`](../AGENTS.md).
scripts/check_rtl_style.py
+10 -4
View File
@@ -18,8 +18,9 @@ INSTANCE_RE = re.compile(
) )
LEGACY_ALWAYS_RE = re.compile(r"\balways\s*@") LEGACY_ALWAYS_RE = re.compile(r"\balways\s*@")
DECL_RE = re.compile(r"\b(?:wire|tri|wand|wor)\b") DECL_RE = re.compile(r"\b(?:wire|tri|wand|wor)\b")
LONG_NAME_DECL_RE = re.compile( LONG_LOCAL_RE = re.compile(
r"\b(?:logic|wire|reg)\b[^;\n]*\b(?:command|request|response|address|enable|error|status|counter|configuration|select|length)\b" r"\b[sr]_[A-Za-z0-9_$]*(?:command|request|response|address|enable|error|status|"
r"counter|configuration|select|length)(?:_|$)"
) )
@@ -79,7 +80,12 @@ def instance_issues(path: Path, source: str) -> list[str]:
cursor = index + 1 cursor = index + 1
while cursor < len(lines) and ");" not in lines[cursor]: while cursor < len(lines) and ");" not in lines[cursor]:
text = lines[cursor].strip() text = lines[cursor].strip()
if text and not text.startswith(".") and not text.startswith("//"): if (
text
and not text.startswith(".")
and not text.startswith("//")
and not text.startswith("`")
):
issues.append(f"{path}:{cursor + 1}: positional port connection") issues.append(f"{path}:{cursor + 1}: positional port connection")
break break
cursor += 1 cursor += 1
@@ -95,7 +101,7 @@ def check_file(path: Path, source: str, profile: str) -> list[str]:
issues.append(f"{path}:{number}: use always_ff/always_comb in owned RTL") issues.append(f"{path}:{number}: use always_ff/always_comb in owned RTL")
if re.search(r"\bwire\b", line) and not re.search(r"\binout\s+wire\b", line): if re.search(r"\bwire\b", line) and not re.search(r"\binout\s+wire\b", line):
issues.append(f"{path}:{number}: explicit wire in owned RTL; justify net semantics") issues.append(f"{path}:{number}: explicit wire in owned RTL; justify net semantics")
if LONG_NAME_DECL_RE.search(line) and not line.lstrip().startswith("//"): if LONG_LOCAL_RE.search(line) and not line.lstrip().startswith("//"):
issues.append(f"{path}:{number}: prefer the local short-name abbreviation") issues.append(f"{path}:{number}: prefer the local short-name abbreviation")
return issues return issues
scripts/migrate_rtl_connections.py
+262
View File
@@ -0,0 +1,262 @@
#!/usr/bin/env python3
"""Convert provably positional RTL instances to named connections.
The converter is deliberately conservative. It only rewrites an instance when
the module header is ANSI-style and every positional argument can be matched
to a known port/parameter in the same order. Ambiguous instances are reported
and left unchanged for manual review.
"""
from __future__ import annotations
import argparse
import re
from pathlib import Path
IDENT_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_$]*")
KEYWORDS = {
"input",
"output",
"inout",
"logic",
"wire",
"reg",
"signed",
"unsigned",
"parameter",
"localparam",
"type",
"integer",
"int",
"bit",
"var",
}
def matching(text: str, opening: int) -> int | None:
depth = 0
quote = False
escaped = False
for index in range(opening, len(text)):
char = text[index]
if quote:
if escaped:
escaped = False
elif char == "\\":
escaped = True
elif char == '"':
quote = False
continue
if char == '"':
quote = True
elif char == "(":
depth += 1
elif char == ")":
depth -= 1
if depth == 0:
return index
return None
def split_top(text: str) -> list[str]:
result: list[str] = []
start = 0
paren = bracket = brace = 0
quote = False
escaped = False
for index, char in enumerate(text):
if quote:
if escaped:
escaped = False
elif char == "\\":
escaped = True
elif char == '"':
quote = False
continue
if char == '"':
quote = True
elif char == "(":
paren += 1
elif char == ")":
paren -= 1
elif char == "[":
bracket += 1
elif char == "]":
bracket -= 1
elif char == "{":
brace += 1
elif char == "}":
brace -= 1
elif char == "," and paren == bracket == brace == 0:
result.append(text[start:index])
start = index + 1
result.append(text[start:])
return result
def port_name(chunk: str) -> str | None:
value = re.sub(r"//.*", "", chunk).strip()
if not value or value.startswith("."):
return None
value = re.sub(r"\[[^]]*\]\s*$", "", value).rstrip()
identifiers = [item for item in IDENT_RE.findall(value) if item not in KEYWORDS]
return identifiers[-1] if identifiers else None
def parameter_name(chunk: str) -> str | None:
value = re.sub(r"//.*", "", chunk).strip()
if not value:
return None
match = re.search(r"(?:parameter\s+)?(?:type\s+)?([A-Za-z_][A-Za-z0-9_$]*)\s*(?:=|$)", value)
return match.group(1) if match else None
def module_headers(paths: list[Path]) -> dict[str, tuple[list[str], list[str]]]:
headers: dict[str, tuple[list[str], list[str]]] = {}
pattern = re.compile(r"\bmodule\s+([A-Za-z_][A-Za-z0-9_$]*)")
for path in paths:
source = path.read_text(encoding="utf-8", errors="replace")
for match in pattern.finditer(source):
name = match.group(1)
cursor = match.end()
while cursor < len(source) and source[cursor].isspace():
cursor += 1
params: list[str] = []
if source[cursor:cursor + 2] == "#(":
close = matching(source, cursor + 1)
if close is None:
continue
params = [parameter_name(chunk) for chunk in split_top(source[cursor + 2:close])]
if any(item is None for item in params):
continue
cursor = close + 1
while cursor < len(source) and source[cursor].isspace():
cursor += 1
if cursor >= len(source) or source[cursor] != "(":
continue
close = matching(source, cursor)
if close is None:
continue
ports = [port_name(chunk) for chunk in split_top(source[cursor + 1:close])]
if not ports or any(item is None for item in ports):
continue
headers.setdefault(name, ([item for item in params if item], [item for item in ports if item]))
return headers
def instance_candidates(source: str):
module_re = re.compile(r"(?m)^[ \t]*(?P<module>[A-Za-z_][A-Za-z0-9_$]*)\b")
for match in module_re.finditer(source):
module = match.group("module")
if module in {"module", "if", "for", "while", "case"}:
continue
cursor = match.end()
while cursor < len(source) and source[cursor].isspace():
cursor += 1
param_open = param_close = None
if cursor < len(source) and source[cursor] == "#":
cursor += 1
while cursor < len(source) and source[cursor].isspace():
cursor += 1
if cursor >= len(source) or source[cursor] != "(":
continue
param_open = cursor
param_close = matching(source, cursor)
if param_close is None:
continue
cursor = param_close + 1
while cursor < len(source) and source[cursor].isspace():
cursor += 1
instance_match = re.match(r"u_[A-Za-z_][A-Za-z0-9_$]*", source[cursor:])
if instance_match is None:
continue
cursor += instance_match.end()
while cursor < len(source) and source[cursor].isspace():
cursor += 1
if cursor >= len(source) or source[cursor] != "(":
continue
yield module, param_open, param_close, cursor
def render_named(args: list[str], names: list[str], indent: str) -> str:
rendered: list[str] = []
for index, (name, arg) in enumerate(zip(names, args, strict=True)):
value = arg.strip()
comma = "," if index + 1 < len(args) else ""
rendered.append(f"{indent}.{name}({value}){comma}")
return "\n".join(rendered)
def rewrite(path: Path, headers: dict[str, tuple[list[str], list[str]]], apply: bool) -> tuple[int, int]:
source = path.read_text(encoding="utf-8")
edits: list[tuple[int, int, str]] = []
skipped = 0
for module, param_open, param_close, open_port in instance_candidates(source):
header = headers.get(module)
if header is None:
continue
close_port = matching(source, open_port)
if close_port is None:
skipped += 1
continue
params, ports = header
if param_open is not None and param_close is not None:
param_args = split_top(source[param_open + 1:param_close])
if param_args and not any(arg.strip().startswith(".") for arg in param_args):
if len(param_args) != len(params):
skipped += 1
continue
line_start = source.rfind("\n", 0, param_open) + 1
indent_match = re.match(r"[ \t]*", source[line_start:])
indent = (indent_match.group(0) if indent_match else "") + " "
replacement = render_named(param_args, params, indent)
edits.append((param_open + 1, param_close, "\n" + replacement + "\n" + indent[:-2]))
args = split_top(source[open_port + 1:close_port])
if not args or any(arg.strip().startswith(".") for arg in args):
continue
if len(args) != len(ports):
skipped += 1
continue
line_start = source.rfind("\n", 0, open_port) + 1
indent_match = re.match(r"[ \t]*", source[line_start:])
indent = (indent_match.group(0) if indent_match else "") + " "
replacement = "\n" + render_named(args, ports, indent) + "\n" + (indent[:-2] if len(indent) >= 2 else "")
edits.append((open_port + 1, close_port, replacement))
if apply:
for start, end, replacement in reversed(edits):
source = source[:start] + replacement + source[end:]
path.write_text(source, encoding="utf-8")
return len(edits), skipped
def main() -> int:
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument("--root", type=Path, required=True)
parser.add_argument("--apply", action="store_true")
args = parser.parse_args()
root = args.root.resolve()
production = sorted((root / "rtl/ip").rglob("*.sv")) + sorted((root / "rtl/mini/top").rglob("*.sv"))
declaration_roots = [
root / "rtl/managed/clusterip/common",
root / "rtl/managed/clusterip",
root / "rtl/tech",
]
declarations = [
path
for directory in declaration_roots
for path in sorted(directory.rglob("*.sv"))
if path.is_file()
]
headers = module_headers([*production, *declarations])
total = skipped = 0
for path in production:
changed, ignored = rewrite(path, headers, args.apply)
total += changed
skipped += ignored
print(f"named connections: rewritten={total} ambiguous={skipped} modules={len(headers)}")
return 0
if __name__ == "__main__":
raise SystemExit(main())
scripts/migrate_rtl_names.py
+74
View File
@@ -0,0 +1,74 @@
#!/usr/bin/env python3
"""Shorten long local RTL identifiers without changing public interfaces."""
from __future__ import annotations
import argparse
import re
from pathlib import Path
ABBREVIATIONS = (
("command", "cmd"),
("request", "req"),
("response", "resp"),
("address", "addr"),
("enable", "en"),
("error", "err"),
("status", "stat"),
("counter", "cnt"),
("configuration", "cfg"),
("select", "sel"),
("length", "len"),
)
IDENTIFIER_RE = re.compile(r"\b[A-Za-z_][A-Za-z0-9_$]*\b")
LOCAL_PREFIX_RE = re.compile(r"^[sr]_")
AUTOMATIC_LOCALS = {
"read_request": "read_req",
"write_request": "write_req",
}
def shorten_identifier(identifier: str) -> str:
if identifier in AUTOMATIC_LOCALS:
return AUTOMATIC_LOCALS[identifier]
if not LOCAL_PREFIX_RE.match(identifier):
return identifier
result = identifier
for long_name, short_name in ABBREVIATIONS:
result = re.sub(rf"(?<=_){long_name}(?=_|$)", short_name, result)
return result
def rewrite(path: Path, apply: bool) -> int:
source = path.read_text(encoding="utf-8")
changed = 0
def replace(match: re.Match[str]) -> str:
nonlocal changed
original = match.group(0)
replacement = shorten_identifier(original)
if replacement != original:
changed += 1
return replacement
rewritten = IDENTIFIER_RE.sub(replace, source)
if apply and rewritten != source:
path.write_text(rewritten, encoding="utf-8")
return changed
def main() -> int:
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument("--root", type=Path, required=True)
parser.add_argument("--apply", action="store_true")
args = parser.parse_args()
root = args.root.resolve()
paths = sorted((root / "rtl/ip").rglob("*.sv")) + sorted((root / "rtl/mini/top").rglob("*.sv"))
changed = sum(rewrite(path, args.apply) for path in paths if path.is_file())
print(f"short names: rewritten={changed} files={len(paths)}")
return 0
if __name__ == "__main__":
raise SystemExit(main())
tests/test_rtl_connection_migration.py
+77
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@@ -0,0 +1,77 @@
from __future__ import annotations
import subprocess
import sys
from pathlib import Path
ROOT = Path(__file__).resolve().parents[1]
SCRIPT = ROOT / "scripts/migrate_rtl_connections.py"
NAME_SCRIPT = ROOT / "scripts/migrate_rtl_names.py"
def test_migrates_exact_positional_instance(tmp_path: Path) -> None:
(tmp_path / "rtl/ip/example.sv").parent.mkdir(parents=True)
(tmp_path / "rtl/ip/example.sv").write_text(
"module dffr #(parameter WIDTH = 1) (input logic clk_i, input logic rst_n_i, "
"input logic dat_i, output logic dat_o); endmodule\n"
"module top(input logic clk_i, output logic data_o);\n"
" dffr #(1) u_reg (clk_i, 1'b1, 1'b0, data_o);\n"
"endmodule\n",
encoding="utf-8",
)
result = subprocess.run(
[sys.executable, str(SCRIPT), "--root", str(tmp_path), "--apply"],
text=True,
capture_output=True,
check=False,
)
assert result.returncode == 0, result.stderr
source = (tmp_path / "rtl/ip/example.sv").read_text(encoding="utf-8")
assert ".WIDTH(1)" in source
assert ".clk_i(clk_i)" in source
assert ".dat_o(data_o)" in source
def test_leaves_ambiguous_instance_unchanged(tmp_path: Path) -> None:
(tmp_path / "rtl/ip/example.sv").parent.mkdir(parents=True)
(tmp_path / "rtl/ip/example.sv").write_text(
"module dffr (input logic clk_i, input logic rst_n_i); endmodule\n"
"module top(input logic clk_i);\n"
" dffr u_reg (clk_i, 1'b1, 1'b0);\n"
"endmodule\n",
encoding="utf-8",
)
before = (tmp_path / "rtl/ip/example.sv").read_text(encoding="utf-8")
result = subprocess.run(
[sys.executable, str(SCRIPT), "--root", str(tmp_path), "--apply"],
text=True,
capture_output=True,
check=False,
)
assert result.returncode == 0, result.stderr
assert "ambiguous=1" in result.stdout
assert (tmp_path / "rtl/ip/example.sv").read_text(encoding="utf-8") == before
def test_shortens_local_names_but_not_ports(tmp_path: Path) -> None:
(tmp_path / "rtl/ip/example.sv").parent.mkdir(parents=True)
path = tmp_path / "rtl/ip/example.sv"
path.write_text(
"module example(input logic request_i, output logic response_o);\n"
" logic s_command_enable;\n"
" assign response_o = request_i & s_command_enable;\n"
"endmodule\n",
encoding="utf-8",
)
result = subprocess.run(
[sys.executable, str(NAME_SCRIPT), "--root", str(tmp_path), "--apply"],
text=True,
capture_output=True,
check=False,
)
assert result.returncode == 0, result.stderr
source = path.read_text(encoding="utf-8")
assert "s_cmd_en" in source
assert "request_i" in source
assert "response_o" in source