docs: add diagram and package reference modules with validation and testing

- Introduced for managing diagram dependencies, validating fields, and collecting diagram data. - Added to handle version-qualified publication packages, including validation of package integrity and runtime imports. - Updated to integrate diagram dependencies into source path resolution. - Created to implement comprehensive tests for diagram validation, package integrity, and runtime import checks.
2026-11-06 14:55:14 +00:00 · 2026-09-09 13:04:59 +08:00
1 parent 084226f3a3
commit 6185729265
@@ -64,3 +64,18 @@ is distributed under Apache License 2.0. The artifact retains both exact
 license texts and is materialized only below the ignored `.cache/` tree.
 The preserved third-party notices are included to maintain attribution for code that was adapted or reused in this repository. They do not replace the repository's main license declaration. The retroSoC project itself is distributed under the Mulan PSL v2 license.
 ## 7. Typst publication diagram packages
 The manual publication builder uses these checksum-locked third-party packages.
 Their original sources and notices remain in the verified package caches.
 | Package | Authors | License | Original text |
 | --- | --- | --- | --- |
 | bytefield 0.0.8 | Jomaway <https://github.com/jomaway> | MIT | [Exact license](licenses/Typst-bytefield-0.0.8-LICENSE) |
 | rivet 0.3.1 | Louis Heredero <https://git.kb28.ch/HEL> | Apache-2.0 | [Exact license](licenses/Typst-rivet-0.3.1-LICENSE) |
 | blockcell 0.1.0 | @daleione | MIT | [Exact license](licenses/Typst-blockcell-0.1.0-LICENSE) |
 | circuiteria 0.2.1 | Louis Heredero <https://git.kb28.ch/HEL> | Apache-2.0 | [Exact license](licenses/Typst-circuiteria-0.2.1-LICENSE) |
 | cetz 0.3.4 | Johannes Wolf <https://github.com/johannes-wolf>; fenjalien <https://github.com/fenjalien> | LGPL-3.0-or-later | [Exact license](licenses/Typst-cetz-0.3.4-LICENSE) |
 | tidy 0.3.0 | Mc-Zen <https://github.com/Mc-Zen> | MIT | [Exact license](licenses/Typst-tidy-0.3.0-LICENSE) |
 | oxifmt 0.2.1 | PgBiel <https://github.com/PgBiel> | MIT-0 | [Exact license](licenses/Typst-oxifmt-0.2.1-LICENSE) |
@@ -17,3 +17,11 @@ The following third-party projects or authors are referenced in the RTL source h
  exact source revisions are retained in the downloaded artifact manifest.
 These notices are included solely to preserve attribution for the retained third-party source material. They do not alter the licensing terms of the retroSoC repository itself, which is distributed under the Mulan PSL v2 license.
 ## Typst publication tooling
 The bytefield, rivet, blockcell and circuiteria drawing packages, and their
 CeTZ 0.3.4, tidy 0.3.0 and oxifmt 0.2.1 runtime dependencies, retain their upstream
 licenses and authorship. See the package/version entries in ATTRIBUTIONS.md and
 the exact Typst-*-LICENSE texts in licenses/. The dependency lock and publication
 manifest identify the archives used for each document build.
@@ -5,8 +5,11 @@ archives, OCI base images, Nix inputs, checksums, and CI tool bundles. Its diges
 contributes to every build variant identity. `flake.lock` resolves the pinned Nix
 inputs and is validated against this lock.
-Publication inputs are also locked here: `publication_media`, the CeTZ and
+Publication inputs are also locked here: `publication_media`, the CeTZ, oxifmt,
-oxifmt archives, and the locally required Typst version in `publication_tools`.
+wavy/jogs, bytefield, rivet, blockcell, circuiteria and tidy archives, and the
 locally required Typst version in `publication_tools`. Package identities include
 both name and version; CeTZ 0.3.4/0.5.2 and oxifmt 0.2.1/1.0.0 coexist as
 separate cache entries. Library imports are checked as a complete offline closure.
 They are prepared manually by `publications/build_datasheet.py setup`, without
 adding a root Makefile target. See [Publications](../publications/README.md).
@@ -114,6 +114,62 @@
    "cluster_wdg": {"url": "https://github.com/retroSoC/wdg.git", "revision": "f5d39fa246054d678d34195824d943367dfcce44", "destination": "rtl/managed/clusterip/wdg", "license": "MulanPSL-2.0"}
  },
  "archives": {
    "typst_bytefield": {
      "package_name": "bytefield",
      "version": "0.0.8",
      "url": "https://packages.typst.org/preview/bytefield-0.0.8.tar.gz",
      "sha256": "00b81fcabf5a2601da82812ce3274597baea4831b014f790a6350948470403c6",
      "destination": ".cache/retrosoc/publications/packages/preview/bytefield/0.0.8",
      "license": "MIT"
    },
    "typst_rivet": {
      "package_name": "rivet",
      "version": "0.3.1",
      "url": "https://packages.typst.org/preview/rivet-0.3.1.tar.gz",
      "sha256": "8057237ae348189df303fbc45548c87a6cf24f5c58c19a072b1d20fa4ce3bcc8",
      "destination": ".cache/retrosoc/publications/packages/preview/rivet/0.3.1",
      "license": "Apache-2.0"
    },
    "typst_blockcell": {
      "package_name": "blockcell",
      "version": "0.1.0",
      "url": "https://packages.typst.org/preview/blockcell-0.1.0.tar.gz",
      "sha256": "cf086664a01bf6ca4b7fa84a9746589039887f4bda13fe7b7781d1cea35f3164",
      "destination": ".cache/retrosoc/publications/packages/preview/blockcell/0.1.0",
      "license": "MIT"
    },
    "typst_circuiteria": {
      "package_name": "circuiteria",
      "version": "0.2.1",
      "url": "https://packages.typst.org/preview/circuiteria-0.2.1.tar.gz",
      "sha256": "207e33352f115c00d6ee141e3d2c89691f1307c456272e0e187f5303c9892729",
      "destination": ".cache/retrosoc/publications/packages/preview/circuiteria/0.2.1",
      "license": "Apache-2.0"
    },
    "typst_cetz_0_3_4": {
      "package_name": "cetz",
      "version": "0.3.4",
      "url": "https://packages.typst.org/preview/cetz-0.3.4.tar.gz",
      "sha256": "4f4b5a8d311d519e749940a766fe50521e40c041129e1c91af0c42e61f307514",
      "destination": ".cache/retrosoc/publications/packages/preview/cetz/0.3.4",
      "license": "LGPL-3.0-or-later"
    },
    "typst_tidy": {
      "package_name": "tidy",
      "version": "0.3.0",
      "url": "https://packages.typst.org/preview/tidy-0.3.0.tar.gz",
      "sha256": "a4c75f15b2cacdeef858453cdea6ee6e665c3464ebb5097a5b1a9c309418c249",
      "destination": ".cache/retrosoc/publications/packages/preview/tidy/0.3.0",
      "license": "MIT"
    },
    "typst_oxifmt_0_2_1": {
      "package_name": "oxifmt",
      "version": "0.2.1",
      "url": "https://packages.typst.org/preview/oxifmt-0.2.1.tar.gz",
      "sha256": "16fac2923032c59727de01e84d42cac45e8790da28df56effca49f4de41b09d9",
      "destination": ".cache/retrosoc/publications/packages/preview/oxifmt/0.2.1",
      "license": "MIT-0"
    },
    "typst_wavy": {
      "version": "0.1.3",
      "url": "https://packages.typst.org/preview/wavy-0.1.3.tar.gz",
@@ -12,3 +12,8 @@ The SKY130 OpenRAM SRAM dependency uses
 [`OpenRAM-BSD-3-Clause`](OpenRAM-BSD-3-Clause) and
 [`SKY130-OpenRAM-Mixed-NOTICE`](SKY130-OpenRAM-Mixed-NOTICE). Its downloaded
 artifact also contains the exact Apache-2.0 SkyWater build-space license.
 The `Typst-*-LICENSE` files preserve the exact license texts of the newly added
 publication diagram packages and their runtime dependencies. Their versions,
 authors and archive provenance are recorded in the dependency lock and
 [attribution inventory](../ATTRIBUTIONS.md).
@@ -0,0 +1,21 @@
 MIT License
 Copyright (c) 2026 Dalei
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal
 in the Software without restriction, including without limitation the rights
 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 copies of the Software, and to permit persons to whom the Software is
 furnished to do so, subject to the following conditions:
 The above copyright notice and this permission notice shall be included in all
 copies or substantial portions of the Software.
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
@@ -0,0 +1,21 @@
 MIT License
 Copyright (c) 2023 jomaway
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal
 in the Software without restriction, including without limitation the rights
 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 copies of the Software, and to permit persons to whom the Software is
 furnished to do so, subject to the following conditions:
 The above copyright notice and this permission notice shall be included in all
 copies or substantial portions of the Software.
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
@@ -0,0 +1,165 @@
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                       Version 3, 29 June 2007
 Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
 Everyone is permitted to copy and distribute verbatim copies
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@@ -0,0 +1,73 @@
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@@ -0,0 +1,16 @@
 MIT No Attribution
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@@ -0,0 +1,73 @@
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 END OF TERMS AND CONDITIONS
 APPENDIX: How to apply the Apache License to your work.
 To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets "[]" replaced with your own identifying information. (Don't include the brackets!)  The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives.
 Copyright 2024 HEL
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 http://www.apache.org/licenses/LICENSE-2.0
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
@@ -0,0 +1,21 @@
 MIT License
 Copyright (c) 2023 Mc-Zen
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal
 in the Software without restriction, including without limitation the rights
 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 copies of the Software, and to permit persons to whom the Software is
 furnished to do so, subject to the following conditions:
 The above copyright notice and this permission notice shall be included in all
 copies or substantial portions of the Software.
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
@@ -21,6 +21,21 @@ register/bitfield and software reference chapters. Each actual IP starts on a
 new page; UART/SDIO instances share their common register descriptions.
 CPU ISA/CSR manuals remain outside this publication's scope.
 The representative drawing layer additionally uses bytefield 0.0.8, rivet 0.3.1,
 blockcell 0.1.0 and circuiteria 0.2.1. `diagram_reference.py` provides source-bound
 descriptor/protocol/instruction/storage data and circuit connections;
 `datasheets/diagram-packages.typ` adapts their visual settings. The three selected
 IP circuit figures are UART0, central DMA and APU; other IP diagrams, register
 bit layouts and waveforms keep their existing implementation.
 `package_reference.py` identifies dependencies by name/version, validates each
 cache and walks its runtime imports. CeTZ 0.3.4 and oxifmt 0.2.1 are retained for
 these packages alongside CeTZ 0.5.2 and oxifmt 1.0.0; tidy 0.3.0 is a runtime
 input of circuiteria. Waveforms retain wavy 0.1.3 and jogs 0.2.4.
 Setup uses checksum-locked archives, and build/check require the
 complete local cache. The manifest records version-qualified package digests
 and their runtime import graph. Third-party manual sources are not built.
 ### Software execution and structure baseline
 The same draft now details generic LP startup/linker initialization, conditional
@@ -185,7 +200,8 @@ uses `configs/ci/ihp130-hp.mk`; legacy selection uses `configs/cluster/mini-mpw.
 Use Python 3.10 or newer, Git and **Typst 0.15.1**. PDF checks additionally use
 `pypdf` and `pdfplumber`, available in the Codex bundled document runtime. The
-build itself uses Python's standard library and the installed Typst CLI.
+build uses Python's standard library and the installed Typst CLI; Python 3.10
 also uses the `tomli` backport already pinned in `requirements/build.txt`.
 From the repository root:
@@ -263,7 +279,8 @@ The three original SVGs are archived byte-for-byte in media and are not used as
 current architecture diagrams. Do not reintroduce copies beside the Typst files.
 [The shared dependency lock](../dependencies/dependencies.lock.json) pins media,
-CeTZ 0.5.2, oxifmt 1.0.0, wavy 0.1.3, jogs 0.2.4 and the required local Typst version.
+all eleven runtime package name/version pairs documented above, and the required
 local Typst version.
 Media's `.gitattributes` prevents platform line-ending conversion of hashed
 assets. Every file listed in media's `assets.json` is checked before building.
 Typst package extraction uses the shared safe archive helper and a file-hash
@@ -32,10 +32,13 @@ from publications.system_reference import collect_system_reference, source_paths
 from publications.retrieval_reference import collect_retrieval  # noqa: E402
 from publications.report_changes import page_ranges  # noqa: E402
 from publications.structure_reference import validate_structure  # noqa: E402
 from publications.diagram_reference import collect_diagrams  # noqa: E402
 from publications.package_reference import (  # noqa: E402
    directory_hashes, package_records, validate_imports, validate_package_closure,
 )
 CONFIG = ROOT / "publications/datasheets/mini.json"
 CACHE = ROOT / ".cache/retrosoc/publications"
 PACKAGES = ("cetz", "oxifmt", "wavy", "jogs")
 MAP = "rtl/mini/address_map/memory_map.json"
 TOPOLOGY = "rtl/mini/integration/soc_topology.json"
 PINS = "rtl/mini/pin_map/pin_map.json"
@@ -163,6 +166,7 @@ def collect_data(config: dict[str, Any], *, check_snapshot: bool = True) -> dict
        read_json(ROOT / "rtl/mini/integration/user_extensions_legacy.json"),
        config["source_revision"], system_reference["support"],
    )
    system_reference["illustrations"] = collect_diagrams(ROOT, system_reference["illustrations"], regions)
    return {
        "document": config,
        "profiles": profiles,
@@ -219,14 +223,6 @@ def gpio_label(mode: Any) -> str:
    return " / ".join(names) or "-"
 def directory_hashes(directory: Path) -> dict[str, str]:
    return {
        p.relative_to(directory).as_posix(): sha256(p)
        for p in sorted(directory.rglob("*"))
        if p.is_file() and p.name != ".manifest.json"
    }
 def prepare(lock: dict, update: bool) -> None:
    for name, dependency in lock["sources"].items():
        if name.startswith("cluster_") or name in {"hazard3", "mpw"}:
@@ -238,8 +234,8 @@ def prepare(lock: dict, update: bool) -> None:
            )
    media = lock["sources"]["publication_media"]
    ensure_git_repo(media["url"], ROOT / media["destination"], media["revision"], update=update)
-    for name in PACKAGES:
+    for package in package_records(lock):
-        package = lock["archives"][f"typst_{name}"]
+        name = package["name"]
        archive = CACHE / "downloads" / f"{name}-{package['version']}.tar.gz"
        download_file(package["url"], archive, package["sha256"], update=update)
        destination = ROOT / package["destination"]
@@ -282,15 +278,7 @@ def check_assets(lock: dict) -> dict:
        path = location / relative
        if not path.is_file() or sha256(path) != expected:
            raise ValueError(f"missing or modified media asset: {relative}")
-    for name in PACKAGES:
+    validate_package_closure(ROOT, package_records(lock))
        spec = lock["archives"][f"typst_{name}"]
        directory = ROOT / spec["destination"]
        marker = directory / ".manifest.json"
        if not marker.is_file() or read_json(marker) != {
            "archive": spec["sha256"],
            "files": directory_hashes(directory),
        }:
            raise ValueError(f"package {name} missing or modified; run setup")
    return manifest
@@ -421,7 +409,8 @@ def build(config: dict, lock: dict, executable: str, out: Path | None) -> Path:
        "media_revision": lock["sources"]["publication_media"]["revision"],
        "assets": assets,
        "typst": lock["publication_tools"]["typst"]["version"],
-        "packages": {n: lock["archives"][f"typst_{n}"]["sha256"] for n in PACKAGES},
+        "packages": {p["identity"]: p["sha256"] for p in package_records(lock)},
        "package_runtime_imports": validate_package_closure(ROOT, package_records(lock)),
        "pdf_sha256": sha256(pdf),
        "layout_regions_sha256": sha256(out / "layout-regions.json"),
        "change_markers_sha256": sha256(out / "change-markers.json"),
@@ -436,10 +425,7 @@ def build(config: dict, lock: dict, executable: str, out: Path | None) -> Path:
 def check_document_sources(config: dict, data: dict) -> None:
    sources = list((ROOT / "publications/datasheets").rglob("*.typ"))
    combined = "\n".join(p.read_text(encoding="utf-8") for p in sources)
-    permitted = {name: load_lock()["archives"][f"typst_{name}"]["version"] for name in PACKAGES}
+    validate_imports(combined, package_records(load_lock()))
    for name, version in re.findall(r"@preview/([\w-]+):([0-9.]+)", combined):
        if permitted.get(name) != version:
            raise ValueError(f"unlocked Typst import: {name}:{version}")
    if re.search(r"#lorem\(|Lorem ipsum|balba|TO BE COMPLETED", combined):
        raise ValueError("unstructured placeholder remains in Typst source")
    for entry in data["catalog"]:
@@ -0,0 +1,172 @@
 #import "style.typ": data, ink, gold, pale-gold, gray, muted, rhythm
 #import "@preview/bytefield:0.0.8" as bf
 #import "@preview/rivet:0.3.1" as rv
 #import "@preview/blockcell:0.1.0" as bc
 #import "@preview/circuiteria:0.2.1" as ce
 #import "@preview/cetz:0.3.4" as c3
 #let diagrams = data.system_reference.illustrations
 #let blue-gray = rgb("#E7EFF6")
 #let diagram-text(body) = text(font:"Inter",size:9pt,fill:ink,body)
 #let diagram-note(body) = block(above:4pt,below:0pt)[
  #set par(leading:rhythm.small-leading,spacing:rhythm.small-spacing)
  #text(size:9pt,fill:muted,body)
 ]
 #let dma-tcd-diagram() = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #show: bf.bf-config.with(row-height:24pt,field-font-size:9pt,note-font-size:9pt,
    header-font-size:9pt,stroke:0.6pt+ink)
  #let fields = ()
  #for field in diagrams.dma_tcd {
    if calc.rem(field.offset,16)==0 {
      fields.push(bf.note(left)[#("0x"+upper(str(field.offset,base:16)))])
    }
    fields.push(bf.bytes(int(field.bits/8),fill:if field.role=="reserved" {gray}
      else if field.role=="writeback" {blue-gray} else {pale-gold})[#field.name])
  }
  #bf.bytefield(bpr:128,msb:right,pre:(36pt,),post:(),
    bf.bitheader(0,[0],32,[4],64,[8],96,[12],numbers:none,angle:0deg,text-size:9pt),..fields)
  #diagram-note[Byte offsets increase left to right; four 16-byte rows form the 64-byte TCD.
    Gold: software configuration. Blue-gray: current HAL result writeback. Gray: reserved.
    Word serialization and 64-byte descriptor alignment are separate from the transfer width.]
 ]
 #let sdio-command-diagram() = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #show: bf.bf-config.with(row-height:26pt,field-font-size:9pt,note-font-size:9pt,
    header-font-size:9pt,stroke:0.6pt+ink)
  #bf.bytefield(bpr:48,msb:left,pre:(),post:(),
    bf.bitheader(47,40,8,0,angle:0deg,text-size:9pt),
    ..diagrams.sdio_command.map(f=>bf.bits(f.bits,fill:if f.bits==1 {gray} else {pale-gold})[#f.label]))
  #diagram-note[Native SD command: S = start 0; T = host transmission 1; CMD = 6-bit command index;
    ARG = 32-bit argument; CRC7 covers S through ARG; E = end 1. Bit 47 is transmitted first.]
 ]
 #let instruction-row(example:none, start:0) = {
  let ranges=(:)
  let colors=(:)
  let short=("CLASS":"CLS","OPCODE":"OP","PREDICATE":"PRED","SRC0":"S0","SRC1":"S1","IMMEDIATE":"IMM")
  for field in diagrams.apu.fields.filter(f=>f.lsb >= start and f.lsb < start + 32) {
    let span=str(field.lsb+field.bits - 1)+"-"+str(field.lsb)
    let name=short.at(field.label,default:field.label)
    if example!=none {
      let value=example.values.at(field.name)
      name=if field.name=="immediate" {"0x"+upper(str(value,base:16))} else {str(value)}
    }
    ranges.insert(span,(name:name))
    colors.insert(span,if field.name in ("instruction_class","opcode","predicate") {pale-gold} else {gray})
  }
  let schema=rv.schema.load((structures:(main:(bits:32,start:start,ranges:ranges)),colors:(main:colors)))
  rv.schema.render(schema,width:100%,config:rv.config.config(
    default-font-family:"Inter",default-font-size:20pt,italic-font-family:"Inter",italic-font-size:20pt,
    text-color:ink,link-color:ink,bit-i-color:ink,border-color:ink,background:white,
    bit-width:32,bit-height:42,margins:(4,4,4,4),all-bit-i:false,full-page:false))
 }
 #let apu-instruction-diagram() = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #diagram-text[*APUMC 64-bit instruction format*]
  #instruction-row(start:32)
  #instruction-row(start:0)
  #for example in diagrams.apu.examples {
    block(above:6pt,below:2pt)[#diagram-text[#example.title · #example.word]]
    instruction-row(example:example,start:32)
    instruction-row(example:example,start:0)
  }
  #diagram-note[CLS = instruction class; OP = opcode; PRED = predicate; DST/S0/S1 = register indexes;
    AUX = operation-specific selector; IMM = immediate. These are internal APU instructions,
    not LP/HP RISC-V extensions. Examples demonstrate encoding, not completed codec execution.]
 ]
 #let memory-window-diagram() = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #set par(leading:rhythm.small-leading,spacing:5pt)
  #for window in diagrams.windows {
    block(above:0pt,below:4pt,grid(columns:(32mm,87mm,47mm),gutter:2mm,
      bc.cell(width:100%,height:12mm,fill:pale-gold,stroke:0.6pt+ink)[#align(center+horizon)[#window.symbol]],
      bc.cell(width:100%,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[#window.base_hex … #window.end_hex]],
      bc.cell(width:100%,height:12mm,fill:white,stroke:0.6pt+ink)[#align(center+horizon)[#window.size_label]]))
  }
  #diagram-note[Selected PRODUCT memory address windows, not to scale. The reference SRAM is 32 KiB.
    FLASH is a boot alias; serial-memory apertures do not establish fitted device capacity.
    Register windows and reserved gaps remain in the complete address tables.]
 ]
 #let cache-boundary-diagram() = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #let c=diagrams.cache
  #diagram-text[Relative byte boundaries: 0 · #c.granule · #c.covered_bytes]
  #v(4pt)
  #bc.region(width:100%,fill:white,stroke:0.6pt+ink,radius:0pt)[
    #bc.cell(width:77mm,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[CBO block 0: bytes 0–63]]
    #h(2mm)
    #bc.cell(width:77mm,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[CBO block 1: bytes 64–127]]
    #linebreak()
    #v(4pt)
    #bc.cell(width:19mm,height:15mm,fill:gray,stroke:0.6pt+ink)[16 B \ before]
    #bc.cell(width:57mm,height:15mm,fill:pale-gold,stroke:0.6pt+ink)[48 B payload \ bytes 16–63]
    #h(2mm)
    #bc.cell(width:19mm,height:15mm,fill:pale-gold,stroke:0.6pt+ink)[16 B \ payload]
    #bc.cell(width:57mm,height:15mm,fill:gray,stroke:0.6pt+ink)[48 B after \ bytes 80–127]
  ]
  #diagram-note[The software-declared 64-byte maintenance granule covers a 64-byte payload at offset 16
    using two blocks. Keep boundary bytes under compatible ownership. Relative offsets are illustrative;
    this is not a verified HP cache tag/set/way layout or an allocated buffer address.]
 ]
 #let uart-fifo-diagram() = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #for (name,geometry) in diagrams.uart_fifo.pairs() {
    block(above:4pt,below:6pt)[
      *#upper(name) FIFO: #geometry.depth entries × #geometry.bits bits*
      #linebreak()
      #v(3pt)
      #bc.region(width:100%,fill:white,stroke:0.6pt+ink,radius:0pt)[
        #for index in ("0","1","2","…","63") {
          bc.cell(width:29mm,height:13mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[Entry #index]]
          h(2pt)
        }
      ]
    ]
  }
  #bc.cell(width:103mm,height:14mm,fill:pale-gold,stroke:0.6pt+ink)[#align(center+horizon)[RX entry: data bits 7:0]]
  #h(2mm)
  #bc.cell(width:61mm,height:14mm,fill:blue-gray,stroke:0.6pt+ink)[#align(center+horizon)[Error metadata bits 11:8]]
  #diagram-note[Storage slots are shown schematically; the drawing is not a live occupancy snapshot.
    TX stores eight data bits. RX stores eight data bits plus four error bits; the 32-bit APB RXDATA
    access width is a separate register interface. Pointer, flush and watermark rules remain in the UART contract.]
 ]
 #let circuit-diagram(id) = block(width:100%,breakable:false)[
  #set text(font:"Inter",size:9pt,fill:ink)
  #let circuit=diagrams.circuits.at(id)
  #ce.circuit(length:1cm,{
    for node in circuit.nodes {
      let ports=(:)
      let margins=(:)
      for side in ("west","east","north","south") {
        ports.insert(side,node.ports.filter(p=>p.side==side).map(p=>(id:p.id,name:"")))
      }
      for (side,values) in node.at("port_margins",default:(:)) {
        margins.insert(side,values.map(v=>v*1%))
      }
      ce.element.block(id:node.id,x:node.x,y:node.y,w:node.w,h:node.h,
        name:node.title.split("\n").map(diagram-text).join(linebreak()),
        ports:ports,ports-margins:margins,
        fill:if node.id in ("reg","loader") {pale-gold} else {gray},
        radius:0.06,stroke:0.6pt+ink)
    }
    for (index,edge) in circuit.edges.enumerate() {
      let src=edge.from.split(".")
      let dst=edge.to.split(".")
      ce.wire.wire("edge"+str(index),(src.first()+"-port-"+src.last(),dst.first()+"-port-"+dst.last()),
        bus:edge.kind=="data",name:none,color:ink,dashed:edge.kind=="control",directed:true,
        style:edge.style,rotate-name:false,zigzag-dir:edge.at("zigzag-dir",default:"vertical"),
        guided-sides:edge.at("guided-sides",default:("east","west")))
      c3.draw.content(("edge"+str(index)+".start",50%,"edge"+str(index)+".end"),
        box(fill:white,inset:(x:2pt,y:1pt),diagram-text(edge.label)))
    }
  })
  #diagram-note[Solid arrows: data paths. Dashed arrows: control signals. #circuit.note]
 ]
@@ -2,6 +2,7 @@
 #import "figures.typ": box, wire
 #import "@preview/cetz:0.5.2"
 #import "waveforms.typ": timing
 #import "diagram-packages.typ": circuit-diagram
 #let inline(value) = {
  let parts=value.split("`")
@@ -145,11 +146,17 @@
  }
 }
-#let ip-reference(id, family, depth, shared:none, legacy:none, register-family:none, software-note:none) = {
+#let ip-reference(id, family, depth, shared:none, legacy:none, register-family:none, software-note:none, functional-note:none, protocol-note:none) = {
  let chapter=data.chapters.at(family)
  subhead(id,"Features and Block Diagram",depth)
  list(..chapter.at("features",default:()).map(inline))
-  figure(component-diagram(family,id),caption:[#chapter.title functional organization.])
+  if id in ("uart0","dma","apu") {
    block(breakable:false)[
      #change-start("circuit-"+id,chapter.title+" internal circuit diagram")
      #figure(circuit-diagram(id),kind:image,supplement:[Figure],caption:[#chapter.title functional organization.])
      #change-end("circuit-"+id)
    ]
  } else {figure(component-diagram(family,id),caption:[#chapter.title functional organization.])}
  subhead(id,"Functional Description",depth)
  if legacy!=none {
    set heading(outlined:false,bookmarked:true)
@@ -157,8 +164,10 @@
  }
  for paragraph in chapter.notes { par(inline(paragraph)) }
  prose-sections(id+"-functional",chapter.functional,depth)
  if functional-note!=none {functional-note}
  subhead(id,"Protocol and Timing",depth)
  [For common APB4/AXI4/stream handshake rules, see @common-protocols.]
  if protocol-note!=none {protocol-note}
  if shared==none {
    timing(family,[#chapter.title example transaction or event sequence.])
    if family+"-exception" in data.waveforms {
@@ -1,6 +1,7 @@
 #import "../style.typ": *
 #import "../ip-reference.typ": ip-reference
 #import "../diagram-packages.typ": apu-instruction-diagram
 #pagebreak(weak:true)
@@ -10,7 +11,15 @@
 #ip("apu")
-#ip-reference("apu","apu",4,legacy:[
+#ip-reference("apu","apu",4,functional-note:[
  #block(breakable:false)[
    #change-start("apu-instruction-layout", "APU internal microcode format and encoding examples", category:"added")
    #figure(apu-instruction-diagram(),kind:image,supplement:[Figure],caption:[APU 64-bit internal microcode fields and source-encoded examples.])<apu-instruction-layout>
    #source-note("scripts/apu_isa.py",title:"Instruction fields and encode/decode definitions")
    #source-note("rtl/ip/multimedia/apu_microcode_pkg.sv",title:"RTL instruction slices and legal-encoding checks")
    #change-end("apu-instruction-layout")
  ]
 ],legacy:[
 The current APU RTL advertises capability word `0x000001BD` and APB version `0x00010000`. WAV/FLAC transport, job submission and stream paths are integrated; MP3 and KWS are not advertised. Delivery still requires a complete accepted microcode image and the corresponding codec corpus. The later 32 KiB/V1.1 capacity refreeze is not implemented by the current register constants.
 ])
@@ -1,6 +1,7 @@
 #import "../style.typ": *
 #import "../ip-reference.typ": ip-reference
 #import "../diagram-packages.typ": dma-tcd-diagram
 #pagebreak(weak:true)
@@ -10,12 +11,20 @@
 #ip("dma")
-#ip-reference("dma","dma",3,software-note:[
+#ip-reference("dma","dma",3,functional-note:[
-  #change-start("dma-api-link", "DMA software: command and drain completion links", category:"cross-reference")
+  #block(breakable:false)[
    #change-start("dma-tcd-layout", "Central DMA transfer-control descriptor layout", category:"added")
    #figure(dma-tcd-diagram(),kind:image,supplement:[Figure],caption:[Central DMA TCD memory layout and field ownership.])<dma-tcd-layout>
    #source-note("crt/include/retrosoc/hal/dma.h",title:"Handwritten 64-byte TCD layout")
    #source-note("crt/src/hal/dma.c",title:"Current HAL descriptor result writeback")
    #change-end("dma-tcd-layout")
  ]
 ],software-note:[
  #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
    #text(9pt)[Command submission, wait exhaustion and confirmed abort/drain: @api-completion.]
  ]
-  #change-end("dma-api-link")
+
 ],legacy:[
 ==== Architecture
 Eight channel contexts share one AXI32 master. The production integration uses 32-bit words,
@@ -1,6 +1,7 @@
 #import "../style.typ": *
 #import "../ip-reference.typ": ip-reference
 #import "../diagram-packages.typ": sdio-command-diagram
 #pagebreak(weak:true)
@@ -10,7 +11,14 @@
 #ip("sdio0")
-#ip-reference("sdio0","sdio",5,legacy:[
+#ip-reference("sdio0","sdio",5,protocol-note:[
  #block(breakable:false)[
    #change-start("sdio-command-layout", "Native SDIO command-field layout", category:"added")
    #figure(sdio-command-diagram(),kind:image,supplement:[Figure],caption:[Native SD command field order, shared by SDIO0 and SDIO1.])<sdio-command-layout>
    #source-note("rtl/ip/storage/sdio_command.sv",title:"Command assembly and most-significant-bit-first transmission")
    #change-end("sdio-command-layout")
  ]
 ],legacy:[
 SDIO0 provides native SD command/data transfers and descriptor-driven DMA through I/O gateway A.
 Its signals share the GPIO alternate-function matrix. The card, pull-ups, bus voltage and board
 timing are external integration requirements. Do not equate protocol support with a qualified
@@ -13,11 +13,11 @@
 #ip("timer")
 #ip-reference("timer","timer",4,software-note:[
-  #change-start("timer-api-link", "Timer software: delay budget and timeout-stop links", category:"cross-reference")
+
  #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
    #text(9pt)[Delay duration versus polling budget, and stop after timeout: @software-timeouts; @api-completion.]
  ]
-  #change-end("timer-api-link")
+
 ],legacy:[
 Both timers support free-running, periodic and one-shot operation, up/down counting and sticky
 interrupt status. An optional debug-freeze input stops counting while management Hazard3 is
@@ -1,6 +1,7 @@
 #import "../style.typ": *
 #import "../ip-reference.typ": ip-reference
 #import "../diagram-packages.typ": uart-fifo-diagram
 #pagebreak(weak:true)
@@ -14,12 +15,19 @@
 #ip("uart0")
-#ip-reference("uart0","uart",5,software-note:[
+#ip-reference("uart0","uart",5,functional-note:[
-  #change-start("uart-api-link", "UART0 software: timeout and completion links", category:"cross-reference")
+  #block(breakable:false)[
    #change-start("uart-fifo-layout", "UART0 transmit and receive FIFO storage", category:"added")
    #figure(uart-fifo-diagram(),kind:image,supplement:[Figure],caption:[UART0 FIFO depth and receive-entry storage.])<uart-fifo-layout>
    #source-note("rtl/ip/serial/uart_reg.sv",title:"Actual TX/RX FIFO geometry and register access")
    #change-end("uart-fifo-layout")
  ]
 ],software-note:[
  #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
    #text(9pt)[FIFO wait budgets and partial transfers: @software-timeouts; @api-completion.]
  ]
-  #change-end("uart-api-link")
+
 ],legacy:[
 UART0 supports configurable framing, fractional baud generation, watermark and receive-timeout
 interrupts, receive diagnostics, break, loopback and automatic active-low RTS/CTS. TX/RX have
@@ -2,7 +2,7 @@
 #let api = data.system_reference.software.api_reference
 === Software Timeouts and Polling Budgets <software-timeouts>
-#change-start("software-timeouts", "Software timeout units and polling budgets")
+
 The SDK defines rs_timeout_t as an unsigned #(api.timeout_bits)-bit value and currently sets
 RS_TIMEOUT_DEFAULT to #api.default_budget. These values are software budgets, not a universal
 unit of microseconds, milliseconds or CPU cycles. Their consumption depends on the function:
@@ -33,10 +33,10 @@ Do not obtain a supposedly portable deadline by treating RS_TIMEOUT_DEFAULT as o
 #source-note("crt/include/retrosoc/core/wait.h",title:"Common wait predicates and zero-budget behavior")
 #source-note("crt/src/hal/uart.c",title:"Shared UART FIFO-wait budget")
 #source-note("crt/src/hal/timer.c",title:"Separate delay duration and software polling budget")
-#change-end("software-timeouts")
+
 === API Completion and State after Failure <api-completion>
-#change-start("api-completion", "API return, completion and failure-state semantics")
+
 RS_OK describes the operation implemented by the called function. It can mean a command was
 written, FIFO entries were accepted or a completion predicate was observed. Identify that
 boundary before releasing resources, consuming output or announcing completion to another hart.
@@ -65,4 +65,3 @@ General side-effect and retry rules remain in @register-programming.
  #source("crt/src/hal/dma.c",title:"DMA implementation") ·
  #source("crt/src/hal/timer.c",title:"Timer implementation")
 ]
 #change-end("api-completion")
@@ -86,7 +86,7 @@ number is used to imply completion.
  (([2025-09-28],[0.1],[Create document],[Yuchi Miao]),
   ([2025-12-02],[0.2],[Initial draft],[Yuchi Miao]),
   ([2026-02-15],[0.3],[Initial release (historical document entry)],[Yuchi Miao]),
-   ([2026-09-06],[0.4 DRAFT],[Expand IP/system-use, retrieval and software references; add polling budgets, API completion/failure semantics and the HP bundle byte format. Retain the frozen chapter/IP structure, reviewed hardware snapshot and gray/gold layout.],[Yuchi Miao / ECOS Team])),
+   ([2026-09-06],[0.4 DRAFT],[Expand the implementation reference and add source-bound descriptor, protocol, microcode and storage diagrams using locked drawing packages. Refine three IP circuit diagrams while retaining the frozen structure and register/waveform implementations.],[Yuchi Miao / ECOS Team])),
  widths:(0.8fr,0.65fr,1.8fr,1fr),
 )
 The retained historical release entry does not establish silicon availability or qualify
@@ -1,6 +1,7 @@
 #import "../style.typ": *
 #import "../figures.typ": *
 #import "../waveforms.typ": timing
 #import "../diagram-packages.typ": memory-window-diagram
 = System Architecture
 == Introduction
@@ -99,6 +100,12 @@ The retained GA register range and SPI-SD data aperture are reserved. PRODUCT ke
 compatibility responder at the former selectable user-IP window; it does not instantiate
 MPW user IPs there. Neither case should be counted as an active accelerator.
 #block(breakable:false)[
  #change-start("memory-window-layout", "PRODUCT memory address-window diagram", category:"added")
  #figure(memory-window-diagram(),kind:image,supplement:[Figure],caption:[Selected PRODUCT memory address windows in the reference configuration.])<memory-window-layout>
  #change-end("memory-window-layout")
 ]
 #pagebreak()
 #include "memory-use.typ"
 == Clock and Reset
@@ -3,7 +3,7 @@
 #let hex(value) = code("0x"+upper(str(value,base:16)))
 === HP Boot Bundle Binary Format <boot-bundle-format>
-#change-start("boot-bundle-format", "HP boot bundle byte layout, validation and synthetic example")
+
 The supplied format is a fixed four-artifact bundle, serialized as little-endian 32-bit words.
 The format version is #bundle.version; it is independent of the datasheet's v0.4 revision.
 The bundle starts at Flash offset #hex(bundle.bundle_offset), after the LP firmware area.
@@ -84,4 +84,3 @@ filled with 0xFF; this includes the gap after LP firmware, gaps before payloads
 alignment padding. The package manifest's image SHA-256 covers that complete generated image.
 The example values are recalculated from the actual packager rather than maintained by hand.
 #source-note("tests/test_hp_boot_bundle.py",title:"Existing package layout/CRC test boundary")
 #change-end("boot-bundle-format")
@@ -1,5 +1,6 @@
 #import "../style.typ": *
 #import "../system-figures.typ": sequence-diagram
 #import "../diagram-packages.typ": cache-boundary-diagram
 == Memory Attributes, Cache and DMA Coherency <memory-coherency>
 The LP and HP cores do not form a cache-coherent SMP system. Shared memory is visible through
@@ -27,12 +28,19 @@ programming uses the command engine. Reserved ranges and inactive QPI/OPI window
 used as scratch space. Physical device capacity must match the controller and board setup.
 === Buffer ownership and alignment
-The generated HP core implements Zicbom with a 64-byte cache-maintenance block. Round shared
+#change-start("cache-maintenance-layout", "Software cache-maintenance granule and buffer boundaries")
 The supplied HP platform metadata declares Zicbom with a 64-byte cache-maintenance block. Round shared
 maintenance ranges to full blocks and prevent unrelated owners from sharing a boundary block.
 Check address-plus-length overflow before rounding. Device descriptors can impose additional
 alignment, byte-count, stride and memory-placement constraints; the DMA TCD is a separate
 64-byte descriptor contract, not a universal transfer-alignment rule for every IP.
 #figure(cache-boundary-diagram(),kind:image,supplement:[Figure],caption:[Software-declared maintenance blocks around a shared-buffer range.])<cache-maintenance-layout>
 Match the platform declaration to the generated HP artifact before deployment; this schematic
 does not independently establish physical cache-line geometry or total cache capacity.
 #source-note("app/ports/linux/linux/retrosoc_hp.dts",title:"Software-declared cache-maintenance block size")
 #change-end("cache-maintenance-layout")
 #ds-table("buffer-ownership",[Shared-buffer responsibilities],
  ([Actor],[Responsibility before handoff],[Responsibility after completion]),
  (([Cached HP producer],[Finish writes; clean required data and descriptors; order publication.],[Do not modify the submitted range while the device owns it.]),
@@ -64,11 +64,10 @@ guarantee. Use the platform's required barriers and the sequences in @memory-coh
 Neither the LP fabric nor the native crossbar admits locked transactions in the reviewed
 predicate; do not infer a global exclusive-access service from CPU ISA names alone.
 #change-start("register-api-link", "Register conventions: software completion link", category:"cross-reference")
 #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
  #text(9pt)[Software timeout budgets and API return boundaries: @software-timeouts; @api-completion.]
 ]
-#change-end("register-api-link")
+
 === RV32 access to multiword registers
 For CLINT, the SDK reads high, low and high again, accepting the result only if both high
@@ -77,7 +77,7 @@ failed release or forced stop, inspect actual reset/drain state before reusing H
 For target acceptance, capture profile/image hashes, LP load/release checkpoints, the expected
 Linux readiness event and the final simulator verdict. Do not treat UART startup alone as
 success. A complete Linux peripheral qualification requires the separate support matrix.
-#change-start("boot-source-layout", "Boot reference links: grouped layout")
+
 #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
  #set text(size:9pt)
  #set par(leading:rhythm.small-leading,spacing:rhythm.small-spacing)
@@ -86,7 +86,7 @@ success. A complete Linux peripheral qualification requires the separate support
  #source("scripts/build_hp_linux.py",title:"OpenSBI FW_JUMP and Linux artifact composition") ·
  #source("scripts/package_hp_boot.py",title:"Bundle generation and layout checks")
 ]
-#change-end("boot-source-layout")
+
 #include "image-maintenance.typ"
@@ -679,6 +679,50 @@ external margin is zero. Its bottom aligns with the first-page body boundary,
 20 mm above the sheet bottom. It must not overlap Features or move to page two.
 Do not achieve this by absolute positioning or shrinking the text.
 ### Specialized diagram packages
 Use namespaced imports through `diagram-packages.typ` for the representative
 diagram families: bytefield 0.0.8 for DMA TCD and native SD command layouts;
 rivet 0.3.1 for APU internal instruction fields/examples; blockcell 0.1.0 for
 address windows, software cache-maintenance boundaries and UART FIFO storage;
 circuiteria 0.2.1 for the UART0, central DMA and APU internal structure figures.
 All other component diagrams keep the existing CeTZ renderer. Do not route
 register descriptions through these packages: the existing bit-layout component,
 field tables and WaveDrom implementation remain separate and unchanged.
 The wrappers render every diagram as Figure, with the existing black 9 pt top
 caption and figure-directory entry, even when the package internally uses a
 native table. Keep Inter/Fira Code, gray/gold fills, final type of at least 9 pt,
 and the current body width. Numeric memory offsets, wire bit order, payload widths
 and storage capacities must be labeled independently. Address windows are not
 physical device capacities; diagrams with compressed gaps are not to scale.
 Rivet instruction words use upper/lower 32-bit rows so adjacent two-digit bit
 indexes remain readable. Coordinate and text settings are calibrated together
 against the rendered PDF; do not solve collisions by making type smaller.
 Circuiteria boxes use the shared thin-border appearance; its unmodified wire
 renderer uses 1 pt control/signal lines and 1.5 pt data buses. Dashed control and
 solid data paths are a local convention. Labels remain horizontal on white
 backing, with endpoints attached to declared ports. Other diagram line widths
 are unaffected.
 `system-reference.json.illustrations` owns reviewed field and connection records.
 `diagram_reference.py` checks source bindings, descriptor coverage, SD frame bit
 order, APU encoder/RTL slices, FIFO geometry and circuit endpoints/directions.
 The data enters the publication manifest with its sources. Encoding examples
 are generated by the existing APU tool; they are not execution or codec-pass
 evidence. Keep capability and disabled-route qualifications on the APU figure.
 The cache diagram illustrates software-declared 64-byte CBO granules and buffer
 ownership, not independently verified physical cache tag/set/way organization.
 Package identity is the pair of name and version. Rivet/circuiteria's CeTZ 0.3.4
 coexists with the existing 0.5.2; oxifmt 0.2.1 likewise coexists with 1.0.0.
 Circuiteria also requires tidy 0.3.0 at runtime. Validate the complete library
 import closure from each entrypoint, excluding standalone third-party manuals.
 Preserve package sources and licenses; prepare them only through the dependency
 lock and existing setup flow. Normal builds verify caches and never download or
 rewrite package sources.
 ### Vector diagrams and Overview
 Use the locked CeTZ implementation for engineering diagrams. Shared boxes have
@@ -0,0 +1,192 @@
 """Source-bound data for representative field, instruction, memory and circuit diagrams."""
 from __future__ import annotations
 import copy
 import importlib.util
 import re
 import sys
 from pathlib import Path
 from publications.implementation_reference import without_comments
 from publications.register_reference import number
 def dependencies(spec: dict) -> set[str]:
    paths = set(spec.get("sources", []))
    for binding in spec.get("bindings", []):
        paths.add(binding["file"])
    for circuit in spec.get("circuits", {}).values():
        for node in circuit["nodes"]:
            paths.update(node.get("sources", []))
        for edge in circuit["edges"]:
            paths.update(binding["file"] for binding in edge["bindings"])
    return paths
 def validate_bindings(root: Path, bindings: list[dict]) -> None:
    for binding in bindings:
        source = (root / binding["file"]).read_text(encoding="utf-8")
        if re.sub(r"\s+", "", without_comments(binding["text"])) not in re.sub(r"\s+", "", without_comments(source)):
            raise ValueError(f"diagram source binding changed: {binding['file']}")
 def validate_fields(fields: list[dict], total_bits: int) -> None:
    occupied, names = set(), set()
    for field in fields:
        name, lsb, bits = field["name"], field["lsb"], field["bits"]
        if name in names or type(lsb) is not int or type(bits) is not int or lsb < 0 or bits < 1:
            raise ValueError("invalid or duplicate diagram field")
        positions = set(range(lsb, lsb + bits))
        if occupied & positions or max(positions) >= total_bits:
            raise ValueError("diagram fields overlap or exceed the layout")
        names.add(name)
        occupied.update(positions)
    if occupied != set(range(total_bits)):
        raise ValueError("diagram layout has undocumented gaps")
 def dma_fields(root: Path) -> list[dict]:
    source = (root / "crt/include/retrosoc/hal/dma.h").read_text(encoding="utf-8")
    matches = re.findall(r"typedef\s+struct\s*\{([^}]+)\}\s*rs_dma_tcd_t\s*;", source)
    if len(matches) != 1:
        raise ValueError("DMA TCD structure missing or ambiguous")
    members = re.findall(r"(u?int)(16|32)_t\s+(\w+)\s*;", matches[0])
    if re.sub(r"(?:u?int)(?:16|32)_t\s+\w+\s*;", "", matches[0]).strip():
        raise ValueError("unreviewed DMA TCD member type")
    fields, offset = [], 0
    for signed, width, name in members:
        bits = int(width)
        role = "reserved" if name.startswith("reserved") else "writeback" if name in {
            "crc_result", "status", "bytes_done", "error_status"} else "configuration"
        fields.append({"name": name, "lsb": offset * 8, "bits": bits, "offset": offset,
                       "role": role, "signed": signed == "int"})
        offset += bits // 8
    validate_fields(fields, 512)
    return fields
 def apu_formats(root: Path) -> dict:
    path = root / "scripts/apu_isa.py"
    source = path.read_text(encoding="utf-8")
    declarations = re.findall(r"\(self\.(\w+),\s*(\d+),\s*(\d+)\)", source)
    aliases = {"instruction_class": "class", "opcode": "opcode", "predicate": "predicate",
               "dst": "dst", "src0": "src0", "src1": "src1", "aux": "aux", "immediate": "immediate"}
    if len(declarations) != 8 or {row[0] for row in declarations} != aliases.keys():
        raise ValueError("APU encoder field inventory changed")
    rtl = (root / "rtl/ip/multimedia/apu_microcode_pkg.sv").read_text(encoding="utf-8")
    fields = []
    for name, width, shift in declarations:
        bits, lsb = int(width), int(shift)
        slices = set(re.findall(r"s_" + aliases[name] + r"\s*=\s*instruction_i\[(\d+):(\d+)\]", rtl))
        if slices != {(str(lsb + bits - 1), str(lsb))}:
            raise ValueError("APU encoder/RTL diagram slice mismatch")
        fields.append({"name": name, "label": aliases[name].upper(), "bits": bits, "lsb": lsb})
    validate_fields(fields, 64)
    spec = importlib.util.spec_from_file_location("publication_apu_diagram_isa", path)
    if spec is None or spec.loader is None:
        raise ValueError("APU encoder could not be loaded")
    isa = importlib.util.module_from_spec(spec)
    sys.modules[spec.name] = isa
    spec.loader.exec_module(isa)
    defines = (root / "rtl/ip/multimedia/apu_define.svh").read_text(encoding="utf-8")
    for suffix, value in (("CLASS_CONTROL", int(isa.InstructionClass.CONTROL)),
                          ("CLASS_SCALAR", int(isa.InstructionClass.SCALAR)),
                          ("CONTROL_WAIT", int(isa.ControlOpcode.WAIT)),
                          ("SCALAR_MOVI", int(isa.ScalarOpcode.MOVI)),
                          ("PRED_ALWAYS", 0)):
        found = re.findall(r"^`define\s+APB4_APU__MC_" + suffix + r"\s+(\S+)", defines, re.M)
        if len(found) != 1 or number(found[0]) != value:
            raise ValueError("APU example opcode/predicate differs from RTL")
    maximum = re.findall(r"^`define\s+APB4_APU__APUMC_MAX_INSTRUCTIONS\s+(\d+)", defines, re.M)
    if maximum != [str(isa.APUMC_MAX_INSTRUCTIONS)]:
        raise ValueError("APU control-store capacity differs from the encoder")
    instructions = (
        ("SCALAR.MOVI: r1 = 0x12345678", isa.Instruction(int(isa.InstructionClass.SCALAR), int(isa.ScalarOpcode.MOVI), dst=1, immediate=0x12345678)),
        ("CONTROL.WAIT: DMA source", isa.Instruction(int(isa.InstructionClass.CONTROL), int(isa.ControlOpcode.WAIT), aux=isa.WAIT_SOURCES.index("dma"))),
    )
    examples = []
    for title, instruction in instructions:
        word = instruction.encode()
        if isa.Instruction.decode(word) != instruction:
            raise ValueError("APU instruction diagram failed round-trip encoding")
        examples.append({"title": title, "word": f"0x{word:016X}",
                         "values": {name: getattr(instruction, name) for name in aliases}})
    return {"bits": 64, "fields": fields, "examples": examples, "max_instructions": isa.APUMC_MAX_INSTRUCTIONS}
 def uart_fifo(root: Path) -> dict:
    source = (root / "rtl/ip/serial/uart_reg.sv").read_text(encoding="utf-8")
    result = {}
    for direction in ("Tx", "Rx"):
        depth = re.findall(r"parameter\s+int\s+" + direction + r"FifoDepth\s*=\s*(\d+)", source)
        fifo = re.findall(r"fifo\s*#\s*\((.*?)\)\s+u_" + direction.lower() + r"_fifo\s*\(", source, re.S)
        if len(depth) != 1 or len(fifo) != 1:
            raise ValueError("UART FIFO instance missing or ambiguous")
        # Select the final declaration before the named instance, not a preceding FIFO.
        widths = re.findall(r"\.DATA_WIDTH\s*\((\d+)\)", fifo[0])
        result[direction.lower()] = {"depth": int(depth[0]), "bits": int(widths[-1])}
    if result != {"tx": {"depth": 64, "bits": 8}, "rx": {"depth": 64, "bits": 12}}:
        raise ValueError("review UART storage diagram after FIFO geometry change")
    return result
 def validate_circuit(root: Path, circuit: dict) -> None:
    nodes, ports = {}, {}
    for node in circuit["nodes"]:
        if node["id"] in nodes:
            raise ValueError("duplicate circuit node")
        nodes[node["id"]] = node
        if not node.get("sources") or not node.get("title"):
            raise ValueError("circuit node lacks source/title")
        for port in node["ports"]:
            key = node["id"] + "." + port["id"]
            if key in ports or port["side"] not in {"north", "south", "east", "west"}:
                raise ValueError("duplicate or invalid circuit port")
            if port["direction"] not in {"in", "out"} or not isinstance(port["width"], int) or port["width"] < 1:
                raise ValueError("invalid circuit port direction/width")
            ports[key] = port
    seen = set()
    for edge in circuit["edges"]:
        src, dst = edge["from"], edge["to"]
        if src not in ports or dst not in ports or (src, dst) in seen:
            raise ValueError("missing or duplicate circuit connection")
        if ports[src]["direction"] != "out" or ports[dst]["direction"] != "in":
            raise ValueError("circuit connection direction mismatch")
        if ports[src]["width"] != ports[dst]["width"] or edge["kind"] not in {"control", "data"}:
            raise ValueError("circuit connection width/kind mismatch")
        if not edge.get("bindings") or not edge.get("label"):
            raise ValueError("circuit connection lacks source binding")
        validate_bindings(root, edge["bindings"])
        seen.add((src, dst))
 def collect_diagrams(root: Path, spec: dict, regions: list[dict]) -> dict:
    for relative in dependencies(spec):
        path = root / relative
        if Path(relative).is_absolute() or ".." in Path(relative).parts or not path.resolve().is_relative_to(root.resolve()) or not path.is_file():
            raise ValueError("missing or invalid diagram source")
    validate_bindings(root, spec["bindings"])
    if set(spec["circuits"]) != {"uart0", "dma", "apu"}:
        raise ValueError("representative circuit coverage changed")
    for circuit in spec["circuits"].values():
        validate_circuit(root, circuit)
    validate_fields(spec["sdio_command"], 48)
    command_fields = [(f["name"], f["lsb"], f["bits"]) for f in spec["sdio_command"]]
    if command_fields != [("start", 47, 1), ("direction", 46, 1), ("command", 40, 6),
                          ("argument", 8, 32), ("crc7", 1, 7), ("end", 0, 1)]:
        raise ValueError("SDIO field order differs from the bound transmitter assembly")
    dts = (root / "app/ports/linux/linux/retrosoc_hp.dts").read_text(encoding="utf-8")
    cbo = re.findall(r"riscv,cbom-block-size\s*=\s*<(\d+)>", dts)
    if cbo != ["64"]:
        raise ValueError("review cache-maintenance diagram after platform granule change")
    windows = [{k: r[k] for k in ("symbol", "base", "size", "base_hex", "end_hex", "size_label")}
               for r in regions if r["size"] > 4096 and r["route"] in {"axi4", "ram"} and r["kind"] == "active"]
    if not windows or any(r["base"] + r["size"] > 1 << 32 for r in windows):
        raise ValueError("memory diagram has an invalid address window")
    if any(int(r["base_hex"], 16) != r["base"] or int(r["end_hex"], 16) != r["base"] + r["size"] - 1 for r in windows):
        raise ValueError("memory diagram range labels disagree with numeric bounds")
    return {"sources": sorted(dependencies(spec)), "dma_tcd": dma_fields(root),
            "sdio_command": copy.deepcopy(spec["sdio_command"]), "apu": apu_formats(root),
            "uart_fifo": uart_fifo(root), "windows": sorted(windows, key=lambda r: r["base"]),
            "cache": {"granule": 64, "offset": 16, "length": 64, "end": 80, "covered_bytes": 128},
            "circuits": copy.deepcopy(spec["circuits"])}
@@ -0,0 +1,97 @@
 """Version-qualified publication packages and their offline runtime import closure."""
 from __future__ import annotations
 import json
 import re
 from pathlib import Path
 from scripts.setup_helpers import sha256
 try:
    import tomllib
 except ModuleNotFoundError:  # Python 3.10 uses the repository's pinned backport.
    import tomli as tomllib
 ARCHIVES = (
    "typst_cetz", "typst_oxifmt", "typst_wavy", "typst_jogs",
    "typst_bytefield", "typst_rivet", "typst_blockcell", "typst_circuiteria",
    "typst_cetz_0_3_4", "typst_tidy", "typst_oxifmt_0_2_1",
 )
 def package_records(lock: dict) -> list[dict]:
    records, seen = [], set()
    for archive in ARCHIVES:
        spec = lock["archives"][archive]
        name = spec.get("package_name", archive.removeprefix("typst_"))
        version = spec["version"]
        if not re.fullmatch(r"[a-z][a-z0-9-]*", name) or not re.fullmatch(r"\d+\.\d+\.\d+", version):
            raise ValueError("invalid publication package name/version")
        identity = f"{name}:{version}"
        if identity in seen:
            raise ValueError("duplicate publication package name/version")
        destination = f".cache/retrosoc/publications/packages/preview/{name}/{version}"
        if spec["destination"] != destination:
            raise ValueError("publication package cache path differs from its name/version")
        seen.add(identity)
        records.append({**spec, "name": name, "identity": identity, "archive_key": archive})
    return records
 def directory_hashes(directory: Path) -> dict[str, str]:
    return {p.relative_to(directory).as_posix(): sha256(p) for p in sorted(directory.rglob("*"))
            if p.is_file() and p.name != ".manifest.json"}
 def checked_package(root: Path, record: dict) -> Path:
    directory = root / record["destination"]
    marker = directory / ".manifest.json"
    if not marker.is_file() or json.loads(marker.read_text(encoding="utf-8")) != {
        "archive": record["sha256"], "files": directory_hashes(directory),
    }:
        raise ValueError(f"package {record['identity']} missing or modified; run setup")
    meta = tomllib.loads((directory / "typst.toml").read_text(encoding="utf-8"))["package"]
    if (meta["name"], meta["version"]) != (record["name"], record["version"]):
        raise ValueError("cached package identity does not match its locked archive")
    return directory
 def runtime_imports(directory: Path) -> set[str]:
    meta = tomllib.loads((directory / "typst.toml").read_text(encoding="utf-8"))["package"]
    pending, visited, imports = [directory / meta["entrypoint"]], set(), set()
    while pending:
        path = pending.pop().resolve()
        if path in visited:
            continue
        if not path.is_relative_to(directory.resolve()) or not path.is_file():
            raise ValueError("package runtime import is missing or escapes its package")
        visited.add(path)
        text = path.read_text(encoding="utf-8")
        # Anchoring excludes commented documentation examples. Walk only files
        # reached from the library entrypoint, never standalone manual sources.
        for ref in re.findall(r'^\s*#(?:import|include)\s+"([^"\n]+)"', text, re.M):
            if ref.startswith("@preview/"):
                imports.add(ref.removeprefix("@preview/"))
            elif ref.startswith("@"):
                raise ValueError("unreviewed package import namespace")
            else:
                pending.append(directory / ref.lstrip("/") if ref.startswith("/") else path.parent / ref)
    return imports
 def validate_imports(text: str, records: list[dict]) -> None:
    allowed = {record["identity"] for record in records}
    for name, version in re.findall(r"@preview/([\w-]+):([0-9.]+)", text):
        if f"{name}:{version}" not in allowed:
            raise ValueError(f"unlocked Typst import: {name}:{version}")
 def validate_package_closure(root: Path, records: list[dict]) -> dict[str, list[str]]:
    allowed = {record["identity"] for record in records}
    graph = {}
    for record in records:
        imports = runtime_imports(checked_package(root, record))
        if imports - allowed:
            raise ValueError(f"unlocked runtime package imports: {sorted(imports - allowed)}")
        graph[record["identity"]] = sorted(imports)
    return graph
@@ -9,6 +9,7 @@ from publications.programming_reference import collect_programming, dependencies
 from publications.implementation_reference import collect_details, dependencies as detail_dependencies
 from publications.retrieval_reference import dependencies as retrieval_dependencies
 from publications.software_reference import collect_software, dependencies as software_dependencies
 from publications.diagram_reference import dependencies as diagram_dependencies
 REFERENCE = "publications/datasheets/system-reference.json"
@@ -19,6 +20,7 @@ def source_paths(reference: dict) -> set[str]:
    paths.update(detail_dependencies(reference.get("product_details", {})))
    paths.update(retrieval_dependencies(reference.get("retrieval", {})))
    paths.update(software_dependencies(reference.get("software", {})))
    paths.update(diagram_dependencies(reference.get("illustrations", {})))
    for row in [*reference["support"], *reference["limitations"]]:
        paths.update(row["sources"])
        paths.update(row.get("tests", []))
@@ -0,0 +1,209 @@
 """Representative diagram geometry, source bindings and multi-version package integrity."""
 from __future__ import annotations
 import copy
 import json
 import os
 import shutil
 import subprocess
 from pathlib import Path
 import pytest
 from publications import diagram_reference as dr
 from publications import package_reference as pr
 from publications.build_datasheet import CONFIG, collect_data, read_json
 from scripts.dependency_lock import load_lock
 ROOT = Path(__file__).resolve().parents[1]
 SPEC = read_json(ROOT / "publications/datasheets/system-reference.json")["illustrations"]
@pytest.fixture(scope="module")
 def data():
    return collect_data(read_json(CONFIG), check_snapshot=False)
@pytest.fixture
 def source_tree(tmp_path):
    for relative in dr.dependencies(SPEC):
        target = tmp_path / relative
        target.parent.mkdir(parents=True, exist_ok=True)
        shutil.copyfile(ROOT / relative, target)
    return tmp_path
 def replace(root: Path, relative: str, old: str, new: str) -> None:
    path = root / relative
    source = path.read_text(encoding="utf-8")
    assert old in source
    path.write_text(source.replace(old, new), encoding="utf-8")
 def test_representative_inventory_uses_actual_widths_and_addresses(data):
    value = data["system_reference"]["illustrations"]
    assert sum(f["bits"] for f in value["dma_tcd"]) == 512
    assert [f["offset"] for f in value["dma_tcd"] if f["name"] == "y_count"] == [24]
    assert [f["bits"] for f in value["sdio_command"]] == [1, 1, 6, 32, 7, 1]
    assert value["apu"]["examples"][0]["word"] == "0x1101000012345678"
    assert value["apu"]["examples"][1]["word"] == "0x0800000000000000"
    assert value["uart_fifo"] == {"tx": {"depth": 64, "bits": 8}, "rx": {"depth": 64, "bits": 12}}
    assert next(row for row in value["windows"] if row["symbol"] == "SRAM")["size"] == 32768
    assert value["cache"] == {"granule": 64, "offset": 16, "length": 64, "end": 80, "covered_bytes": 128}
    assert set(value["circuits"]) == {"uart0", "dma", "apu"}
@pytest.mark.parametrize("mutation", ["gap", "overlap", "oversize", "duplicate"])
 def test_field_coverage_rejects_invalid_diagrams(mutation):
    fields = copy.deepcopy(SPEC["sdio_command"])
    if mutation == "gap":
        fields.pop()
    elif mutation == "overlap":
        fields[-1]["lsb"] = 1
    elif mutation == "oversize":
        fields[0]["bits"] = 2
    else:
        fields[-1]["name"] = fields[0]["name"]
    with pytest.raises(ValueError):
        dr.validate_fields(fields, 48)
 def test_protocol_field_order_is_checked_even_with_complete_coverage(data):
    spec = copy.deepcopy(SPEC)
    spec["sdio_command"][0], spec["sdio_command"][-1] = spec["sdio_command"][-1], spec["sdio_command"][0]
    with pytest.raises(ValueError, match="field order"):
        dr.collect_diagrams(ROOT, spec, data["regions"])
@pytest.mark.parametrize("relative,old,new", [
    ("rtl/ip/storage/sdio_command.sv", "cmd_index_i,", "other_index_i,"),
    ("rtl/ip/serial/uart_reg.sv", ".DATA_WIDTH      (12)", ".DATA_WIDTH      (16)"),
    ("rtl/ip/serial/uart_reg.sv", "TxFifoDepth    = 64", "TxFifoDepth    = 32"),
    ("scripts/apu_isa.py", "(self.dst, 4, 48)", "(self.dst, 4, 47)"),
    ("scripts/apu_isa.py", "APUMC_MAX_INSTRUCTIONS = 2048", "APUMC_MAX_INSTRUCTIONS = 4096"),
    ("app/ports/linux/linux/retrosoc_hp.dts", "riscv,cbom-block-size = <64>", "riscv,cbom-block-size = <128>"),
 ])
 def test_source_drift_requires_diagram_review(source_tree, data, relative, old, new):
    replace(source_tree, relative, old, new)
    with pytest.raises(ValueError):
        dr.collect_diagrams(source_tree, SPEC, data["regions"])
@pytest.mark.parametrize("mutation", ["node", "port", "endpoint", "direction", "width", "binding", "duplicate-edge"])
 def test_circuit_records_reject_invented_or_inconsistent_connections(mutation):
    circuit = copy.deepcopy(SPEC["circuits"]["uart0"])
    if mutation == "node":
        circuit["nodes"].append(circuit["nodes"][0])
    elif mutation == "port":
        circuit["nodes"][0]["ports"].append(circuit["nodes"][0]["ports"][0])
    elif mutation == "endpoint":
        circuit["edges"][0]["to"] = "missing.input"
    elif mutation == "direction":
        circuit["nodes"][0]["ports"][0]["direction"] = "in"
    elif mutation == "width":
        circuit["nodes"][0]["ports"][0]["width"] = 64
    elif mutation == "binding":
        circuit["edges"][0]["bindings"][0]["text"] = ".nonexistent(nonexistent)"
    else:
        circuit["edges"].append(circuit["edges"][0])
    with pytest.raises(ValueError):
        dr.validate_circuit(ROOT, circuit)
 def test_memory_window_labels_cannot_disagree_with_numeric_bounds(data):
    regions = copy.deepcopy(data["regions"])
    next(row for row in regions if row["symbol"] == "SRAM")["end_hex"] = "0xFFFFFFFF"
    with pytest.raises(ValueError, match="range labels"):
        dr.collect_diagrams(ROOT, SPEC, regions)
 def test_both_package_versions_are_locked_and_permitted():
    records = pr.package_records(load_lock())
    ids = {row["identity"] for row in records}
    assert {"cetz:0.3.4", "cetz:0.5.2", "oxifmt:0.2.1", "oxifmt:1.0.0"} <= ids
    assert len(ids) == len(records) == 11
    pr.validate_imports('#import "@preview/cetz:0.5.2"\n#import "@preview/cetz:0.3.4"', records)
    with pytest.raises(ValueError, match="unlocked"):
        pr.validate_imports('#import "@preview/cetz:0.3.3"', records)
 def test_duplicate_package_identity_is_rejected():
    lock = copy.deepcopy(load_lock())
    lock["archives"]["typst_cetz_0_3_4"] = copy.deepcopy(lock["archives"]["typst_cetz"])
    lock["archives"]["typst_cetz_0_3_4"]["package_name"] = "cetz"
    with pytest.raises(ValueError, match="duplicate"):
        pr.package_records(lock)
@pytest.fixture
 def cached_package(tmp_path):
    directory = tmp_path / "package"
    directory.mkdir()
    (directory / "typst.toml").write_text('[package]\nname="example"\nversion="1.0.0"\nentrypoint="lib.typ"\n')
    (directory / "lib.typ").write_text('#import "src/runtime.typ"\n// #import "missing.typ"\n')
    (directory / "src").mkdir()
    (directory / "src/runtime.typ").write_text('#import "/helper.typ"\n')
    (directory / "helper.typ").write_text('#import "@preview/cetz:0.3.4"\n')
    (directory / "manual.typ").write_text('#import "@preview/unneeded-manual-package:9.9.9"\n')
    record = {"name": "example", "version": "1.0.0", "identity": "example:1.0.0", "destination": "package", "sha256": "0" * 64}
    marker = directory / ".manifest.json"
    marker.write_text(json.dumps({"archive": record["sha256"], "files": pr.directory_hashes(directory)}))
    return tmp_path, directory, record
 def test_runtime_graph_excludes_manuals_and_resolves_package_root(cached_package):
    root, directory, record = cached_package
    assert pr.checked_package(root, record) == directory
    assert pr.runtime_imports(directory) == {"cetz:0.3.4"}
@pytest.mark.parametrize("mutation", ["missing-marker", "changed-file", "missing-file", "archive"])
 def test_missing_or_tampered_package_caches_are_rejected(cached_package, mutation):
    root, directory, record = cached_package
    if mutation == "missing-marker":
        (directory / ".manifest.json").unlink()
    elif mutation == "changed-file":
        (directory / "helper.typ").write_text("changed")
    elif mutation == "missing-file":
        (directory / "helper.typ").unlink()
    else:
        record["sha256"] = "1" * 64
    with pytest.raises(ValueError, match="missing or modified"):
        pr.checked_package(root, record)
 def test_offline_closure_rejects_an_unlocked_runtime_dependency(cached_package):
    root, _, record = cached_package
    with pytest.raises(ValueError, match="unlocked runtime"):
        pr.validate_package_closure(root, [record])
 def test_missing_local_runtime_import_is_rejected(cached_package):
    _, directory, _ = cached_package
    (directory / "helper.typ").unlink()
    with pytest.raises(ValueError, match="missing or escapes"):
        pr.runtime_imports(directory)
 def test_tcd_diagram_matches_actual_c_offsets(tmp_path):
    if os.name == "nt":
        pytest.skip("C layout comparison runs in the Linux host environment")
    cc = shutil.which("cc") or shutil.which("gcc")
    if cc is None:
        pytest.skip("host C compiler unavailable")
    generated = tmp_path / "retrosoc/generated"
    generated.mkdir(parents=True)
    (generated / "memory_map.h").write_text("/* No MMIO is executed. */\n")
    (generated / "user_extensions.h").write_text("/* No selectors are executed. */\n")
    fields = dr.dma_fields(ROOT)
    program = '#include <stdio.h>\n#include <stddef.h>\n#include <retrosoc/hal/dma.h>\nint main(void) {\n'
    for row in fields:
        name = row["name"]
        program += f'printf("%zu %zu\\n", offsetof(rs_dma_tcd_t,{name}), sizeof(((rs_dma_tcd_t*)0)->{name}));\n'
    program += 'return 0; }\n'
    source, exe = tmp_path / "offsets.c", tmp_path / "offsets"
    source.write_text(program)
    subprocess.run([cc, "-std=c11", "-Wall", "-Wextra", "-Werror", "-I", str(ROOT / "crt/include"),
                    "-I", str(tmp_path), str(source), "-o", str(exe)], check=True, capture_output=True, text=True)
    values = subprocess.check_output([str(exe)], text=True).splitlines()
    assert [tuple(map(int, line.split())) for line in values] == [(f["offset"], f["bits"] // 8) for f in fields]