feat: add testbenches for on-chip RAM and resource controller, enhance AXI4 and APB4 support

- Introduced  to validate AXI4 interface for 64-bit on-chip SRAM.
- Added  to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated  to include resource controller interface.
- Enhanced  to cover additional IRQ scenarios.
- Added new tests in  for AXI4 target guard timeout and isolation.
- Updated  to reflect changes in the high-performance profile.
- Modified  to verify on-chip SRAM bank configurations.
- Added  for directed verification of resource controller.
- Updated  to check SDRAM mapped window coverage.
- Enhanced  to ensure correct IRQ mappings and APB target generation.

Makefile

@@ -44,7 +44,7 @@ SRAM_SIZE_KIB            ?= $(if $(filter ICS55,$(PDK)),128,32)
 PDK_BEHAV                ?= NO
 HAVE_SVA                 ?= NO
 HAVE_HP                  ?= YES
-HP_CONFIG                ?= rv32imafdc_max
+HP_CONFIG                ?= rv32imafdc_zicbom_max
 BUILD_RELEASE            ?= NO
 JTAG_IDCODE              ?= DEADBEEF
 EXT_CLK_HZ               ?= 72000000
@@ -159,7 +159,7 @@ VALID_SYNTH_RECIPE  := balanced area speed
 VALID_STA           := NONE OPENSTA
 VALID_PDK           := ICS55 IHP130 SKY130 GF180
 VALID_BOOL          := YES NO
-VALID_HP_CONFIG     := rv32imafdc_max
+VALID_HP_CONFIG     := rv32imafdc_zicbom_max
 VALID_ISA           := RV32E RV32I RV32IM
 VALID_APP           := benchmark bringup ci_smoke coremark debug hp_boot shell xpi_flash_loader
 VALID_LINK_TYPE     := xip jtag_sram ld2_all_sram ld2_sram ld2_psram ld2_sdram