feat: add testbenches for on-chip RAM and resource controller, enhance AXI4 and APB4 support

- Introduced  to validate AXI4 interface for 64-bit on-chip SRAM.
- Added  to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated  to include resource controller interface.
- Enhanced  to cover additional IRQ scenarios.
- Added new tests in  for AXI4 target guard timeout and isolation.
- Updated  to reflect changes in the high-performance profile.
- Modified  to verify on-chip SRAM bank configurations.
- Added  for directed verification of resource controller.
- Updated  to check SDRAM mapped window coverage.
- Enhanced  to ensure correct IRQ mappings and APB target generation.

configs/benchmark/ihp130-hazard3-coremark.mk

@@ -6,7 +6,7 @@ HAVE_SRAM_IF      := YES
 HAVE_SRAM_MACRO   := YES
 SRAM_SIZE_KIB     := 32
 HAVE_HP           := YES
-HP_CONFIG         := rv32imafdc_max
+HP_CONFIG         := rv32imafdc_zicbom_max
 PDK_BEHAV         := YES
 HAVE_SVA          := NO
 EXT_CLK_HZ        := 72000000