feat: add testbenches for on-chip RAM and resource controller, enhance AXI4 and APB4 support

- Introduced  to validate AXI4 interface for 64-bit on-chip SRAM.
- Added  to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated  to include resource controller interface.
- Enhanced  to cover additional IRQ scenarios.
- Added new tests in  for AXI4 target guard timeout and isolation.
- Updated  to reflect changes in the high-performance profile.
- Modified  to verify on-chip SRAM bank configurations.
- Added  for directed verification of resource controller.
- Updated  to check SDRAM mapped window coverage.
- Enhanced  to ensure correct IRQ mappings and APB target generation.

scripts/build_hp_linux.py

@@ -142,7 +142,7 @@ def build(args: argparse.Namespace) -> None:
             f"PLATFORM_DIR={external / 'opensbi'}",
             "PLATFORM_RISCV_XLEN=32",
             "PLATFORM_RISCV_ABI=ilp32d",
-            "PLATFORM_RISCV_ISA=rv32imafdc_zicsr_zifencei",
+            "PLATFORM_RISCV_ISA=rv32imafdc_zicbom_zicsr_zifencei",
             "FW_TEXT_START=0x38000000",
             "FW_JUMP=y",
             "FW_JUMP_ADDR=0x38400000",

scripts/build_hp_smoke.py

@@ -18,7 +18,7 @@ def build(args: argparse.Namespace) -> None:
     subprocess.run(
         [
             compiler,
-            "-march=rv32imafdc_zicsr_zifencei",
+            "-march=rv32imafdc_zicbom_zicsr_zifencei",
             "-mabi=ilp32d",
             "-nostdlib",
             "-nostartfiles",

scripts/generate_vexiiriscv.py

@@ -86,7 +86,7 @@ def generate(args: argparse.Namespace) -> None:
     manifest = {
         "schema_version": 1,
         "module": GENERATED_MODULE,
-        "configuration": "rv32imafdc_max",
+        "configuration": "rv32imafdc_zicbom_max",
         "vexiiriscv_revision": actual,
         "source_status": git_status(source),
         "submodules": submodules,

scripts/regress.py

@@ -16,16 +16,25 @@ from scripts.check_c_warnings import self_owned_warnings  # noqa: E402
 
 
 CI_SMOKE_APP_VALUE = "APP=ci_smoke"
-CI_SMOKE_SIM_VALUES = (
-    CI_SMOKE_APP_VALUE,
-    "LINK_TYPE=ld2_all_sram",
+CI_SMOKE_VERILATOR_VALUES = (
     "VERILATOR_SIM_ARGS=--fast-flash",
-    "SOC_SIM_TIME=360",
     "SIMU=VERILATOR",
     "HAVE_SVA=YES",
     "firmware",
     "sim",
 )
+CI_SMOKE_SIM_VALUES = (
+    CI_SMOKE_APP_VALUE,
+    "LINK_TYPE=ld2_all_sram",
+    "SOC_SIM_TIME=360",
+    *CI_SMOKE_VERILATOR_VALUES,
+)
+CI_SMOKE_SDRAM_SIM_VALUES = (
+    CI_SMOKE_APP_VALUE,
+    "LINK_TYPE=ld2_sdram",
+    "SOC_SIM_TIME=600",
+    *CI_SMOKE_VERILATOR_VALUES,
+)
 RTL_LINT_VALUES = ("SIMU=VERILATOR", "HAVE_SVA=YES", "rtl-lint")
 RTL_LINT_OBSERVATION_VALUES = (
     "SIMU=VERILATOR",
@@ -106,7 +115,7 @@ def pdk_pr_commands(profile: str) -> tuple[tuple[str, tuple[str, ...]], ...]:
     verilator_values = (
         CI_SMOKE_SIM_VALUES
         if profile == "configs/ci/ihp130.mk"
-        else (CI_SMOKE_APP_VALUE, "SIMU=VERILATOR", "HAVE_SVA=YES", "firmware", "sim")
+        else CI_SMOKE_SDRAM_SIM_VALUES
     )
     return (
         (profile, RTL_LINT_VALUES),

scripts/run_c_tests.py

@@ -34,6 +34,7 @@ TEST_SOURCES = (
     "crt/src/hal/dma_math.c",
     "crt/src/hal/sysctrl.c",
     "crt/src/hal/clock.c",
+    "crt/src/hal/resource.c",
     "crt/src/hal/extension.c",
     "crt/src/hal/user_ip.c",
     "rtl/managed/clusterip/ps2/sw/src/ps2.c",

scripts/vexiiriscv/GenerateRetroSocHp.scala

@@ -20,7 +20,7 @@ object GenerateRetroSocHp extends App {
   param.physicalWidth = 32
   param.resetVector = 0x38000000L
   param.asidWidth = 9
-  param.addISA("m", "a", "f", "d", "c", "s", "u", "zicntr", "zihpm")
+  param.addISA("m", "a", "f", "d", "c", "s", "u", "zicbom", "zicntr", "zihpm")
   param.fixIsaParams()
 
   param.decoders = 2