feat: add testbenches for on-chip RAM and resource controller, enhance AXI4 and APB4 support

- Introduced  to validate AXI4 interface for 64-bit on-chip SRAM.
- Added  to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated  to include resource controller interface.
- Enhanced  to cover additional IRQ scenarios.
- Added new tests in  for AXI4 target guard timeout and isolation.
- Updated  to reflect changes in the high-performance profile.
- Modified  to verify on-chip SRAM bank configurations.
- Added  for directed verification of resource controller.
- Updated  to check SDRAM mapped window coverage.
- Enhanced  to ensure correct IRQ mappings and APB target generation.

tests/test_librelane_flow.py

@@ -129,8 +129,14 @@ def test_chip_config_includes_configured_onchip_sram_banks(tmp_path: Path) -> No
 
     macro = config["MACROS"]["RM_IHPSG13_1P_1024x32_c2_bm_bist"]
     assert len(macro["instances"]) == 8
-    assert "u_retrosoc.u_onchip_ram.gen_memory.gen_bank[0].u_ram.u_mem" in macro["instances"]
-    assert "u_retrosoc.u_onchip_ram.gen_memory.gen_bank[7].u_ram.u_mem" in macro["instances"]
+    assert (
+        "u_retrosoc.u_onchip_ram.gen_memory64.gen_bank[0].u_ram_lo.u_mem"
+        in macro["instances"]
+    )
+    assert (
+        "u_retrosoc.u_onchip_ram.gen_memory64.gen_bank[3].u_ram_hi.u_mem"
+        in macro["instances"]
+    )
     assert any(
         "gen_bank.*0.*\\.u_ram" in connection
         for connection in config["PDN_MACRO_CONNECTIONS"]