feat: add testbenches for on-chip RAM and resource controller, enhance AXI4 and APB4 support

- Introduced  to validate AXI4 interface for 64-bit on-chip SRAM.
- Added  to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated  to include resource controller interface.
- Enhanced  to cover additional IRQ scenarios.
- Added new tests in  for AXI4 target guard timeout and isolation.
- Updated  to reflect changes in the high-performance profile.
- Modified  to verify on-chip SRAM bank configurations.
- Added  for directed verification of resource controller.
- Updated  to check SDRAM mapped window coverage.
- Enhanced  to ensure correct IRQ mappings and APB target generation.

tests/test_script_tools.py

@@ -1162,8 +1162,9 @@ def test_pdk_pr_regressions_cover_firmware_rtl_and_selected_netlist_target() ->
             assert "VERILATOR_SIM_ARGS=--fast-flash" in verilator_values
             assert "SOC_SIM_TIME=360" in verilator_values
         else:
-            assert "LINK_TYPE=ld2_all_sram" not in verilator_values
-            assert "VERILATOR_SIM_ARGS=--fast-flash" not in verilator_values
+            assert "LINK_TYPE=ld2_sdram" in verilator_values
+            assert "VERILATOR_SIM_ARGS=--fast-flash" in verilator_values
+            assert "SOC_SIM_TIME=600" in verilator_values
         assert any("SIMU=IVERILOG" in values and "sim-asm" in values for values in command_values)
         assert any("SYNTH=YOSYS" in values and "synth" in values for values in command_values)
         assert not any(