feat: add testbenches for on-chip RAM and resource controller, enhance AXI4 and APB4 support

- Introduced  to validate AXI4 interface for 64-bit on-chip SRAM.
- Added  to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated  to include resource controller interface.
- Enhanced  to cover additional IRQ scenarios.
- Added new tests in  for AXI4 target guard timeout and isolation.
- Updated  to reflect changes in the high-performance profile.
- Modified  to verify on-chip SRAM bank configurations.
- Added  for directed verification of resource controller.
- Updated  to check SDRAM mapped window coverage.
- Enhanced  to ensure correct IRQ mappings and APB target generation.

tests/test_sdram.py

@@ -170,5 +170,6 @@ def test_ci_software_covers_sdram_mapped_window() -> None:
 
     assert "rs_ci_smoke_sdram_access" in smoke
     assert "RS_SOC_SDRAM_BASE" in smoke
+    assert "RS_SOC_SDRAM_END - RS_CI_SMOKE_SDRAM_SPAN" in smoke
     assert "RS_SOC_SDRAM_BASE" in hello
     assert "WAIT_SDRAM_READY" in hello