feat(hp): replace the OpenC906 clock-gating cells with per-PDK ICGs

Complete the integration manual chapter 3 cell swap (the ICG half; the
SRAM half landed earlier). Three new reviewed overrides, registered in
generate_openc906.py with sha256 pins on the vendored files and added to
the generated-filelist stamp prerequisites:

- gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM):
  pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/
  PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell
  (sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E
  because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with
  SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off).
- BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model
  stays byte-identical by default; the same four PDK branches substitute
  the process cell with the scan input tied off.

The GF180 branch uses a repo-owned icgtp_1 functional model in
rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent)
because the vendor functional model references a UDP latch primitive that
the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor
sdlclkp model through pdk_sky130.fl, following the existing cell pattern.
ASIC CI profiles with PDK_BEHAV unset now compile real clock gating;
PDK_BEHAV=YES profiles are bit-identical.

Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK
cell paths (Icarus adaptation); the five-mode boot testbench suite passes
on top of this change.

scripts/generate_openc906.py

@@ -18,8 +18,16 @@ for their vendored counterparts:
   integration manual chapter 3 memory swap). Each override keeps the upstream
   behavioral ``aq_f_spsram_*`` instance by default and substitutes IHP130
   ``RM_IHPSG13_1P_*`` macro combinations (depth/width stacking per manual
-  section 3.1.5) only when the build defines ``PDK_IHP130`` and
+  section 3.1.5) or exact-geometry ICS55 ``ics55_ecos_sram_*`` macros only
+  when the build defines ``PDK_IHP130``/``PDK_ICS55`` and
   ``HAVE_SRAM_MACRO`` without ``PDK_BEHAV``.
+- ``gated_clk_cell.v`` / ``tdt_gated_clk_cell.v`` / ``BUFGCE.v``: the
+  clock-gating cells (manual chapter 3 ICG swap). Each override keeps the
+  upstream default (pass-through for the two ``*_gated_clk_cell`` wrappers,
+  behavioral latch gate for ``BUFGCE``) unless a PDK define is set without
+  ``PDK_BEHAV``, in which case the process ICG cell is instantiated
+  (``sg13g2_slgcp_1`` / ``ICGX1H7R`` / ``sky130_fd_sc_hd__sdlclkp_1`` /
+  ``gf180mcu_fd_sc_mcu7t5v0__icgtp_1``).
 
 All sources are concatenated into a single compilation unit
 (``openc906_combined.v``) because gen_rtl relies on header macros being
@@ -88,6 +96,18 @@ OVERRIDES = {
         "aq_spsram_64x98.v",
         "99680fb11271eee6cfe6ff7aaa95cbdd04ef4f78d7b0e23a18c17ef064a8bedf",
     ),
+    "C906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v": (
+        "gated_clk_cell.v",
+        "22a4a5f41c7733bd4935adc8a036870a110a8e2f2a70f1f3cf64476b7a49eb9e",
+    ),
+    "C906_RTL_FACTORY/gen_rtl/tdt/rtl/common/tdt_gated_clk_cell.v": (
+        "tdt_gated_clk_cell.v",
+        "9c38f1d71a3aaa64e00d2aa7d5a43f5836080c604f245dd414a85935241d26bd",
+    ),
+    "C906_RTL_FACTORY/gen_rtl/common/rtl/BUFGCE.v": (
+        "BUFGCE.v",
+        "b0907982b81c64494756d7f62a3a35bf961f6cbf7d54241460a476dde36a333a",
+    ),
 }