feat: add management debug reset and JTAG integration for Hazard3

- Implemented  module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge.
- Created  to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure.
- Updated  and  modules to include JTAG interface signals.
- Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB.
- Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios.
- Updated SDC generation to include JTAG clock domain and port requirements.
- Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.

tests/test_clock_reset_domains.py

@@ -36,8 +36,13 @@ def test_clock_reset_domain_inventory_matches_the_rcu() -> None:
         "external",
         "system",
         "audio",
+        "jtag",
         "dvp",
     }
+    assert {
+        (crossing["name"], crossing["source"], crossing["destination"])
+        for crossing in document["crossings"]
+    } >= {("jtag_dmi", "jtag", "system")}
 
 
 def test_clock_reset_domain_inventory_rejects_unknown_domain_and_instance(tmp_path: Path) -> None: