docs: record the ICS55 SRAM macro path and its evidence

Extend the chapter 3 SRAM swap documentation to the ICS55 exact-geometry
macros: hp-platform.md describes the direct-replacement mapping and
gating next to the IHP130 stacking table, hp-rv64-validation.md records
the ICS55 boot-TB, MEM_INTF, and SoC macro-sim evidence along with the
precise remaining gaps (Yosys smoke synth needs Liberty registration for
the new macros; STA/LEC stay deferred), and the two READMEs generalize
the override wording to the PDK-selectable IHP130/ICS55 paths.

docs/hp-rv64-validation.md

@@ -123,16 +123,37 @@ qualification. Current evidence requires, at minimum:
   smoke payload (cache maintenance plus GA2D data movement, which exercises
   the BHT/ICache/DCache/JTLB RAMs for real) on the macro path with the same
   `HP_C906_BOOT_TEST_PASS` verdict as the behavioral run.
+- The wrappers also have an ICS55 macro path: under `PDK_ICS55`+
+  `HAVE_SRAM_MACRO` without `PDK_BEHAV` each wrapper directly instantiates
+  its exact-geometry `ics55_ecos_sram_<geom>_m4/m8` macro (locked
+  `openecos-projects/ics55_ecos_sram` release assets materialized by
+  `make setup-pdk`; polarity-identical ports, no stacking or padding). The
+  focused boot testbench variant
+  `test_c906_boots_smoke_payload_with_ics55_sram_macros` passes with the same
+  verdict, the vendored MEM_INTF memory suite (manual section 3.2, adapted
+  to Icarus) passes on the ICS55 path as well, and the `ics55.mk` CI profile
+  smoke simulation (`APP=ci_smoke`, Verilator) passes with the macro path
+  compiled into the SoC.
 
 `hp-linux-sim` was run with a bounded wall-clock budget this round and its
 current frontier is recorded above; the synthesis-dependent gates remain
 unrun (synthesis, netlist simulation, STA, and the physical/LEC qualification
-of the macro path). The SoC-level macro-mode simulation now has passing
+of the macro path; on Yosys the C906 ICS55 macros additionally need their
+Liberty views registered in `physical/smoke/syn/yosys/script/init_tech.tcl`,
+and the ICS55 smoke synthesis is already red without this work because
+`npu_scheduler.sv` hard-codes IHP130 `sg13g2_dlygate4sd3_1` delay cells under
+plain `SYNTHESIS`). The SoC-level macro-mode simulation now has passing
 evidence: `make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR
 hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and
 `tc_sram`) on the IHP130 macro models and passes with
 `SIM_TEST_PASS code=0` plus the `HP_LINUX_READY`/`HP_GA2D_PASS`/
-`HP_GA2D_CACHE_CLEAN` markers. All stay required evidence for qualification.
+`HP_GA2D_CACHE_CLEAN` markers. The same SoC smoke passes on the ICS55 macro
+path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, `SIM_TEST_PASS code=0` with the
+full GA2D cache-lifecycle marker sequence); the default 300 s
+`HP_SMOKE_SIM_TIME` is only enough when the run is uncontended, and the bare
+`ics55.mk` profile-default `sim` (no fast-flash) exceeds its 180 s default
+budget in this environment, so both were run with the CI-sized time budgets.
+All stay required evidence for qualification.
 
 Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT
 (scan/mbist tied off), the debug SBA AXI master (unconnected), the chapter 3

docs/ip/hp-platform.md

@@ -66,9 +66,22 @@ section 3.1.5:
 
 Depth stacks register the bank select on read transactions and mux the bank
 outputs one cycle later (manual section 3.1.4 timing); unused upper
-write-mask bits are tied off so unimplemented bits are never written. Every
+write-mask bits are tied off so unimplemented bits are never written.
-other configuration — including the committed `PDK_BEHAV=YES` CI profiles —
+
-compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically.
+With `PDK_ICS55` + `HAVE_SRAM_MACRO` and without `PDK_BEHAV`, each wrapper
+instead instantiates its exact-geometry ICS55 OpenECOS macro
+(`ics55_ecos_sram_1024x16_m8`, `_2048x32_m8`, `_256x59_m4`, `_1024x64_m8`,
+`_128x8_m8`, `_64x58_m4`, `_64x88_m4`, `_64x98_m4`), materialized by
+`make setup-pdk` from the locked `openecos-projects/ics55_ecos_sram` release
+assets (`dependencies.lock.json` `pdk_ics55_sram_<geom>` entries). The macro
+interface matches the wrapper polarity exactly (`CEB`/`GWEB`/per-bit `WEB`
+are active-low at identical widths), so the replacement is a direct
+connection with no inversion, padding, or stacking; `MARE`/`MAR` are tied
+off as in `tc_sram.sv`.
+
+Every other configuration — including the committed `PDK_BEHAV=YES` CI
+profiles — compiles the upstream behavioral `aq_f_spsram_*` instance
+byte-identically.
 Deferred this phase: low-power support
 (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI
 master (unconnected), the chapter 3 ICG (`gated_clk_cell`) replacement,

rtl/README.md

@@ -21,8 +21,9 @@ filelist and manifest below `build/<variant>/generated/openc906/`; the OpenC906
 sources are an external lint boundary. The reviewed hart-ID, sysmap
 address-attribute, and SRAM wrapper overrides live in `rtl/mini/ip_overrides/`
 (the `aq_spsram_*.v` overrides implement the integration manual chapter 3
-memory swap and select IHP130 `RM_IHPSG13_1P_*` macros only under
+memory swap and select IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55
-`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied
+`ics55_ecos_sram_*` macros only under `PDK_IHP130`/`PDK_ICS55` +
+`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied
 by filelist generation, never by editing the vendored checkout. The former
 VexiiRiscv HP generator is preserved
 only as the frozen Std-series asset (`make std-vexii-generate`). See

scripts/README.md

@@ -131,8 +131,10 @@ the vendored checkout is never modified. `generate_openc906.py` resolves the
 upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes
 the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1
 `aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, and the eight
-`aq_spsram_*.v` SRAM wrappers whose IHP130 macro path is gated on
+`aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked
-`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, each pinned to
+IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is
+gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`,
+each pinned to
 the upstream file's SHA-256 so a locked-revision move forces review), and
 emits the single compilation unit `openc906_combined.v` below `build/`;
 generated RTL is never tracked.