feat: Add support for SKY130 OpenRAM SRAM integration

- Introduced  to handle the preparation of the SKY130 OpenRAM SRAM views.
- Updated  to download and prepare the SRAM archive during PDK setup.
- Enhanced OpenSTA and Yosys configurations to accommodate SRAM macro integration.
- Added Verilog simulation models for GF180 and SKY130 SRAM macros.
- Implemented tests for SRAM setup and validation, ensuring correct integration and functionality.
- Updated various Makefiles and scripts to support SRAM size and macro configurations.

tests/test_sta_constraints.py

@@ -93,6 +93,16 @@ def test_ihp130_core_sta_loads_usb2_packet_ram_liberties() -> None:
     assert "OPENSTA_SRAM_LIBS := $(IHP130_USB2_SRAM_LIBS)" in makefile
 
 
+def test_open_pdk_core_sta_uses_matching_sram_corners() -> None:
+    makefile = PDK_TIMING_MAKEFILE.read_text(encoding="utf-8")
+    opensta = OPENSTA_MAKEFILE.read_text(encoding="utf-8")
+
+    assert "gf180mcu_fd_ip_sram__sram512x8m8wm1__ss_125C_4v50.lib" in makefile
+    assert "sky130_sram_4kbyte_1rw_32x1024_8_SS_1p4V_100C.lib" in makefile
+    assert "HAVE_SRAM_MACRO=$(HAVE_SRAM_MACRO)" in opensta
+    assert "SRAM_SIZE_KIB=$(SRAM_SIZE_KIB)" in opensta
+
+
 def test_core_sdc_rejects_pads_missing_from_the_pin_map(tmp_path: Path) -> None:
     document = json.loads(DOMAINS.read_text(encoding="utf-8"))
     document["domains"][3]["sta"]["source_port"] = "missing_pad"