feat: add System Control (SysCtrl) peripheral implementation and testbench

- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl.
- Created sysctrl_if.sv interface for communication with SysCtrl.
- Implemented sysctrl_reg.sv module to handle register read/write operations and state management.
- Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status.
- Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.

scripts/run_c_tests.py

@@ -26,6 +26,7 @@ TEST_SOURCES = (
     "crt/src/hal/uart_math.c",
     "crt/src/hal/timer_math.c",
     "crt/src/hal/psram_math.c",
+    "crt/src/hal/sysctrl.c",
     "rtl/managed/clusterip/ps2/sw/src/ps2.c",
     "rtl/managed/clusterip/ps2/sw/src/ps2_keyboard.c",
     "rtl/managed/clusterip/ps2/sw/src/ps2_mouse.c",