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feat: add System Control (SysCtrl) peripheral implementation and testbench

Browse Source 
- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl.
- Created sysctrl_if.sv interface for communication with SysCtrl.
- Implemented sysctrl_reg.sv module to handle register read/write operations and state management.
- Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status.
- Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.
This commit is contained in:
maksyuki committed 2026-08-15 21:08:59 +08:00
1 parent 24d425c3e8
commit 795559f785
31 files changed
+1441 -1025
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tests/rtl/sysctrl_fault_tb.sv → tests/rtl/sysctrl_tb.sv
+2 -2
View File
@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module sysctrl_fault_tb;
module sysctrl_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
logic fault_valid_i = 1'b0;
@@ -186,7 +186,7 @@ module sysctrl_fault_tb;
$fatal(1, "RTC wake sticky status W1C failed");
end
$display("sysctrl fault, user core control, and RTC wake test passed");
$display("SystemCtrl register, lifecycle, fault, performance, and RTC wake test passed");
$finish;
end
endmodule
tests/test_memory_map.py
+7 -51
View File
@@ -193,53 +193,6 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P
assert "bus fault responder test passed" in result.stdout
def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> None:
iverilog = shutil.which("iverilog")
vvp = shutil.which("vvp")
if iverilog is None or vvp is None:
return
generate(tmp_path)
source_list = tmp_path / "sysctrl_fault.fl"
source_list.write_text(
"\n".join(
[
"+define+SV_ASSRT_DISABLE",
f"+incdir+{tmp_path / 'rtl'}",
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
str(ROOT / "rtl/ip/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv"),
str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "sysctrl_fault_tb.v"
subprocess.run(
[
sys.executable,
str(ROOT / "rtl/mini/script/convt_sv2v.py"),
"-f",
str(source_list),
"--output",
str(converted),
],
check=True,
)
simulation = tmp_path / "sysctrl_fault_tb"
subprocess.run(
[iverilog, "-g2012", "-s", "sysctrl_fault_tb", "-o", str(simulation), str(converted)],
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
assert "sysctrl fault, user core control, and RTC wake test passed" in result.stdout
def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: Path) -> None:
iverilog = shutil.which("iverilog")
vvp = shutil.which("vvp")
@@ -267,6 +220,10 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"),
str(ROOT / "rtl/ip/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/peripheral/clint_timebase.sv"),
str(ROOT / "rtl/ip/peripheral/sysctrl_if.sv"),
str(ROOT / "rtl/ip/peripheral/sysctrl_define.svh"),
str(ROOT / "rtl/ip/peripheral/sysctrl_reg.sv"),
str(ROOT / "rtl/ip/peripheral/sysctrl_core.sv"),
str(ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv"),
str(ROOT / "rtl/tech/tc_clk.sv"),
str(ROOT / "rtl/tech/tc_pll.sv"),
@@ -339,8 +296,8 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
rtl = (ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv").read_text(encoding="utf-8")
header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8")
rtl = (ROOT / "rtl/ip/peripheral/sysctrl_core.sv").read_text(encoding="utf-8")
header = (ROOT / "crt/include/retrosoc/hal/sysctrl.h").read_text(encoding="utf-8")
for symbol in (
"SYSCTRL_I2CSEL",
@@ -351,5 +308,4 @@ def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
"s_sysctrl_qspisel",
):
assert symbol not in rtl
assert "reg_sysctrl_i2csel" not in header
assert "reg_sysctrl_qspicsel" not in header
assert "reg_sysctrl_" not in header
tests/test_script_tools.py
+4
View File
@@ -256,6 +256,10 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
assert ROOT / "rtl/mini/top/rib2apb.sv" in rib2apb.files
assert ROOT / "rtl/mini/formal/rib2apb_formal.sv" in rib2apb.files
assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in rib2apb.files
assert ROOT / "rtl/ip/peripheral/sysctrl_if.sv" in sysctrl.files
assert ROOT / "rtl/ip/peripheral/sysctrl_define.svh" in sysctrl.files
assert ROOT / "rtl/ip/peripheral/sysctrl_reg.sv" in sysctrl.files
assert ROOT / "rtl/ip/peripheral/sysctrl_core.sv" in sysctrl.files
assert ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv" in sysctrl.files
assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv" in sysctrl.files
assert ROOT / "rtl/mini/formal/sysctrl_formal.sv" in sysctrl.files
tests/test_sysctrl.py
+93
View File
@@ -0,0 +1,93 @@
"""SystemCtrl RTL regression tests."""
from __future__ import annotations
import shutil
import subprocess
import sys
from pathlib import Path
ROOT = Path(__file__).resolve().parents[1]
PERIPHERAL = ROOT / "rtl/ip/peripheral"
def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None:
iverilog = shutil.which("iverilog")
vvp = shutil.which("vvp")
if iverilog is None or vvp is None:
return
common = ROOT / "rtl/managed/clusterip/common/rtl"
generated = tmp_path / "generated"
subprocess.run(
[
sys.executable,
str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
"--map",
str(ROOT / "rtl/mini/address_map/memory_map.json"),
"--output-dir",
str(generated),
],
check=True,
)
subprocess.run(
[
sys.executable,
str(ROOT / "rtl/mini/integration/generate_user_extensions.py"),
"--map",
str(ROOT / "rtl/mini/integration/user_extensions.json"),
"--output-dir",
str(generated / "user_extensions"),
],
check=True,
)
source_list = tmp_path / "sysctrl.fl"
source_list.write_text(
"\n".join(
[
"+define+SV_ASSRT_DISABLE",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{generated / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{common}",
f"+incdir+{common / 'interface'}",
f"+incdir+{common / 'utils'}",
f"+incdir+{common / 'cdc'}",
f"+incdir+{PERIPHERAL}",
str(common / "interface/ribp_if.sv"),
str(common / "utils/register.sv"),
str(common / "cdc/cdc_sync.sv"),
str(PERIPHERAL / "pll_ctrl_if.sv"),
str(PERIPHERAL / "sysctrl_if.sv"),
str(PERIPHERAL / "sysctrl_define.svh"),
str(PERIPHERAL / "sysctrl_reg.sv"),
str(PERIPHERAL / "sysctrl_core.sv"),
str(PERIPHERAL / "ribp_sysctrl.sv"),
str(ROOT / "tests/rtl/sysctrl_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "sysctrl_tb.v"
subprocess.run(
[
sys.executable,
str(ROOT / "rtl/mini/script/convt_sv2v.py"),
"-f",
str(source_list),
"--output",
str(converted),
],
check=True,
)
simulation = tmp_path / "sysctrl_tb"
subprocess.run(
[iverilog, "-g2012", "-s", "sysctrl_tb", "-o", str(simulation), str(converted)],
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
assert "SystemCtrl register, lifecycle, fault, performance, and RTC wake test passed" in (
result.stdout
)