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https://github.com/retroSoC/retroSoC.git
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feat: refactor NMI interface and remove unused variables
- Removed CORE and IP variables from common.tcl and synth.tcl scripts. - Updated yosys.mk to exclude CORE and IP from environment variables. - Modified bus_fault_tb to enhance NMI interface with management and user NMI signals. - Added user access denial handling in bus_fault_tb. - Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface. - Adjusted test_gpio_user_mux.py to remove IP_MDD definition. - Enhanced memory map tests to include user extensions and ensure proper generation. - Updated test_script_tools.py to reflect changes in core management and user extensions. - Refined topology tests to ensure user APB target is always added. - Adjusted tech cell configuration tests to use simplified profile paths. - Improved user extensions tests for scalar bindings and slot validation.
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@@ -1,6 +1,4 @@
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SOC := MINI
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CORE := HAZARD3
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IP := NONE
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PDK := GF180
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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@@ -1,12 +0,0 @@
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SOC := MINI
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CORE := HAZARD3
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IP := MDD
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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HAVE_SRAM_MACRO := NO
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HAVE_SVA := NO
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ISA := RV32IM
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HAVE_CSR := NO
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APP := bringup
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LINK_TYPE := ld2_psram
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@@ -1,12 +0,0 @@
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SOC := MINI
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CORE := HAZARD3
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IP := NONE
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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HAVE_SRAM_MACRO := NO
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HAVE_SVA := NO
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ISA := RV32IM
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HAVE_CSR := YES
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APP := shell
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LINK_TYPE := ld2_psram
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@@ -1,12 +0,0 @@
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SOC := MINI
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CORE := HAZARD3
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IP := NONE
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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HAVE_SRAM_MACRO := NO
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HAVE_SVA := NO
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ISA := RV32IM
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HAVE_CSR := NO
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APP := bringup
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LINK_TYPE := ld2_psram
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@@ -1,6 +1,4 @@
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SOC := MINI
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CORE := HAZARD3
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IP := MDD
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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@@ -1,6 +1,4 @@
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SOC := MINI
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CORE := MDD
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IP := NONE
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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@@ -1,6 +1,4 @@
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SOC := MINI
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CORE := HAZARD3
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IP := NONE
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PDK := SKY130
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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