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feat: refactor NMI interface and remove unused variables

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- Removed CORE and IP variables from common.tcl and synth.tcl scripts.
- Updated yosys.mk to exclude CORE and IP from environment variables.
- Modified bus_fault_tb to enhance NMI interface with management and user NMI signals.
- Added user access denial handling in bus_fault_tb.
- Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface.
- Adjusted test_gpio_user_mux.py to remove IP_MDD definition.
- Enhanced memory map tests to include user extensions and ensure proper generation.
- Updated test_script_tools.py to reflect changes in core management and user extensions.
- Refined topology tests to ensure user APB target is always added.
- Adjusted tech cell configuration tests to use simplified profile paths.
- Improved user extensions tests for scalar bindings and slot validation.
This commit is contained in:
maksyuki committed 2026-07-26 09:03:33 +08:00
1 parent 3f98ad646c
commit 7a604ec86b
111 files changed
+3729 -2012
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tests/rtl/sysctrl_fault_tb.sv
+24 -2
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@@ -60,7 +60,9 @@ module sysctrl_fault_tb;
nmi.addr = '0;
nmi.wdata = '0;
nmi.wstrb = '0;
sysctrl.core_sel_i = '0;
sysctrl.user_bus_idle_i = 1'b1;
sysctrl.fault_access_i = 1'b0;
sysctrl.fault_master_i = '0;
pll_ctrl.req_ready_i = 1'b1;
pll_ctrl.rsp_active_sel_i = '0;
pll_ctrl.rsp_active_valid_i = 1'b0;
@@ -90,7 +92,27 @@ module sysctrl_fault_tb;
read_register(32'h1000_B010, read_data);
if (read_data !== 32'h0000_000A) $fatal(1, "fault W1C did not clear pending");
$display("sysctrl fault registers test passed");
read_register(32'h1000_B020, read_data);
if (read_data !== 32'h0000_003F) $fatal(1, "user cores were not held in reset");
write_register(32'h1000_B000, 32'h0000_0006);
read_register(32'h1000_B024, read_data);
if ((read_data & 32'h0000_081F) !== 32'h0000_0800) begin
$fatal(1, "out-of-range user core selection was accepted");
end
write_register(32'h1000_B024, 32'h0000_0800);
write_register(32'h1000_B000, 32'h0000_0001);
write_register(32'h1000_B020, 32'h0000_003D);
read_register(32'h1000_B024, read_data);
if ((read_data & 32'h0000_0300) !== 32'h0000_0300 || (read_data & 32'h1F) != 1) begin
$fatal(1, "user core start state was not recorded");
end
write_register(32'h1000_B020, 32'h0000_003F);
read_register(32'h1000_B024, read_data);
if ((read_data & 32'h0000_0300) !== 32'h0000_0200) begin
$fatal(1, "user core stop state was not recorded");
end
$display("sysctrl fault and user core control test passed");
$finish;
end
endmodule