feat: add support for GF180 and SKY130 PDKs with corresponding warnings and simulation files

- Introduced new JSON files for warnings generated by Icarus Verilog, Verilator, and Yosys for both GF180 and SKY130 PDKs.
- Updated the build requirements to include necessary packages for handling JSON data.
- Modified RTL filelists to use generated files for GF180 and SKY130 standard-cell models.
- Enhanced the Iverilog makefile to generate filelists dynamically based on the selected PDK.
- Implemented a Python script to generate Iverilog filelists, accommodating both GF180 and SKY130 technologies.
- Added behavioral definitions for GF180 UDPs and a tri-state buffer for netlist simulations.
- Updated Yosys synthesis scripts to handle new PDKs and ensure proper tie cell mapping.
- Extended regression scripts to support PDK-specific commands for GF180 and SKY130.
- Added tests to verify that PDK-specific regression commands cover firmware, RTL, and netlist simulations.

configs/ci/hazard3-rv32im-gf180.mk

@@ -0,0 +1,12 @@
+SOC             := MINI
+CORE            := HAZARD3
+IP              := NONE
+PDK             := GF180
+HAVE_PLL        := NO
+HAVE_SRAM_IF    := NO
+HAVE_SRAM_MACRO := NO
+HAVE_SVA        := NO
+ISA             := RV32IM
+HAVE_CSR        := NO
+APP             := bringup
+LINK_TYPE       := ld2_psram

configs/ci/hazard3-rv32im-sky130.mk

@@ -0,0 +1,12 @@
+SOC             := MINI
+CORE            := HAZARD3
+IP              := NONE
+PDK             := SKY130
+HAVE_PLL        := NO
+HAVE_SRAM_IF    := NO
+HAVE_SRAM_MACRO := NO
+HAVE_SVA        := NO
+ISA             := RV32IM
+HAVE_CSR        := NO
+APP             := bringup
+LINK_TYPE       := ld2_psram