docs: update quality workflow and enhance APU simulation tests

.github/workflows/quality.yml

@@ -73,6 +73,14 @@ jobs:
       - name: Test scripts
         run: python3 -m pytest -q
 
+      - name: Set up locked APU simulation tools
+        uses: ./.github/actions/locked-tools
+        with:
+          tools: verilator sv2v iverilog
+
+      - name: Run APU P5 simulator acceptance
+        run: python3 -m pytest -q tests/test_apu_codec_transport.py
+
       - name: Lint YAML
         run: yamllint .github .yamllint.yml
 

rtl/ip/multimedia/apu_codec_transport.sv

@@ -258,27 +258,9 @@ module apu_codec_transport (
       ({1'b0, s_logical_output_q} + {1'b0, request_source1_i} <=
        {1'b0, s_output_cursor_q});
   assign s_source_info_valid = source_info_valid(memory_data_i);
-  assign s_req_trap_detail1 = {
+  assign s_req_trap_detail1 = {request_detail_aux_i, request_opcode_i, 4'd6, request_pc_i, 8'd1};
-    request_detail_aux_i,
+  assign s_req_trap_detail5 = {request_detail_aux_i, request_opcode_i, 4'd6, request_pc_i, 8'd5};
-    request_opcode_i,
+  assign s_req_trap_detail9 = {request_detail_aux_i, request_opcode_i, 4'd6, request_pc_i, 8'd9};
-    4'd6,
-    request_pc_i,
-    8'd1
-  };
-  assign s_req_trap_detail5 = {
-    request_detail_aux_i,
-    request_opcode_i,
-    4'd6,
-    request_pc_i,
-    8'd5
-  };
-  assign s_req_trap_detail9 = {
-    request_detail_aux_i,
-    request_opcode_i,
-    4'd6,
-    request_pc_i,
-    8'd9
-  };
   assign s_active_trap_detail5 = {1'b0, s_req_aux_q, s_opcode_q, 4'd6, s_pc_q, 8'd5};
   assign s_active_trap_detail9 = {1'b0, s_req_aux_q, s_opcode_q, 4'd6, s_pc_q, 8'd9};
   assign s_output_channels = (s_descriptor_q[0][9:8] == 2'd1) ? 2'd2 :

rtl/mini/formal/apu_codec_formal.sv

@@ -5,7 +5,7 @@ module apu_codec_formal_design (
     input  logic        clk_i,
     output logic        rst_n_i,
     output logic        f_past_valid,
-    output logic [2:0]  scenario,
+    output logic [ 2:0] scenario,
     output logic [ 5:0] cycle,
     output logic        block_new,
     output logic        context_ready,
@@ -18,11 +18,11 @@ module apu_codec_formal_design (
     output logic        memory_claim,
     output logic        memory_request,
     output logic        fault_valid,
-    output logic [5:0]  fault_code,
+    output logic [ 5:0] fault_code,
-    output logic [3:0]  fault_stage,
+    output logic [ 3:0] fault_stage,
     output logic [31:0] fault_detail
 );
-  (* anyconst *)logic   [2:0]  f_scenario;
+  (* anyconst *)logic [   2:0] f_scenario;
   logic [   5:0] s_cycle_q;
   logic [1023:0] s_descriptor;
 

rtl/mini/formal/apu_codec_formal_props.sv

@@ -10,8 +10,8 @@ module apu_codec_formal;
   wire dma_request_valid, dma_request_ready, memory_claim, memory_request;
   wire [31:0] dma_request_addr, dma_request_bytes;
   wire        fault_valid;
-  wire [5:0] fault_code;
+  wire [ 5:0] fault_code;
-  wire [3:0] fault_stage;
+  wire [ 3:0] fault_stage;
   wire [31:0] fault_detail;
 
   apu_codec_formal_design u_design (.*);
@@ -49,7 +49,6 @@ module apu_codec_formal;
     cover (rst_n_i && dma_request_valid && !block_new && (cycle >= 6'd22));
     cover (rst_n_i && block_new && request_valid && !request_ready);
     cover (rst_n_i && (scenario == 3'd1) && fault_valid && (fault_detail[7:0] == 8'd5));
-    cover (rst_n_i && (scenario == 3'd2) && fault_valid &&
+    cover (rst_n_i && (scenario == 3'd2) && fault_valid && (fault_detail[15:0] == 16'h0051));
-           (fault_detail[15:0] == 16'h0051));
   end
 endmodule

tests/rtl/apu_p5_transport_tb.sv

@@ -26,7 +26,7 @@ module apu_p5_transport_tb;
   logic dma_done, dma_error;
   logic dma_error_q, dma_write_burst_done_q, dma_write_active_q, dma_fault_after_prefix_q;
   logic [31:0] dma_write_burst_bytes_q;
-  logic [6:0] dma_write_beat_q;
+  logic [ 6:0] dma_write_beat_q;
   logic        tx_ready_q;
   logic fault_valid, event_input, event_output, tx_active, input_pending, output_pending;
   logic [5:0] fault_code;

tests/rtl/axi4_target_guard_tb.sv

@@ -74,8 +74,8 @@ module axi4_target_guard_tb;
     end
   endtask
 
-  task automatic return_read_beat(input logic [5:0] id, input logic last,
+  task automatic return_read_beat(input logic [5:0] id, input logic last, input logic expected_last,
-                                  input logic expected_last, input logic [1:0] expected_resp);
+                                  input logic [1:0] expected_resp);
     begin
       @(negedge clk_i);
       sink.rid    = id;

tests/test_apu_codec_transport.py

@@ -9,6 +9,8 @@ from pathlib import Path
 import shutil
 import subprocess
 
+import pytest
+
 
 ROOT = Path(__file__).resolve().parents[1]
 sys.path.insert(0, str(ROOT / "scripts"))
@@ -88,7 +90,7 @@ def test_p5_production_transport_matches_icarus_and_verilator(tmp_path: Path) ->
     sv2v = shutil.which("sv2v")
     verilator = shutil.which("verilator")
     if None in (iverilog, vvp, sv2v, verilator):
-        raise RuntimeError("P5 requires Icarus, vvp, sv2v, and Verilator")
+        pytest.skip("P5 requires Icarus, vvp, sv2v, and Verilator")
     common = ROOT / "rtl/managed/clusterip/common/rtl"
     multimedia = ROOT / "rtl/ip/multimedia"
     filelist = tmp_path / "apu_p5_transport.fl"
@@ -161,7 +163,7 @@ def test_p5_direct_wav_uses_product_loader_dma_sequencer_and_tx(tmp_path: Path)
     sv2v = shutil.which("sv2v")
     verilator = shutil.which("verilator")
     if None in (iverilog, vvp, sv2v, verilator):
-        raise RuntimeError("P5 integration requires Icarus, vvp, sv2v, and Verilator")
+        pytest.skip("P5 integration requires Icarus, vvp, sv2v, and Verilator")
     multimedia = ROOT / "rtl/ip/multimedia"
     common = ROOT / "rtl/managed/clusterip/common/rtl"
     assembly = assemble(

tests/test_script_tools.py

@@ -1434,6 +1434,13 @@ def test_nightly_workflow_splits_netsim_from_extended_recipes() -> None:
     assert "--suite nightly-extra --pdk IHP130 --behavioral-only --dry-run" in quality
 
 
+def test_quality_runs_p5_with_locked_open_source_simulators() -> None:
+    quality = (ROOT / ".github/workflows/quality.yml").read_text()
+
+    assert "tools: verilator sv2v iverilog" in quality
+    assert "python3 -m pytest -q tests/test_apu_codec_transport.py" in quality
+
+
 def test_regression_observations_do_not_block_or_skip_metrics(
     monkeypatch, tmp_path: Path, capsys
 ) -> None: