mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: add I2C support to the SoC topology and formal verification
- Updated to include I2C1 in IRQ bindings. - Modified to increase IRQ group width and add I2C1 interrupt. - Enhanced to include I2C formal properties and adjust timeouts. - Added I2C-related source files to the formal verification flow. - Updated DMA wrapper in to handle I2C DMA signals. - Created a new testbench for I2C functionality verification. - Implemented I2C helper functions in for testing. - Added I2C tests in to validate controller behavior and recovery. - Updated existing tests to accommodate changes in DMA and IRQ handling.
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48 files changed
+3862
-1030
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@@ -7,7 +7,7 @@ module dma_error_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [ 2:0] mode_i = 3'd0;
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logic [ 3:0] mode_i = 4'd0;
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logic [31:0] srcaddr_i = 32'h3800_1000;
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logic srcincr_i = 1'b1;
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logic [31:0] dstaddr_i = 32'h4000_1000;
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@@ -145,6 +145,10 @@ module dma_error_tb;
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hw_trg.qspi_rx_proc = 1'b0;
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hw_trg.uart_tx_proc = 1'b0;
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hw_trg.uart_rx_proc = 1'b0;
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hw_trg.i2c0_tx_proc = 1'b0;
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hw_trg.i2c0_rx_proc = 1'b0;
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hw_trg.i2c1_tx_proc = 1'b0;
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hw_trg.i2c1_rx_proc = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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@@ -0,0 +1,314 @@
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`timescale 1ns / 1ps
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`include "ribp_i2c_define.svh"
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module i2c_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic dma_tx_stall;
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logic dma_rx_stall;
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logic slave_scl_low = 1'b0;
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logic slave_sda_low = 1'b0;
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logic scl_line;
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logic sda_line;
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ribp_if ribp ();
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i2c_if i2c ();
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always #5 clk_i = ~clk_i;
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assign scl_line = (i2c.scl_oe_o || slave_scl_low) ? 1'b0 : 1'b1;
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assign sda_line = (i2c.sda_oe_o || slave_sda_low) ? 1'b0 : 1'b1;
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assign i2c.scl_i = scl_line;
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assign i2c.sda_i = sda_line;
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ribp_i2c u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(dma_tx_stall),
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.dma_rx_stall_o(dma_rx_stall),
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.ribp (ribp),
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.i2c (i2c)
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);
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task automatic ribp_write(input logic [31:0] address, input logic [31:0] data,
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input logic expected_error);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = data;
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ribp.wstrb = 4'hF;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "I2C write %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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@(negedge clk_i);
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ribp.valid = 1'b0;
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ribp.wstrb = '0;
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end
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endtask
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task automatic ribp_read(input logic [31:0] address, input logic expected_error,
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output logic [31:0] data);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "I2C read %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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data = ribp.rdata;
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@(negedge clk_i);
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ribp.valid = 1'b0;
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end
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endtask
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task automatic wait_start;
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begin
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@(negedge sda_line);
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while (!scl_line) begin
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@(negedge sda_line);
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end
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end
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endtask
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task automatic receive_byte(output logic [7:0] data, input integer stretch_cycles);
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integer bit_index;
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begin
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for (bit_index = 7; bit_index >= 0; bit_index = bit_index - 1) begin
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@(posedge scl_line);
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data[bit_index] = sda_line;
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end
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@(negedge scl_line);
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slave_sda_low = 1'b1;
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if (stretch_cycles != 0) begin
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slave_scl_low = 1'b1;
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repeat (stretch_cycles) @(posedge clk_i);
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slave_scl_low = 1'b0;
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end
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@(posedge scl_line);
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@(negedge scl_line);
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slave_sda_low = 1'b0;
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end
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endtask
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task automatic send_byte(input logic [7:0] data, output logic nack);
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integer bit_index;
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begin
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for (bit_index = 7; bit_index >= 0; bit_index = bit_index - 1) begin
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slave_sda_low = !data[bit_index];
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@(posedge scl_line);
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@(negedge scl_line);
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end
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slave_sda_low = 1'b0;
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@(posedge scl_line);
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nack = sda_line;
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@(negedge scl_line);
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end
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endtask
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task automatic wait_done;
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logic [31:0] value;
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logic [31:0] error_value;
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logic [31:0] status_value;
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integer attempts;
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begin
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value = '0;
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for (attempts = 0; attempts < 4000; attempts = attempts + 1) begin
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ribp_read(`RIBP_I2C_INTR_STATE, 1'b0, value);
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if (value[`I2C_INTR_DONE]) begin
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attempts = 4000;
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end
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end
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if (!value[`I2C_INTR_DONE]) begin
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ribp_read(`RIBP_I2C_ERROR_STATUS, 1'b0, error_value);
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ribp_read(`RIBP_I2C_STATUS, 1'b0, status_value);
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$fatal(1, "I2C transaction did not complete: error=%h status=%h fsm=%0d", error_value,
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status_value, u_dut.u_i2c_core.s_fsm_q);
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end
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ribp_write(`RIBP_I2C_INTR_STATE, 32'hFF, 1'b0);
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end
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endtask
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task automatic clear_state;
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begin
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ribp_write(`RIBP_I2C_ERROR_STATUS, 32'h7FF, 1'b0);
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ribp_write(`RIBP_I2C_INTR_STATE, 32'hFF, 1'b0);
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ribp_write(`RIBP_I2C_COMMAND, 32'hC, 1'b0);
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end
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endtask
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initial begin
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logic [31:0] value;
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logic [ 7:0] byte_value;
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logic nack;
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integer pulse_count;
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ribp.valid = 1'b0;
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ribp.addr = '0;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (4) @(posedge clk_i);
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ribp_read(`RIBP_I2C_IP_VERSION, 1'b0, value);
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if (value != 32'h0002_0000) $fatal(1, "I2C version mismatch");
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ribp_read(`RIBP_I2C_CAPABILITY, 1'b0, value);
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if (value != 32'h007F_1010) $fatal(1, "I2C capability mismatch: %h", value);
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ribp_read(32'h2, 1'b1, value);
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ribp_write(`RIBP_I2C_SCL_TIMING, 32'h0008_0008, 1'b0);
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ribp_write(`RIBP_I2C_START_TIMING, 32'h0002_0002, 1'b0);
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ribp_write(`RIBP_I2C_DATA_TIMING, 32'h0001_0000, 1'b0);
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ribp_write(`RIBP_I2C_STOP_TIMING, 32'h0002_0002, 1'b0);
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ribp_write(`RIBP_I2C_FILTER, 0, 1'b0);
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ribp_write(`RIBP_I2C_STRETCH_TIMEOUT, 200, 1'b0);
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ribp_write(`RIBP_I2C_BUS_IDLE_TIMEOUT, 200, 1'b0);
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ribp_write(`RIBP_I2C_COMMAND_TIMEOUT, 2000, 1'b0);
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ribp_write(`RIBP_I2C_TARGET_ADDR, 7'h50, 1'b0);
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ribp_write(`RIBP_I2C_CTRL, 1, 1'b0);
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fork
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begin
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA0) $fatal(1, "write address mismatch: %h", byte_value);
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA5) $fatal(1, "write data mismatch: %h", byte_value);
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end
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begin
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ribp_write(`RIBP_I2C_DATA_CMD, 32'h4A5, 1'b0);
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wait_done();
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end
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join
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clear_state();
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ribp_write(`RIBP_I2C_TARGET_ADDR, 32'h0000_06AA, 1'b0);
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fork
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begin
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hF4) $fatal(1, "10-bit write header mismatch: %h", byte_value);
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receive_byte(byte_value, 0);
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if (byte_value != 8'hAA) $fatal(1, "10-bit low address mismatch: %h", byte_value);
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hF5) $fatal(1, "10-bit read header mismatch: %h", byte_value);
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send_byte(8'hC3, nack);
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if (!nack) $fatal(1, "final 10-bit read byte was not NACKed");
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end
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begin
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ribp_write(`RIBP_I2C_DATA_CMD, 32'hD00, 1'b0);
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wait_done();
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ribp_read(`RIBP_I2C_RXDATA, 1'b0, value);
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if (value[7:0] != 8'hC3) $fatal(1, "10-bit read data mismatch: %h", value);
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end
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join
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clear_state();
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ribp_write(`RIBP_I2C_TARGET_ADDR, 7'h50, 1'b0);
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fork
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begin
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA0) $fatal(1, "combined write address mismatch");
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receive_byte(byte_value, 0);
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if (byte_value != 8'h12) $fatal(1, "combined register byte mismatch");
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA1) $fatal(1, "combined read address mismatch");
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send_byte(8'h5A, nack);
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if (!nack) $fatal(1, "final read byte was not NACKed");
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end
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begin
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ribp_write(`RIBP_I2C_DATA_CMD, 32'h012, 1'b0);
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ribp_write(`RIBP_I2C_DATA_CMD, 32'hF00, 1'b0);
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wait_done();
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ribp_read(`RIBP_I2C_RXDATA, 1'b0, value);
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if (value[7:0] != 8'h5A) $fatal(1, "read data mismatch: %h", value);
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end
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join
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clear_state();
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fork
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begin
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wait_start();
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receive_byte(byte_value, 12);
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receive_byte(byte_value, 0);
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end
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begin
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ribp_write(`RIBP_I2C_DATA_CMD, 32'h45C, 1'b0);
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wait_done();
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end
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join
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clear_state();
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ribp_write(`RIBP_I2C_TARGET_ADDR, 7'h51, 1'b0);
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ribp_write(`RIBP_I2C_DATA_CMD, 32'h455, 1'b0);
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repeat (300) @(posedge clk_i);
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ribp_read(`RIBP_I2C_ERROR_STATUS, 1'b0, value);
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if (!value[`I2C_ERROR_ADDR_NACK]) $fatal(1, "address NACK was not reported");
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clear_state();
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ribp_write(`RIBP_I2C_TARGET_ADDR, 7'h7F, 1'b0);
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fork
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begin
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wait_start();
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@(negedge scl_line);
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#1 slave_sda_low = 1'b1;
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@(posedge scl_line);
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repeat (4) @(posedge clk_i);
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slave_sda_low = 1'b0;
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end
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begin
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ribp_write(`RIBP_I2C_DATA_CMD, 32'h400, 1'b0);
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end
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join
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repeat (20) @(posedge clk_i);
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ribp_read(`RIBP_I2C_ERROR_STATUS, 1'b0, value);
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if (!value[`I2C_ERROR_ARB_LOST]) $fatal(1, "arbitration loss was not reported");
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clear_state();
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slave_sda_low = 1'b1;
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fork
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begin
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pulse_count = 0;
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while (pulse_count < 9) begin
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@(posedge scl_line);
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pulse_count = pulse_count + 1;
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end
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slave_sda_low = 1'b0;
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end
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begin
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ribp_write(`RIBP_I2C_COMMAND, 32'h2, 1'b0);
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end
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join
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repeat (80) @(posedge clk_i);
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ribp_read(`RIBP_I2C_INTR_STATE, 1'b0, value);
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if (!value[`I2C_INTR_RECOVERY_DONE] || (pulse_count != 9)) begin
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$fatal(1, "bus recovery failed: intr=%h pulses=%0d", value, pulse_count);
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end
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if (i2c.scl_o !== 1'b0 || i2c.sda_o !== 1'b0) begin
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$fatal(1, "I2C pads are not open-drain constants");
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end
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$display("I2C V2 transfer, error, stretch, arbitration, and recovery test passed");
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$finish;
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end
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initial begin
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repeat (50000) @(posedge clk_i);
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$fatal(1, "I2C test timeout");
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end
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endmodule
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@@ -127,7 +127,7 @@ module ws2812_dma_tb;
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dma_core u_dma_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.mode_i (3'd0),
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.mode_i (4'd0),
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.srcaddr_i (SOURCE_BASE + 32'd4),
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.srcincr_i (1'b1),
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.dstaddr_i (WS2812_TXDATA),
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@@ -219,6 +219,10 @@ module ws2812_dma_tb;
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hw_trg.qspi_rx_proc = 1'b0;
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hw_trg.uart_tx_proc = 1'b0;
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hw_trg.uart_rx_proc = 1'b0;
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hw_trg.i2c0_tx_proc = 1'b0;
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hw_trg.i2c0_rx_proc = 1'b0;
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hw_trg.i2c1_tx_proc = 1'b0;
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hw_trg.i2c1_rx_proc = 1'b0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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