refactor: refactor parameter naming conventions and update RTL style

- Changed parameter names in various modules from uppercase to camel case for consistency.
- Updated local parameters in testbenches to follow the same naming convention.
- Modified the RTL style manifest to include additional prefixes for better organization.
- Enhanced the check_format and check_rtl_style scripts to improve file tracking and naming validation.
- Added new tests to ensure compliance with the updated naming conventions and allowed local parameters in specific contexts.

tests/rtl/axi4_interconnect_tb.sv

@@ -4,8 +4,8 @@
 `include "rib_defs.svh"
 
 module axi4_interconnect_tb;
-  localparam int NUM_MASTERS = 3;
-  localparam int NUM_TARGETS = 9;
+  localparam int NumMasters = 3;
+  localparam int NumTargets = 9;
 
   logic        clk_i = 1'b0;
   logic        rst_n_i = 1'b0;
@@ -23,7 +23,7 @@ module axi4_interconnect_tb;
       .DATA_WIDTH(32),
       .ID_WIDTH  (1),
       .USER_WIDTH(1)
-  ) masters[NUM_MASTERS] (
+  ) masters[NumMasters] (
       .aclk   (clk_i),
       .aresetn(rst_n_i)
   );
@@ -33,7 +33,7 @@ module axi4_interconnect_tb;
       .DATA_WIDTH(32),
       .ID_WIDTH  (1),
       .USER_WIDTH(1)
-  ) targets[NUM_TARGETS] (
+  ) targets[NumTargets] (
       .aclk   (clk_i),
       .aresetn(rst_n_i)
   );
@@ -41,8 +41,8 @@ module axi4_interconnect_tb;
   always #5 clk_i = ~clk_i;
 
   axi4_interconnect #(
-      .NUM_MASTERS(NUM_MASTERS),
-      .NUM_TARGETS(NUM_TARGETS)
+      .NumMasters(NumMasters),
+      .NumTargets(NumTargets)
   ) u_dut (
       .clk_i            (clk_i),
       .rst_n_i          (rst_n_i),
@@ -69,12 +69,12 @@ module axi4_interconnect_tb;
       .perf_flash_wait_o()
   );
 
-  for (genvar target = 0; target < NUM_TARGETS; target++) begin : GEN_TARGETS
-    localparam logic [1:0] RESPONSE =
+  for (genvar target = 0; target < NumTargets; target++) begin : GEN_TARGETS
+    localparam logic [1:0] Response =
         (target == 7) ? `AXI4_RESP_DECODE_ERROR :
         (target == 8) ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY;
     axi4_error_slave #(
-        .RESPONSE(RESPONSE)
+        .Response(Response)
     ) u_target (
         .clk_i  (clk_i),
         .rst_n_i(rst_n_i),

tests/rtl/clint_tb.sv

@@ -9,7 +9,7 @@ module clint_tb;
   logic   [31:0] value;
   integer        timebase_tick_count = 0;
   ribp_if ribp ();
-  clint_if #(.HART_NUM(2)) clint ();
+  clint_if #(.HartNum(2)) clint ();
 
   always #5 clk_i = ~clk_i;
   always #2 ref_clk_i = ~ref_clk_i;
@@ -19,8 +19,8 @@ module clint_tb;
   end
 
   clint_timebase #(
-      .REF_CLK_HZ (4),
-      .TIMEBASE_HZ(1)
+      .RefClkHz  (4),
+      .TimebaseHz(1)
   ) u_timebase (
       .ref_clk_i  (ref_clk_i),
       .ref_rst_n_i(rst_n_i),
@@ -30,7 +30,7 @@ module clint_tb;
   );
 
   ribp_clint #(
-      .HART_NUM(2)
+      .HartNum(2)
   ) u_dut (
       .clk_i,
       .rst_n_i,

tests/rtl/gpio_tb.sv

@@ -3,26 +3,26 @@
 `include "gpio_define.svh"
 
 module gpio_tb;
-  localparam int PIN_NUM = 4;
+  localparam int PinNum = 4;
   localparam logic [31:0] USER_BASE = 32'h1000_0000;
   localparam logic [31:0] ADMIN_BASE = 32'h1001_4000;
 
   logic clk_i = 1'b0;
   logic rst_n_i = 1'b0;
   ribp_if ribp ();
-  gpio_if #(PIN_NUM) gpio ();
-  user_gpio_if #(PIN_NUM) user_gpio ();
+  gpio_if #(PinNum) gpio ();
+  user_gpio_if #(PinNum) user_gpio ();
   logic [31:0] read_data;
 
   always #5 clk_i = ~clk_i;
 
   ribp_gpio #(
-      .PIN_NUM        (PIN_NUM),
-      .USER_BASE_ADDR (USER_BASE),
-      .ADMIN_BASE_ADDR(ADMIN_BASE),
-      .HAS_INPUT_CMOS (1'b1),
-      .HAS_PULL_UP    (1'b1),
-      .HAS_PULL_DOWN  (1'b1)
+      .PinNum       (PinNum),
+      .UserBaseAddr (USER_BASE),
+      .AdminBaseAddr(ADMIN_BASE),
+      .HasInputCmos (1'b1),
+      .HasPullUp    (1'b1),
+      .HasPullDown  (1'b1)
   ) dut (
       .clk_i    (clk_i),
       .rst_n_i  (rst_n_i),

tests/rtl/ws2812_dma_tb.sv

@@ -178,7 +178,7 @@ module ws2812_dma_tb;
   );
 
   ribp_ws2812 #(
-      .TX_FIFO_DEPTH(4)
+      .TxFifoDepth(4)
   ) u_ws2812 (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),

tests/rtl/ws2812_tb.sv

@@ -35,7 +35,7 @@ module ws2812_tb;
   end
 
   ribp_ws2812 #(
-      .TX_FIFO_DEPTH(FIFO_DEPTH)
+      .TxFifoDepth(FIFO_DEPTH)
   ) u_dut (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),

tests/test_rtl_style.py

@@ -130,3 +130,32 @@ def test_owned_style_accepts_project_naming_contract(tmp_path: Path) -> None:
         enforce_naming=True,
     )
     assert result.returncode == 0, result.stderr
+
+
+def test_owned_style_allows_protocol_localparams(tmp_path: Path) -> None:
+    result = run_style(
+        tmp_path,
+        "module test_module #(parameter int DataWidth = 32) ("
+        "input logic clk_i, output logic data_o);\n"
+        "  localparam logic [1:0] FSM_IDLE = 2'd0;\n"
+        "  localparam logic [1:0] FSM_RESP = 2'd1;\n"
+        "  assign data_o = clk_i;\n"
+        "endmodule\n",
+        enforce_naming=True,
+    )
+    assert result.returncode == 0, result.stderr
+
+
+def test_owned_style_allows_interface_members_and_include_guards(tmp_path: Path) -> None:
+    result = run_style(
+        tmp_path,
+        "`ifndef GPIO_DEFINE_SVH\n"
+        "`define GPIO_DEFINE_SVH\n"
+        "interface test_if ();\n"
+        "  logic cmd_valid;\n"
+        "  modport dut(input cmd_valid);\n"
+        "endinterface\n"
+        "`endif\n",
+        enforce_naming=True,
+    )
+    assert result.returncode == 0, result.stderr

tests/test_user_extensions.py

@@ -52,8 +52,8 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
     assert core.count("rib_if u_user_") == 6
     assert core.count("ribp_if u_user_") == 6
     assert core.count("ribp2rib #(") == 6
-    assert core.count(".SYNC_RESET(1'b1)") == 3
-    assert core.count(".SYNC_RESET(1'b0)") == 3
+    assert core.count(".SyncReset(1'b1)") == 3
+    assert core.count(".SyncReset(1'b0)") == 3
     assert "u_user_rib_if.cmd_valid = '0;" in core
     assert "5'd0: begin" in core
     assert "5'd4: begin" in core