feat: add HP mailbox and PLIC tests; enhance existing test coverage

- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.

configs/ci/ihp130-hp.mk

@@ -0,0 +1,20 @@
+SOC                := MINI
+PDK                := IHP130
+HAVE_PLL           := NO
+HAVE_HP            := YES
+HP_CONFIG          := rv32imafdc_max
+HAVE_SRAM_IF       := YES
+HAVE_SRAM_MACRO    := YES
+SRAM_SIZE_KIB      := 32
+PDK_BEHAV          := YES
+EXT_CLK_HZ         := 72000000
+AUD_CLK_HZ         := 18432000
+CLINT_TIMEBASE_HZ  := 1000000
+ISA                := RV32IM
+HAVE_CSR           := YES
+APP                := hp_boot
+LINK_TYPE          := ld2_all_sram
+SIM_SUCCESS_MARKER := SIM_TEST_PASS
+RTL_SIM_TIMEOUT    := 20000000
+FIRMWARE_NAME      := retrosoc_hp_boot
+SIM_FIRMWARE_NAME  := retrosoc_hp_boot