mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: add HP mailbox and PLIC tests; enhance existing test coverage
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests. - Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations. - Added plic_tb to validate PLIC priority, claim, and completion mechanisms. - Enhanced pll_ctrl_tb to initialize additional system control signals. - Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior. - Improved sysctrl_tb to include tests for HP lifecycle control and status registers. - Added tests for HP boot bundle layout, CRC, and payload validation. - Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox. - Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries. - Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration. - Added performance log tests to validate LP and HP coremark ratios. - Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
This commit is contained in:
101 files changed
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@@ -0,0 +1,273 @@
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`timescale 1ns / 1ps
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`include "axi4_define.svh"
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module axi4_downsizer_64to32_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(64),
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.ID_WIDTH (3),
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.USER_WIDTH(1)
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) wide (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) narrow (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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axi4_downsizer_64to32 u_dut (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.wide (wide),
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.narrow (narrow)
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);
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task automatic init_bus;
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begin
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wide.awid = '0;
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wide.awaddr = '0;
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wide.awlen = '0;
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wide.awsize = `AXI4_BURST_SIZE_8BYTES;
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wide.awburst = `AXI4_BURST_TYPE_INCR;
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wide.awlock = `AXI4_LOCK_NORM;
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wide.awcache = `AXI4_CACHE_NO_BUF;
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wide.awprot = `AXI4_PROT_DATA;
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wide.awqos = `AXI4_QOS_NORMAL;
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wide.awregion = `AXI4_REGION_NORMAL;
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wide.awuser = '0;
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wide.awvalid = 1'b0;
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wide.wdata = '0;
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wide.wstrb = '0;
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wide.wlast = 1'b0;
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wide.wuser = '0;
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wide.wvalid = 1'b0;
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wide.bready = 1'b0;
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wide.arid = '0;
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wide.araddr = '0;
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wide.arlen = '0;
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wide.arsize = `AXI4_BURST_SIZE_8BYTES;
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wide.arburst = `AXI4_BURST_TYPE_INCR;
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wide.arlock = `AXI4_LOCK_NORM;
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wide.arcache = `AXI4_CACHE_NO_BUF;
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wide.arprot = `AXI4_PROT_DATA;
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wide.arqos = `AXI4_QOS_NORMAL;
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wide.arregion = `AXI4_REGION_NORMAL;
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wide.aruser = '0;
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wide.arvalid = 1'b0;
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wide.rready = 1'b0;
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narrow.awready = 1'b0;
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narrow.wready = 1'b0;
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narrow.bid = '0;
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narrow.bresp = `AXI4_RESP_OKAY;
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narrow.buser = '0;
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narrow.bvalid = 1'b0;
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narrow.arready = 1'b0;
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narrow.rid = '0;
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narrow.rdata = '0;
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narrow.rresp = `AXI4_RESP_OKAY;
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narrow.rlast = 1'b0;
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narrow.ruser = '0;
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narrow.rvalid = 1'b0;
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end
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endtask
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task automatic accept_read(input logic [31:0] address, input logic [7:0] length,
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input logic [2:0] size, input logic [2:0] id,
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input logic [7:0] expected_length);
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begin
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@(negedge clk_i);
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wide.araddr = address;
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wide.arlen = length;
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wide.arsize = size;
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wide.arid = id;
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wide.arvalid = 1'b1;
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#1;
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if (wide.arready) $fatal(1, "read address ignored narrow backpressure");
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narrow.arready = 1'b1;
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#1;
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if (!narrow.arvalid || narrow.araddr != address || narrow.arlen != expected_length ||
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narrow.arsize != ((size == 3'd3) ? 3'd2 : size)) begin
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$fatal(1, "read address conversion mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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wide.arvalid = 1'b0;
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narrow.arready = 1'b0;
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end
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endtask
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task automatic accept_write(input logic [31:0] address, input logic [7:0] length,
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input logic [2:0] size, input logic [2:0] id,
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input logic [7:0] expected_length);
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begin
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@(negedge clk_i);
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wide.awaddr = address;
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wide.awlen = length;
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wide.awsize = size;
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wide.awid = id;
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wide.awvalid = 1'b1;
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#1;
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if (wide.awready) $fatal(1, "write address ignored narrow backpressure");
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narrow.awready = 1'b1;
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#1;
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if (!narrow.awvalid || narrow.awaddr != address || narrow.awlen != expected_length ||
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narrow.awsize != ((size == 3'd3) ? 3'd2 : size)) begin
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$fatal(1, "write address conversion mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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wide.awvalid = 1'b0;
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narrow.awready = 1'b0;
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end
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endtask
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task automatic return_write_response(input logic [2:0] expected_id, input logic [1:0] response);
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begin
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@(negedge clk_i);
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narrow.bresp = response;
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narrow.bvalid = 1'b1;
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wide.bready = 1'b0;
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#1;
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if (!narrow.bready) $fatal(1, "narrow write response was not accepted into buffer");
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@(posedge clk_i);
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@(negedge clk_i);
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narrow.bvalid = 1'b0;
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#1;
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if (!wide.bvalid || wide.bid != expected_id || wide.bresp != response) begin
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$fatal(1, "buffered write response mismatch");
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end
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repeat (2) @(posedge clk_i);
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if (!wide.bvalid || wide.bid != expected_id || wide.bresp != response) begin
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$fatal(1, "write response changed under backpressure");
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end
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@(negedge clk_i);
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wide.bready = 1'b1;
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@(posedge clk_i);
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@(negedge clk_i);
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wide.bready = 1'b0;
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end
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endtask
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initial begin
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init_bus();
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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accept_read(32'h0000_0040, 8'd0, 3'd3, 3'd5, 8'd1);
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@(negedge clk_i);
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narrow.rdata = 32'h1122_3344;
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narrow.rresp = `AXI4_RESP_SLAVE_ERROR;
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narrow.rlast = 1'b0;
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narrow.rvalid = 1'b1;
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wide.rready = 1'b0;
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#1;
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if (!narrow.rready || wide.rvalid) $fatal(1, "lower read beat was not buffered");
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@(posedge clk_i);
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@(negedge clk_i);
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narrow.rdata = 32'h5566_7788;
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narrow.rresp = `AXI4_RESP_OKAY;
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narrow.rlast = 1'b1;
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#1;
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if (!wide.rvalid || narrow.rready || wide.rid != 3'd5 ||
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wide.rdata != 64'h5566_7788_1122_3344 || wide.rresp != `AXI4_RESP_SLAVE_ERROR ||
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!wide.rlast) begin
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$fatal(1, "64-bit read assembly or backpressure mismatch");
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end
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repeat (2) @(posedge clk_i);
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@(negedge clk_i);
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wide.rready = 1'b1;
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@(posedge clk_i);
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@(negedge clk_i);
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wide.rready = 1'b0;
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narrow.rvalid = 1'b0;
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accept_read(32'h0000_0000, 8'd1, 3'd2, 3'd3, 8'd1);
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@(negedge clk_i);
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narrow.rdata = 32'hA5A5_0000;
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narrow.rresp = `AXI4_RESP_OKAY;
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narrow.rlast = 1'b0;
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narrow.rvalid = 1'b1;
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wide.rready = 1'b1;
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#1;
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if (wide.rdata != 64'h0000_0000_A5A5_0000 || wide.rid != 3'd3) begin
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$fatal(1, "lower 32-bit read lane mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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narrow.rdata = 32'hA5A5_0001;
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narrow.rlast = 1'b1;
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#1;
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if (wide.rdata != 64'hA5A5_0001_0000_0000 || !wide.rlast) begin
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$fatal(1, "upper 32-bit read lane mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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wide.rready = 1'b0;
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narrow.rvalid = 1'b0;
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accept_write(32'h0000_0080, 8'd0, 3'd3, 3'd6, 8'd1);
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@(negedge clk_i);
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wide.wdata = 64'h1122_3344_5566_7788;
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wide.wstrb = 8'hF3;
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wide.wlast = 1'b1;
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wide.wvalid = 1'b1;
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narrow.wready = 1'b1;
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#1;
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if (narrow.wdata != 32'h5566_7788 || narrow.wstrb != 4'h3 || narrow.wlast || wide.wready) begin
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$fatal(1, "lower 64-bit write split mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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#1;
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if (narrow.wdata != 32'h1122_3344 || narrow.wstrb != 4'hF || !narrow.wlast ||
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!wide.wready) begin
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$fatal(1, "upper 64-bit write split mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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wide.wvalid = 1'b0;
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narrow.wready = 1'b0;
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return_write_response(3'd6, `AXI4_RESP_DECODE_ERROR);
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accept_write(32'h0000_0004, 8'd1, 3'd2, 3'd2, 8'd1);
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@(negedge clk_i);
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wide.wdata = 64'hCAFE_0000_DEAD_0000;
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wide.wstrb = 8'hF0;
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wide.wlast = 1'b0;
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wide.wvalid = 1'b1;
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narrow.wready = 1'b1;
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#1;
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if (narrow.wdata != 32'hCAFE_0000 || narrow.wstrb != 4'hF || !wide.wready) begin
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$fatal(1, "upper 32-bit write lane mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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wide.wdata = 64'hDEAD_0000_CAFE_0001;
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wide.wstrb = 8'h0F;
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wide.wlast = 1'b1;
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#1;
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if (narrow.wdata != 32'hCAFE_0001 || narrow.wstrb != 4'hF || !wide.wready) begin
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$fatal(1, "lower 32-bit write lane mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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wide.wvalid = 1'b0;
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narrow.wready = 1'b0;
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return_write_response(3'd2, `AXI4_RESP_OKAY);
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$display("AXI4 64-to-32 downsizer test passed");
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$finish;
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end
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endmodule
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@@ -4,7 +4,7 @@
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`include "rib_defs.svh"
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module axi4_interconnect_tb;
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localparam int NumMasters = 7;
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localparam int NumMasters = 8;
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localparam int NumTargets = 9;
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logic clk_i = 1'b0;
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@@ -288,6 +288,50 @@ module axi4_interconnect_tb;
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end
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endtask
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task automatic issue_hp_accesses;
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integer beat;
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begin
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@(negedge clk_i);
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masters[7].araddr = 32'h3800_0000;
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masters[7].arlen = 8'd15;
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masters[7].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[7].arready);
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@(negedge clk_i);
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masters[7].arvalid = 1'b0;
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masters[7].rready = 1'b1;
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beat = 0;
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while (beat < 16) begin
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@(negedge clk_i);
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if (masters[7].rvalid) begin
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if ((masters[7].rresp != `AXI4_RESP_OKAY) ||
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(masters[7].rlast != (beat == 15)) || fault_valid_o) begin
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$fatal(1, "HP SDRAM burst was rejected or misclassified");
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end
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beat = beat + 1;
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end
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end
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@(negedge clk_i);
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masters[7].rready = 1'b0;
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masters[7].araddr = 32'hA000_7000;
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masters[7].arlen = 8'd0;
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masters[7].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[7].arready);
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@(negedge clk_i);
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masters[7].arvalid = 1'b0;
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masters[7].rready = 1'b1;
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while (!masters[7].rvalid) @(negedge clk_i);
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#1;
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if ((masters[7].rresp != `AXI4_RESP_DECODE_ERROR) || !fault_valid_o ||
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(fault_master_o != 3'd7) || (fault_addr_o != 32'hA000_7000) ||
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(fault_code_o != `RIB_RESP_DECERR)) begin
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$fatal(1, "HP decode fault attribution mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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masters[7].rready = 1'b0;
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end
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endtask
|
||||
|
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initial begin
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||||
`INIT_MASTER(0)
|
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`INIT_MASTER(1)
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@@ -295,6 +339,8 @@ module axi4_interconnect_tb;
|
||||
`INIT_MASTER(3)
|
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`INIT_MASTER(4)
|
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`INIT_MASTER(5)
|
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`INIT_MASTER(6)
|
||||
`INIT_MASTER(7)
|
||||
repeat (4) @(posedge clk_i);
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||||
rst_n_i = 1'b1;
|
||||
|
||||
@@ -303,6 +349,7 @@ module axi4_interconnect_tb;
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||||
issue_mgmt_error_read(32'h3000_0000, 8'd16, `AXI4_RESP_SLAVE_ERROR, `RIB_RESP_BURSTERR);
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issue_denied_user_write(32'h1000_B000);
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||||
issue_contending_sdio_faults();
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||||
issue_hp_accesses();
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||||
|
||||
$display("AXI4 interconnect fault classification test passed");
|
||||
$finish;
|
||||
|
||||
@@ -0,0 +1,89 @@
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||||
`timescale 1ns / 1ps
|
||||
|
||||
module hp_mailbox_tb;
|
||||
logic clk_i = 1'b0;
|
||||
logic rst_n_i = 1'b0;
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||||
logic lp_irq_o;
|
||||
logic hp_irq_o;
|
||||
logic [31:0] value;
|
||||
apb4_if apb4 (
|
||||
.pclk (clk_i),
|
||||
.presetn(rst_n_i)
|
||||
);
|
||||
|
||||
always #5 clk_i = ~clk_i;
|
||||
|
||||
apb4_hp_mailbox u_dut (
|
||||
.clk_i,
|
||||
.rst_n_i,
|
||||
.apb4,
|
||||
.lp_irq_o,
|
||||
.hp_irq_o
|
||||
);
|
||||
|
||||
task automatic apb_write(input logic [31:0] address, input logic [31:0] data);
|
||||
begin
|
||||
@(negedge clk_i);
|
||||
apb4.paddr = address;
|
||||
apb4.pwdata = data;
|
||||
apb4.pstrb = 4'hf;
|
||||
apb4.pwrite = 1'b1;
|
||||
apb4.psel = 1'b1;
|
||||
apb4.penable = 1'b1;
|
||||
while (!apb4.pready) @(negedge clk_i);
|
||||
apb4.psel = 1'b0;
|
||||
apb4.penable = 1'b0;
|
||||
apb4.pwrite = 1'b0;
|
||||
apb4.pstrb = '0;
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic apb_read(input logic [31:0] address, output logic [31:0] data);
|
||||
begin
|
||||
@(negedge clk_i);
|
||||
apb4.paddr = address;
|
||||
apb4.pstrb = '0;
|
||||
apb4.pwrite = 1'b0;
|
||||
apb4.psel = 1'b1;
|
||||
apb4.penable = 1'b1;
|
||||
while (!apb4.pready) @(negedge clk_i);
|
||||
data = apb4.prdata;
|
||||
apb4.psel = 1'b0;
|
||||
apb4.penable = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
apb4.psel = 1'b0;
|
||||
apb4.penable = 1'b0;
|
||||
apb4.pwrite = 1'b0;
|
||||
apb4.paddr = '0;
|
||||
apb4.pwdata = '0;
|
||||
apb4.pstrb = '0;
|
||||
repeat (4) @(posedge clk_i);
|
||||
rst_n_i = 1'b1;
|
||||
|
||||
apb_read(32'h0, value);
|
||||
if (value != 32'h0001_0000) $fatal(1, "mailbox version mismatch");
|
||||
apb_write(32'h44, 32'h1);
|
||||
apb_write(32'h10, 32'h1);
|
||||
apb_write(32'h18, 32'h1234);
|
||||
apb_write(32'h1c, 32'h1);
|
||||
if (!hp_irq_o) $fatal(1, "LP-to-HP doorbell did not assert");
|
||||
apb_read(32'h18, value);
|
||||
if (value != 32'h1234) $fatal(1, "LP sequence did not persist");
|
||||
apb_write(32'h40, 32'h1);
|
||||
if (hp_irq_o) $fatal(1, "HP interrupt did not clear");
|
||||
|
||||
apb_write(32'h34, 32'h1);
|
||||
apb_write(32'h20, 32'h1);
|
||||
apb_write(32'h2c, 32'h1);
|
||||
if (!lp_irq_o) $fatal(1, "HP-to-LP doorbell did not assert");
|
||||
apb_write(32'h30, 32'h1);
|
||||
if (lp_irq_o) $fatal(1, "LP interrupt did not clear");
|
||||
|
||||
$display("HP mailbox register and doorbell test passed");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,92 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module plic_tb;
|
||||
logic clk_i = 1'b0;
|
||||
logic rst_n_i = 1'b0;
|
||||
logic [31:0] source_i = '0;
|
||||
logic [ 1:0] context_irq_o;
|
||||
logic [31:0] value;
|
||||
apb4_if apb4 (
|
||||
.pclk (clk_i),
|
||||
.presetn(rst_n_i)
|
||||
);
|
||||
|
||||
always #5 clk_i = ~clk_i;
|
||||
|
||||
apb4_plic u_dut (
|
||||
.clk_i,
|
||||
.rst_n_i,
|
||||
.source_i,
|
||||
.apb4,
|
||||
.context_irq_o
|
||||
);
|
||||
|
||||
task automatic apb_write(input logic [31:0] address, input logic [31:0] data);
|
||||
begin
|
||||
@(negedge clk_i);
|
||||
apb4.paddr = address;
|
||||
apb4.pwdata = data;
|
||||
apb4.pstrb = 4'hf;
|
||||
apb4.pwrite = 1'b1;
|
||||
apb4.psel = 1'b1;
|
||||
apb4.penable = 1'b1;
|
||||
while (!apb4.pready) @(negedge clk_i);
|
||||
if (apb4.pslverr) $fatal(1, "PLIC write failed at %h", address);
|
||||
apb4.psel = 1'b0;
|
||||
apb4.penable = 1'b0;
|
||||
apb4.pwrite = 1'b0;
|
||||
apb4.pstrb = '0;
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic apb_read(input logic [31:0] address, output logic [31:0] data);
|
||||
begin
|
||||
@(negedge clk_i);
|
||||
apb4.paddr = address;
|
||||
apb4.pstrb = '0;
|
||||
apb4.pwrite = 1'b0;
|
||||
apb4.psel = 1'b1;
|
||||
apb4.penable = 1'b1;
|
||||
while (!apb4.pready) @(negedge clk_i);
|
||||
if (apb4.pslverr) $fatal(1, "PLIC read failed at %h", address);
|
||||
data = apb4.prdata;
|
||||
apb4.psel = 1'b0;
|
||||
apb4.penable = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
apb4.psel = 1'b0;
|
||||
apb4.penable = 1'b0;
|
||||
apb4.pwrite = 1'b0;
|
||||
apb4.paddr = '0;
|
||||
apb4.pwdata = '0;
|
||||
apb4.pstrb = '0;
|
||||
repeat (4) @(posedge clk_i);
|
||||
rst_n_i = 1'b1;
|
||||
|
||||
apb_write(32'h0000_0004, 32'd3);
|
||||
apb_write(32'h0000_0008, 32'd5);
|
||||
apb_write(32'h0000_2080, 32'h0000_0006);
|
||||
apb_write(32'h0020_1000, 32'd0);
|
||||
source_i[1] = 1'b1;
|
||||
source_i[2] = 1'b1;
|
||||
repeat (2) @(posedge clk_i);
|
||||
if (!context_irq_o[1]) $fatal(1, "supervisor context IRQ did not assert");
|
||||
apb_read(32'h0020_1004, value);
|
||||
if (value != 32'd2) $fatal(1, "highest-priority source was not claimed");
|
||||
source_i[2] = 1'b0;
|
||||
apb_write(32'h0020_1004, 32'd2);
|
||||
repeat (2) @(posedge clk_i);
|
||||
apb_read(32'h0020_1004, value);
|
||||
if (value != 32'd1) $fatal(1, "remaining source was not claimed");
|
||||
source_i[1] = 1'b0;
|
||||
apb_write(32'h0020_1004, 32'd1);
|
||||
repeat (2) @(posedge clk_i);
|
||||
if (context_irq_o[1]) $fatal(1, "supervisor context IRQ did not clear");
|
||||
|
||||
$display("PLIC priority, claim, and completion test passed");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -120,14 +120,27 @@ module pll_ctrl_tb;
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
apb4.psel = 1'b0;
|
||||
apb4.paddr = '0;
|
||||
apb4.pwdata = '0;
|
||||
apb4.pstrb = '0;
|
||||
sysctrl.user_bus_idle_i = 1'b1;
|
||||
sysctrl.fault_access_i = 1'b0;
|
||||
sysctrl.fault_master_i = '0;
|
||||
sysctrl.rtc_wake_i = 1'b0;
|
||||
apb4.psel = 1'b0;
|
||||
apb4.paddr = '0;
|
||||
apb4.pwdata = '0;
|
||||
apb4.pstrb = '0;
|
||||
sysctrl.user_bus_idle_i = 1'b1;
|
||||
sysctrl.fault_access_i = 1'b0;
|
||||
sysctrl.fault_master_i = '0;
|
||||
sysctrl.fault_code_i = '0;
|
||||
sysctrl.perf_mgmt_wait_i = '0;
|
||||
sysctrl.perf_user_wait_i = '0;
|
||||
sysctrl.perf_dma_wait_i = '0;
|
||||
sysctrl.perf_sdio0_wait_i = '0;
|
||||
sysctrl.perf_sdio1_wait_i = '0;
|
||||
sysctrl.perf_usb2_wait_i = '0;
|
||||
sysctrl.perf_apb4_periph_wait_i = '0;
|
||||
sysctrl.perf_apb4_system_wait_i = '0;
|
||||
sysctrl.perf_sdram_wait_i = '0;
|
||||
sysctrl.perf_psram_wait_i = '0;
|
||||
sysctrl.perf_flash_wait_i = '0;
|
||||
sysctrl.rtc_wake_i = 1'b0;
|
||||
sysctrl.hp_present_i = 1'b0;
|
||||
#100;
|
||||
rst_n_i = 1'b1;
|
||||
repeat (2) begin
|
||||
|
||||
@@ -40,6 +40,8 @@ module soc_irq_topology_tb;
|
||||
17: expect_irq(32'd1 << 21);
|
||||
18: expect_irq(32'd1 << 23);
|
||||
19: expect_irq(32'd1 << 24);
|
||||
20: expect_irq(32'd1 << 25);
|
||||
21: expect_irq(32'd1 << 26);
|
||||
default: expect_irq(32'd1 << (bit_index + 7));
|
||||
endcase
|
||||
end
|
||||
@@ -64,7 +66,7 @@ module soc_irq_topology_tb;
|
||||
$fatal(1, "SDIO core IRQ bits are not low when sources are low: IRQ10=%b IRQ21=%b",
|
||||
s_irq[10], s_irq[21]);
|
||||
end
|
||||
if ((s_irq[31:25] !== '0) || (s_irq[19:18] !== '0)) begin
|
||||
if ((s_irq[31:27] !== '0) || (s_irq[19:18] !== '0)) begin
|
||||
$fatal(1, "unallocated core IRQ bits are not low: %h", s_irq);
|
||||
end
|
||||
|
||||
|
||||
+28
-1
@@ -93,6 +93,7 @@ module sysctrl_tb;
|
||||
sysctrl.perf_psram_wait_i = 64'd17;
|
||||
sysctrl.perf_flash_wait_i = 64'd18;
|
||||
sysctrl.rtc_wake_i = 1'b0;
|
||||
sysctrl.hp_present_i = 1'b0;
|
||||
pll_ctrl.req_ready_i = 1'b1;
|
||||
pll_ctrl.rsp_active_sel_i = '0;
|
||||
pll_ctrl.rsp_active_valid_i = 1'b0;
|
||||
@@ -216,7 +217,33 @@ module sysctrl_tb;
|
||||
$fatal(1, "RTC wake sticky status W1C failed");
|
||||
end
|
||||
|
||||
$display("SystemCtrl register, lifecycle, fault, performance, and RTC wake test passed");
|
||||
read_register(32'h1000_B0A8, read_data);
|
||||
if (read_data !== 32'h0000_0000) $fatal(1, "absent HP status was not zero");
|
||||
write_register(32'h1000_B0A4, 32'h0000_0001);
|
||||
write_register(32'h1000_B0AC, 32'h0000_0001);
|
||||
if (sysctrl.hp_release_o || sysctrl.debug_hp_select_o) begin
|
||||
$fatal(1, "absent HP accepted lifecycle control");
|
||||
end
|
||||
|
||||
sysctrl.hp_present_i = 1'b1;
|
||||
read_register(32'h1000_B0A8, read_data);
|
||||
if (read_data !== 32'h0000_0005) $fatal(1, "present HP reset status mismatch");
|
||||
write_register(32'h1000_B0AC, 32'h0000_0001);
|
||||
if (!sysctrl.debug_hp_select_o) $fatal(1, "HP debug selection was not accepted in reset");
|
||||
write_register(32'h1000_B0A4, 32'h0000_0001);
|
||||
read_register(32'h1000_B0A8, read_data);
|
||||
if ((read_data !== 32'h0000_0003) || !sysctrl.hp_release_o) begin
|
||||
$fatal(1, "HP release status mismatch");
|
||||
end
|
||||
write_register(32'h1000_B0AC, 32'h0000_0000);
|
||||
if (!sysctrl.debug_hp_select_o) $fatal(1, "running HP allowed JTAG selection change");
|
||||
write_register(32'h1000_B0A4, 32'h0000_0000);
|
||||
write_register(32'h1000_B0AC, 32'h0000_0000);
|
||||
if (sysctrl.hp_release_o || sysctrl.debug_hp_select_o) begin
|
||||
$fatal(1, "HP reset/debug return did not complete");
|
||||
end
|
||||
|
||||
$display("SystemCtrl register, lifecycle, fault, performance, RTC wake, and HP test passed");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Reference in new issue
Block a user