feat: add HP mailbox and PLIC tests; enhance existing test coverage

- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.

tests/test_librelane_flow.py

@@ -44,10 +44,10 @@ def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> N
     sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER}
     placed = [instance for side in module.SIDE_ORDER for instance in sides[side]]
 
-    assert len(placed) == 189
+    assert len(placed) == 191
     assert len(placed) == len(set(placed))
     assert {side: len(instances) for side, instances in sides.items()} == {
-        "south": 30,
+        "south": 32,
         "east": 52,
         "north": 48,
         "west": 59,