admin/retroSoC
1
0 Fork 0
mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-06 14:55:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

refactor: refactor macro definitions for consistency and readability across multiple headers

Browse Source 
- Adjusted formatting of macro definitions in i2c.h, lcd.h, shell.h, irq.c, system_irq_handler.c, and clock.c to align with coding standards.
- Ensured consistent spacing and indentation for better readability.
This commit is contained in:
maksyuki committed 2026-07-21 12:11:52 +08:00
1 parent 7418acfe42
commit 91b4f78892
18 files changed
+443 -442
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

.clang-format
+1
View File
@@ -8,3 +8,4 @@ AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: Never AllowShortIfStatementsOnASingleLine: Never
PointerAlignment: Right PointerAlignment: Right
SortIncludes: Never SortIncludes: Never
AlignConsecutiveMacros: AcrossEmptyLinesAndComments
app/benchmark/coremark/core_portme.c
+5 -5
View File
@@ -56,12 +56,12 @@ static CORETIMETYPE barebones_clock(void) {
does not occur. If there are issues with the return value overflowing, does not occur. If there are issues with the return value overflowing,
increase this value. increase this value.
*/ */
#define CLOCKS_PER_SEC 72000000 #define CLOCKS_PER_SEC 72000000
#define GETMYTIME(_t) (*_t = barebones_clock()) #define GETMYTIME(_t) (*_t = barebones_clock())
#define MYTIMEDIFF(fin, ini) ((fin) - (ini)) #define MYTIMEDIFF(fin, ini) ((fin) - (ini))
#define TIMER_RES_DIVIDER 1 #define TIMER_RES_DIVIDER 1
#define SAMPLE_TIME_IMPLEMENTATION 1 #define SAMPLE_TIME_IMPLEMENTATION 1
#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER) #define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
/** Define Host specific (POSIX), or target specific global time variables. */ /** Define Host specific (POSIX), or target specific global time variables. */
static CORETIMETYPE start_time_val, stop_time_val; static CORETIMETYPE start_time_val, stop_time_val;
app/benchmark/coremark/core_portme.h
+3 -3
View File
@@ -98,7 +98,7 @@ typedef unsigned char ee_u8;
typedef unsigned int ee_u32; typedef unsigned int ee_u32;
typedef ee_u32 ee_ptr_int; typedef ee_u32 ee_ptr_int;
typedef size_t ee_size_t; typedef size_t ee_size_t;
#define NULL ((void *)0) #define NULL ((void *)0)
/* align_mem : /* align_mem :
This macro is used to align an offset to point to a 32b value. It is This macro is used to align an offset to point to a 32b value. It is
used in the Matrix algorithm to initialize the input memory blocks. used in the Matrix algorithm to initialize the input memory blocks.
@@ -156,8 +156,8 @@ typedef ee_u32 CORE_TICKS;
#ifndef MULTITHREAD #ifndef MULTITHREAD
#define MULTITHREAD 1 #define MULTITHREAD 1
#define USE_PTHREAD 0 #define USE_PTHREAD 0
#define USE_FORK 0 #define USE_FORK 0
#define USE_SOCKET 0 #define USE_SOCKET 0
#endif #endif
/* Configuration : MAIN_HAS_NOARGC /* Configuration : MAIN_HAS_NOARGC
app/board/include/retrosoc/board/at24cxx.h
+1 -1
View File
@@ -1,7 +1,7 @@
#ifndef RETROSOC_BOARD_AT24CXX_H #ifndef RETROSOC_BOARD_AT24CXX_H
#define RETROSOC_BOARD_AT24CXX_H #define RETROSOC_BOARD_AT24CXX_H
#define I2C_TEST_NUM 24 #define I2C_TEST_NUM 24
#define AT24C64_DEV_ADDR 0x50 #define AT24C64_DEV_ADDR 0x50
void at24cxx_test(void); void at24cxx_test(void);
app/board/include/retrosoc/board/pcf8563b.h
+15 -15
View File
@@ -3,24 +3,24 @@
#include <stdint.h> #include <stdint.h>
#define PCF8563B_DEV_ADDR 0x51 #define PCF8563B_DEV_ADDR 0x51
#define PCF8563B_CTL_STATUS1 ((uint8_t)0x00) #define PCF8563B_CTL_STATUS1 ((uint8_t)0x00)
#define PCF8563B_CTL_STATUS2 ((uint8_t)0x01) #define PCF8563B_CTL_STATUS2 ((uint8_t)0x01)
#define PCF8563B_SECOND_REG ((uint8_t)0x02) #define PCF8563B_SECOND_REG ((uint8_t)0x02)
#define PCF8563B_MINUTE_REG ((uint8_t)0x03) #define PCF8563B_MINUTE_REG ((uint8_t)0x03)
#define PCF8563B_HOUR_REG ((uint8_t)0x04) #define PCF8563B_HOUR_REG ((uint8_t)0x04)
#define PCF8563B_DAY_REG ((uint8_t)0x05) #define PCF8563B_DAY_REG ((uint8_t)0x05)
#define PCF8563B_WEEKDAY_REG ((uint8_t)0x06) #define PCF8563B_WEEKDAY_REG ((uint8_t)0x06)
#define PCF8563B_MONTH_REG ((uint8_t)0x07) #define PCF8563B_MONTH_REG ((uint8_t)0x07)
#define PCF8563B_YEAR_REG ((uint8_t)0x08) #define PCF8563B_YEAR_REG ((uint8_t)0x08)
#define SECOND_MINUTE_REG_WIDTH ((uint8_t)0x7F) #define SECOND_MINUTE_REG_WIDTH ((uint8_t)0x7F)
#define HOUR_DAY_REG_WIDTH ((uint8_t)0x3F) #define HOUR_DAY_REG_WIDTH ((uint8_t)0x3F)
#define WEEKDAY_REG_WIDTH ((uint8_t)0x07) #define WEEKDAY_REG_WIDTH ((uint8_t)0x07)
#define MONTH_REG_WIDTH ((uint8_t)0x1F) #define MONTH_REG_WIDTH ((uint8_t)0x1F)
#define YEAR_REG_WIDTH ((uint8_t)0xFF) #define YEAR_REG_WIDTH ((uint8_t)0xFF)
#define BCD_Century ((uint8_t)0x80) #define BCD_Century ((uint8_t)0x80)
typedef struct { typedef struct {
struct { struct {
app/media/src/donut.c
+8 -8
View File
@@ -31,15 +31,15 @@
#include <retrosoc/hal/lcd.h> #include <retrosoc/hal/lcd.h>
#include <retrosoc/media/donut.h> #include <retrosoc/media/donut.h>
#define likely(x) __builtin_expect(!!(x), 1) #define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0) #define unlikely(x) __builtin_expect(!!(x), 0)
#define GRAY_LEVELS 12 #define GRAY_LEVELS 12
// screen framebuffer (128x128) // screen framebuffer (128x128)
#define scale_x 8 #define scale_x 8
#define scale_y 8 #define scale_y 8
#define DONUT_SIZE 16 #define DONUT_SIZE 16
#define DONUT_WIDTH DONUT_SIZE *scale_x #define DONUT_WIDTH DONUT_SIZE *scale_x
#define DONUT_HEIGHT DONUT_SIZE *scale_y #define DONUT_HEIGHT DONUT_SIZE *scale_y
#define RS_DONUT_FRAME_COUNT 300U #define RS_DONUT_FRAME_COUNT 300U
static const uint32_t gray_colors[GRAY_LEVELS] = { static const uint32_t gray_colors[GRAY_LEVELS] = {
crt/include/retrosoc/arch/riscv/system_base.h
+6 -6
View File
@@ -623,17 +623,17 @@ __STATIC_FORCEINLINE void __FENCE_I(void) {
} }
/** \brief Read & Write Memory barrier */ /** \brief Read & Write Memory barrier */
#define __RWMB() __FENCE(iorw, iorw) #define __RWMB() __FENCE(iorw, iorw)
/** \brief Read Memory barrier */ /** \brief Read Memory barrier */
#define __RMB() __FENCE(ir, ir) #define __RMB() __FENCE(ir, ir)
/** \brief Write Memory barrier */ /** \brief Write Memory barrier */
#define __WMB() __FENCE(ow, ow) #define __WMB() __FENCE(ow, ow)
/** \brief SMP Read & Write Memory barrier */ /** \brief SMP Read & Write Memory barrier */
#define __SMP_RWMB() __FENCE(rw, rw) #define __SMP_RWMB() __FENCE(rw, rw)
/** \brief SMP Read Memory barrier */ /** \brief SMP Read Memory barrier */
#define __SMP_RMB() __FENCE(r, r) #define __SMP_RMB() __FENCE(r, r)
/** \brief SMP Write Memory barrier */ /** \brief SMP Write Memory barrier */
#define __SMP_WMB() __FENCE(w, w) #define __SMP_WMB() __FENCE(w, w)
/** \brief CPU relax for busy loop */ /** \brief CPU relax for busy loop */
#define __CPU_RELAX() __ASM volatile("" : : : "memory") #define __CPU_RELAX() __ASM volatile("" : : : "memory")
crt/include/retrosoc/arch/riscv/system_bit.h
+31 -31
View File
@@ -31,41 +31,41 @@
#define __SYSTEM_BIT_H__ #define __SYSTEM_BIT_H__
#if __riscv_xlen == 64 #if __riscv_xlen == 64
#define SLL32 sllw #define SLL32 sllw
#define STORE sd #define STORE sd
#define LOAD ld #define LOAD ld
#define LWU lwu #define LWU lwu
#define LOG_REGBYTES 3 #define LOG_REGBYTES 3
#else #else
#define SLL32 sll #define SLL32 sll
#define STORE sw #define STORE sw
#define LOAD lw #define LOAD lw
#define LWU lw #define LWU lw
#define LOG_REGBYTES 2 #define LOG_REGBYTES 2
#endif /* __riscv_xlen */ #endif /* __riscv_xlen */
#define REGBYTES (1 << LOG_REGBYTES) #define REGBYTES (1 << LOG_REGBYTES)
#if __riscv_flen == 64 #if __riscv_flen == 64
#define FPSTORE fsd #define FPSTORE fsd
#define FPLOAD fld #define FPLOAD fld
#define LOG_FPREGBYTES 3 #define LOG_FPREGBYTES 3
#else #else
#define FPSTORE fsw #define FPSTORE fsw
#define FPLOAD flw #define FPLOAD flw
#define LOG_FPREGBYTES 2 #define LOG_FPREGBYTES 2
#endif /* __riscv_flen */ #endif /* __riscv_flen */
#define FPREGBYTES (1 << LOG_FPREGBYTES) #define FPREGBYTES (1 << LOG_FPREGBYTES)
#define __rv_likely(x) __builtin_expect((x), 1) #define __rv_likely(x) __builtin_expect((x), 1)
#define __rv_unlikely(x) __builtin_expect((x), 0) #define __rv_unlikely(x) __builtin_expect((x), 0)
#define __RV_ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) #define __RV_ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
#define __RV_ROUNDDOWN(a, b) ((a) / (b) * (b)) #define __RV_ROUNDDOWN(a, b) ((a) / (b) * (b))
#define __RV_MAX(a, b) ((a) > (b) ? (a) : (b)) #define __RV_MAX(a, b) ((a) > (b) ? (a) : (b))
#define __RV_MIN(a, b) ((a) < (b) ? (a) : (b)) #define __RV_MIN(a, b) ((a) < (b) ? (a) : (b))
#define __RV_CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) #define __RV_CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define __RV_EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define __RV_EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define __RV_INSERT_FIELD(val, which, fieldval) \ #define __RV_INSERT_FIELD(val, which, fieldval) \
@@ -76,22 +76,22 @@
#define _AT(T, X) X #define _AT(T, X) X
#else #else
#define __AC(X, Y) (X##Y) #define __AC(X, Y) (X##Y)
#define _AC(X, Y) __AC(X, Y) #define _AC(X, Y) __AC(X, Y)
#define _AT(T, X) ((T)(X)) #define _AT(T, X) ((T)(X))
#endif #endif
#define _UL(x) (_AC(x, UL)) #define _UL(x) (_AC(x, UL))
#define _ULL(x) (_AC(x, ULL)) #define _ULL(x) (_AC(x, ULL))
#define _BITUL(x) (_UL(1) << (x)) #define _BITUL(x) (_UL(1) << (x))
#define _BITULL(x) (_ULL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x))
#define UL(x) (_UL(x)) #define UL(x) (_UL(x))
#define ULL(x) (_ULL(x)) #define ULL(x) (_ULL(x))
#define STR(x) XSTR(x) #define STR(x) XSTR(x)
#define XSTR(x) #x #define XSTR(x) #x
#define __STR(s) #s #define __STR(s) #s
#define STRINGIFY(s) __STR(s) #define STRINGIFY(s) __STR(s)
#endif #endif
crt/include/retrosoc/arch/riscv/system_csr.h
+148 -148
View File
@@ -32,202 +32,202 @@
#include <retrosoc/arch/riscv/system_bit.h> #include <retrosoc/arch/riscv/system_bit.h>
#define MSTATUS_UIE 0x00000001 #define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002 #define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004 #define MSTATUS_HIE 0x00000004
#define MSTATUS_MIE 0x00000008 #define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010 #define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020 #define MSTATUS_SPIE 0x00000020
#define MSTATUS_HPIE 0x00000040 #define MSTATUS_HPIE 0x00000040
#define MSTATUS_MPIE 0x00000080 #define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100 #define MSTATUS_SPP 0x00000100
#define MSTATUS_MPP 0x00001800 #define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000 #define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000 #define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000 #define MSTATUS_MPRV 0x00020000
#define MSTATUS_PUM 0x00040000 #define MSTATUS_PUM 0x00040000
#define MSTATUS_MXR 0x00080000 #define MSTATUS_MXR 0x00080000
#define MSTATUS_VM 0x1F000000 #define MSTATUS_VM 0x1F000000
#define MSTATUS32_SD 0x80000000 #define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000 #define MSTATUS64_SD 0x8000000000000000
#define MSTATUS_FS_INITIAL 0x00002000 #define MSTATUS_FS_INITIAL 0x00002000
#define MSTATUS_FS_CLEAN 0x00004000 #define MSTATUS_FS_CLEAN 0x00004000
#define MSTATUS_FS_DIRTY 0x00006000 #define MSTATUS_FS_DIRTY 0x00006000
#define SSTATUS_UIE 0x00000001 #define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002 #define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010 #define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100 #define SSTATUS_SPP 0x00000100
#define SSTATUS_FS 0x00006000 #define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000 #define SSTATUS_XS 0x00018000
#define SSTATUS_PUM 0x00040000 #define SSTATUS_PUM 0x00040000
#define SSTATUS32_SD 0x80000000 #define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000 #define SSTATUS64_SD 0x8000000000000000
#define MCAUSE_INTERRUPT (1ULL << ((__riscv_xlen)-1)) #define MCAUSE_INTERRUPT (1ULL << ((__riscv_xlen)-1))
#define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT)
#define MIP_STIP (1 << IRQ_S_TIMER) #define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_HTIP (1 << IRQ_H_TIMER) #define MIP_HTIP (1 << IRQ_H_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER)
#define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_HEIP (1 << IRQ_H_EXT) #define MIP_HEIP (1 << IRQ_H_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_MEIP (1 << IRQ_M_EXT)
#define MIE_SSIE MIP_SSIP #define MIE_SSIE MIP_SSIP
#define MIE_HSIE MIP_HSIP #define MIE_HSIE MIP_HSIP
#define MIE_MSIE MIP_MSIP #define MIE_MSIE MIP_MSIP
#define MIE_STIE MIP_STIP #define MIE_STIE MIP_STIP
#define MIE_HTIE MIP_HTIP #define MIE_HTIE MIP_HTIP
#define MIE_MTIE MIP_MTIP #define MIE_MTIE MIP_MTIP
#define MIE_SEIE MIP_SEIP #define MIE_SEIE MIP_SEIP
#define MIE_HEIE MIP_HEIP #define MIE_HEIE MIP_HEIP
#define MIE_MEIE MIP_MEIP #define MIE_MEIE MIP_MEIP
#define WFE_WFE 0x1 #define WFE_WFE 0x1
#define MCOUNTINHIBIT_IR (1 << 2) #define MCOUNTINHIBIT_IR (1 << 2)
#define MCOUNTINHIBIT_CY (1 << 0) #define MCOUNTINHIBIT_CY (1 << 0)
#define MMISC_CTL_NMI_CAUSE_FFF (1 << 9) #define MMISC_CTL_NMI_CAUSE_FFF (1 << 9)
#define MMISC_CTL_MISALIGN (1 << 6) #define MMISC_CTL_MISALIGN (1 << 6)
#define MMISC_CTL_BPU (1 << 3) #define MMISC_CTL_BPU (1 << 3)
#define SIP_SSIP MIP_SSIP #define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP #define SIP_STIP MIP_STIP
#define PRV_U 0 #define PRV_U 0
#define PRV_S 1 #define PRV_S 1
#define PRV_H 2 #define PRV_H 2
#define PRV_M 3 #define PRV_M 3
#define VM_MBARE 0 #define VM_MBARE 0
#define VM_MBB 1 #define VM_MBB 1
#define VM_MBBID 2 #define VM_MBBID 2
#define VM_SV32 8 #define VM_SV32 8
#define VM_SV39 9 #define VM_SV39 9
#define VM_SV48 10 #define VM_SV48 10
#define IRQ_S_SOFT 1 #define IRQ_S_SOFT 1
#define IRQ_H_SOFT 2 #define IRQ_H_SOFT 2
#define IRQ_M_SOFT 3 #define IRQ_M_SOFT 3
#define IRQ_S_TIMER 5 #define IRQ_S_TIMER 5
#define IRQ_H_TIMER 6 #define IRQ_H_TIMER 6
#define IRQ_M_TIMER 7 #define IRQ_M_TIMER 7
#define IRQ_S_EXT 9 #define IRQ_S_EXT 9
#define IRQ_H_EXT 10 #define IRQ_H_EXT 10
#define IRQ_M_EXT 11 #define IRQ_M_EXT 11
#define IRQ_COP 12 #define IRQ_COP 12
#define IRQ_HOST 13 #define IRQ_HOST 13
/* === FPU FRM Rounding Mode === */ /* === FPU FRM Rounding Mode === */
/** FPU Round to Nearest, ties to Even*/ /** FPU Round to Nearest, ties to Even*/
#define FRM_RNDMODE_RNE 0x0 #define FRM_RNDMODE_RNE 0x0
/** FPU Round Towards Zero */ /** FPU Round Towards Zero */
#define FRM_RNDMODE_RTZ 0x1 #define FRM_RNDMODE_RTZ 0x1
/** FPU Round Down (towards -inf) */ /** FPU Round Down (towards -inf) */
#define FRM_RNDMODE_RDN 0x2 #define FRM_RNDMODE_RDN 0x2
/** FPU Round Up (towards +inf) */ /** FPU Round Up (towards +inf) */
#define FRM_RNDMODE_RUP 0x3 #define FRM_RNDMODE_RUP 0x3
/** FPU Round to nearest, ties to Max Magnitude */ /** FPU Round to nearest, ties to Max Magnitude */
#define FRM_RNDMODE_RMM 0x4 #define FRM_RNDMODE_RMM 0x4
/** /**
* In instruction's rm, selects dynamic rounding mode. * In instruction's rm, selects dynamic rounding mode.
* In Rounding Mode register, Invalid */ * In Rounding Mode register, Invalid */
#define FRM_RNDMODE_DYN 0x7 #define FRM_RNDMODE_DYN 0x7
/* === FPU FFLAGS Accrued Exceptions === */ /* === FPU FFLAGS Accrued Exceptions === */
/** FPU Inexact */ /** FPU Inexact */
#define FFLAGS_AE_NX (1 << 0) #define FFLAGS_AE_NX (1 << 0)
/** FPU Underflow */ /** FPU Underflow */
#define FFLAGS_AE_UF (1 << 1) #define FFLAGS_AE_UF (1 << 1)
/** FPU Overflow */ /** FPU Overflow */
#define FFLAGS_AE_OF (1 << 2) #define FFLAGS_AE_OF (1 << 2)
/** FPU Divide by Zero */ /** FPU Divide by Zero */
#define FFLAGS_AE_DZ (1 << 3) #define FFLAGS_AE_DZ (1 << 3)
/** FPU Invalid Operation */ /** FPU Invalid Operation */
#define FFLAGS_AE_NV (1 << 4) #define FFLAGS_AE_NV (1 << 4)
/** Floating Point Register f0-f31, eg. f0 -> FREG(0) */ /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
#define FREG(idx) f##idx #define FREG(idx) f##idx
#ifdef __riscv #ifdef __riscv
#ifdef __riscv64 #ifdef __riscv64
#define MSTATUS_SD MSTATUS64_SD #define MSTATUS_SD MSTATUS64_SD
#define SSTATUS_SD SSTATUS64_SD #define SSTATUS_SD SSTATUS64_SD
#define RISCV_PGLEVEL_BITS 9 #define RISCV_PGLEVEL_BITS 9
#else #else
#define MSTATUS_SD MSTATUS32_SD #define MSTATUS_SD MSTATUS32_SD
#define SSTATUS_SD SSTATUS32_SD #define SSTATUS_SD SSTATUS32_SD
#define RISCV_PGLEVEL_BITS 10 #define RISCV_PGLEVEL_BITS 10
#endif /* __riscv64 */ #endif /* __riscv64 */
#define RISCV_PGSHIFT 12 #define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
#endif #endif
/* === Standard RISC-V CSR Registers === */ /* === Standard RISC-V CSR Registers === */
#define CSR_USTATUS 0x0 #define CSR_USTATUS 0x0
#define CSR_FFLAGS 0x1 #define CSR_FFLAGS 0x1
#define CSR_FRM 0x2 #define CSR_FRM 0x2
#define CSR_FCSR 0x3 #define CSR_FCSR 0x3
#define CSR_CYCLE 0xc00 #define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01 #define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02 #define CSR_INSTRET 0xc02
#define CSR_SSTATUS 0x100 #define CSR_SSTATUS 0x100
#define CSR_SIE 0x104 #define CSR_SIE 0x104
#define CSR_STVEC 0x105 #define CSR_STVEC 0x105
#define CSR_SSCRATCH 0x140 #define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141 #define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142 #define CSR_SCAUSE 0x142
#define CSR_SBADADDR 0x143 #define CSR_SBADADDR 0x143
#define CSR_SIP 0x144 #define CSR_SIP 0x144
#define CSR_SPTBR 0x180 #define CSR_SPTBR 0x180
#define CSR_MSTATUS 0x300 #define CSR_MSTATUS 0x300
#define CSR_MISA 0x301 #define CSR_MISA 0x301
#define CSR_MEDELEG 0x302 #define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303 #define CSR_MIDELEG 0x303
#define CSR_MIE 0x304 #define CSR_MIE 0x304
#define CSR_MTVEC 0x305 #define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306 #define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340 #define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341 #define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342 #define CSR_MCAUSE 0x342
#define CSR_MBADADDR 0x343 #define CSR_MBADADDR 0x343
#define CSR_MIP 0x344 #define CSR_MIP 0x344
#define CSR_MCYCLE 0xb00 #define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02 #define CSR_MINSTRET 0xb02
#define CSR_MUCOUNTEREN 0x320 #define CSR_MUCOUNTEREN 0x320
#define CSR_MCOUNTINHIBIT 0x320 #define CSR_MCOUNTINHIBIT 0x320
#define CSR_MSCOUNTEREN 0x321 #define CSR_MSCOUNTEREN 0x321
#define CSR_MVENDORID 0xf11 #define CSR_MVENDORID 0xf11
#define CSR_MARCHID 0xf12 #define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13 #define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14 #define CSR_MHARTID 0xf14
#define CSR_CYCLEH 0xc80 #define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81 #define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82 #define CSR_INSTRETH 0xc82
#define CSR_MCYCLEH 0xb80 #define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82 #define CSR_MINSTRETH 0xb82
/* Exception Code in MCAUSE CSR */ /* Exception Code in MCAUSE CSR */
#define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FAULT_FETCH 0x1 #define CAUSE_FAULT_FETCH 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
#define CAUSE_BREAKPOINT 0x3 #define CAUSE_BREAKPOINT 0x3
#define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_MISALIGNED_LOAD 0x4
#define CAUSE_FAULT_LOAD 0x5 #define CAUSE_FAULT_LOAD 0x5
#define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_MISALIGNED_STORE 0x6
#define CAUSE_FAULT_STORE 0x7 #define CAUSE_FAULT_STORE 0x7
#define CAUSE_USER_ECALL 0x8 #define CAUSE_USER_ECALL 0x8
#define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_SUPERVISOR_ECALL 0x9
#define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_HYPERVISOR_ECALL 0xa
#define CAUSE_MACHINE_ECALL 0xb #define CAUSE_MACHINE_ECALL 0xb
#endif #endif
crt/include/retrosoc/arch/riscv/system_gcc.h
+4 -4
View File
@@ -131,15 +131,15 @@
#define __I volatile const #define __I volatile const
#endif #endif
/** \brief Defines 'write only' permissions */ /** \brief Defines 'write only' permissions */
#define __O volatile #define __O volatile
/** \brief Defines 'read / write' permissions */ /** \brief Defines 'read / write' permissions */
#define __IO volatile #define __IO volatile
/* following defines should be used for structure members */ /* following defines should be used for structure members */
/** \brief Defines 'read only' structure member permissions */ /** \brief Defines 'read only' structure member permissions */
#define __IM volatile const #define __IM volatile const
/** \brief Defines 'write only' structure member permissions */ /** \brief Defines 'write only' structure member permissions */
#define __OM volatile #define __OM volatile
/** \brief Defines 'read/write' structure member permissions */ /** \brief Defines 'read/write' structure member permissions */
#define __IOM volatile #define __IOM volatile
crt/include/retrosoc/arch/riscv/system_timer.h
+5 -5
View File
@@ -45,18 +45,18 @@ typedef struct {
#define SysTimer_MSIP_MSIP_MASK \ #define SysTimer_MSIP_MSIP_MASK \
(1UL << SysTimer_MSIP_MSIP_POS) /*!< SysTick Timer msip: msip Mask */ (1UL << SysTimer_MSIP_MSIP_POS) /*!< SysTick Timer msip: msip Mask */
#define SysTimer_MTIMER_MASK (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMER value Mask */ #define SysTimer_MTIMER_MASK (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMER value Mask */
#define SysTimer_MTIMERCMP_MASK (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMERCMP value Mask */ #define SysTimer_MTIMERCMP_MASK (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMERCMP value Mask */
#define SysTimer_MSIP_MASK (0xFFFFFFFFUL) /*!< SysTick Timer msip value Mask */ #define SysTimer_MSIP_MASK (0xFFFFFFFFUL) /*!< SysTick Timer msip value Mask */
#define __SYSTIMER_BASEADDR 0x1000C000 #define __SYSTIMER_BASEADDR 0x1000C000
#ifndef __SYSTIMER_BASEADDR #ifndef __SYSTIMER_BASEADDR
/* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in <Device.h> */ /* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in <Device.h> */
#error "__SYSTIMER_BASEADDR is not defined, please check!" #error "__SYSTIMER_BASEADDR is not defined, please check!"
#endif #endif
/* System Timer Memory mapping of Device */ /* System Timer Memory mapping of Device */
#define SysTimer_BASE __SYSTIMER_BASEADDR /*!< SysTick Base Address */ #define SysTimer_BASE __SYSTIMER_BASEADDR /*!< SysTick Base Address */
#define SysTimer ((SysTimer_Type *)SysTimer_BASE) /*!< SysTick configuration struct */ #define SysTimer ((SysTimer_Type *)SysTimer_BASE) /*!< SysTick configuration struct */
/** /**
* \defgroup NMSIS_Core_SysTimer SysTimer Functions * \defgroup NMSIS_Core_SysTimer SysTimer Functions
crt/include/retrosoc/core/soc.h
+193 -193
View File
@@ -14,230 +14,230 @@
#define HW_CORE "none" #define HW_CORE "none"
#endif #endif
#define CPU_FREQ 72 // unit: MHz #define CPU_FREQ 72 // unit: MHz
#define UART_BPS 921600 // unit: bps #define UART_BPS 921600 // unit: bps
#define PSRAM_NUM 4 #define PSRAM_NUM 4
#define PSRAM_SCLK_MIN_FREQ 12 // unit: MHz #define PSRAM_SCLK_MIN_FREQ 12 // unit: MHz
#define PSRAM_SCLK_MAX_FREQ 133 // unit: MHz #define PSRAM_SCLK_MAX_FREQ 133 // unit: MHz
#define PSRAM_SCLK_FREQ (CPU_FREQ / 2) #define PSRAM_SCLK_FREQ (CPU_FREQ / 2)
#define SPFS_MEM_START RS_SOC_FLASH_BASE #define SPFS_MEM_START RS_SOC_FLASH_BASE
#define SPFS_MEM_OFFST RS_SOC_FLASH_SIZE #define SPFS_MEM_OFFST RS_SOC_FLASH_SIZE
#define SRAM_MEM_START RS_SOC_SRAM_BASE #define SRAM_MEM_START RS_SOC_SRAM_BASE
#define SRAM_MEM_OFFST RS_SOC_SRAM_SIZE #define SRAM_MEM_OFFST RS_SOC_SRAM_SIZE
#define SDRAM_MEM_START RS_SOC_SDRAM_BASE #define SDRAM_MEM_START RS_SOC_SDRAM_BASE
#define SDRAM_MEM_OFFST RS_SOC_SDRAM_SIZE #define SDRAM_MEM_OFFST RS_SOC_SDRAM_SIZE
#define PSRAM_MEM_START RS_SOC_PSRAM_BASE #define PSRAM_MEM_START RS_SOC_PSRAM_BASE
#define PSRAM_MEM_OFFST RS_SOC_PSRAM_SIZE #define PSRAM_MEM_OFFST RS_SOC_PSRAM_SIZE
#define XPI_MEM_START RS_SOC_XPI_BASE #define XPI_MEM_START RS_SOC_XPI_BASE
#define XPI_MEM_OFFST RS_SOC_XPI_SIZE #define XPI_MEM_OFFST RS_SOC_XPI_SIZE
#define TF_CARD_START RS_SOC_SPISD_BASE #define TF_CARD_START RS_SOC_SPISD_BASE
#define TF_CARD_OFFST RS_SOC_SPISD_SIZE #define TF_CARD_OFFST RS_SOC_SPISD_SIZE
#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset))) #define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
// gpio // gpio
#define reg_gpio_oe RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x00)) #define reg_gpio_oe RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x00))
#define reg_gpio_cs RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x04)) #define reg_gpio_cs RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x04))
#define reg_gpio_pu RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x08)) #define reg_gpio_pu RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x08))
#define reg_gpio_pd RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x0C)) #define reg_gpio_pd RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x0C))
#define reg_gpio_do RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x10)) #define reg_gpio_do RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x10))
#define reg_gpio_di RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x14)) #define reg_gpio_di RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x14))
#define reg_gpio_ien RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x18)) #define reg_gpio_ien RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x18))
#define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x1C)) #define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x1C))
#define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x20)) #define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x20))
#define reg_gpio_istat RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x24)) #define reg_gpio_istat RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x24))
#define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x28)) #define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x28))
#define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x2C)) #define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x2C))
// uart0 // uart0
#define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_NMI_UART0_BASE, UINT32_C(0x00)) #define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_NMI_UART0_BASE, UINT32_C(0x00))
#define reg_uart0_data RS_SOC_REG32(RS_SOC_NMI_UART0_BASE, UINT32_C(0x04)) #define reg_uart0_data RS_SOC_REG32(RS_SOC_NMI_UART0_BASE, UINT32_C(0x04))
// tim0 // tim0
#define reg_tim0_cfg RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x00)) #define reg_tim0_cfg RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x00))
#define reg_tim0_rld RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x04)) #define reg_tim0_rld RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x04))
#define reg_tim0_val RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x08)) #define reg_tim0_val RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x08))
// tim1 // tim1
#define reg_tim1_cfg RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x00)) #define reg_tim1_cfg RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x00))
#define reg_tim1_rld RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x04)) #define reg_tim1_rld RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x04))
#define reg_tim1_val RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x08)) #define reg_tim1_val RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x08))
// psram // psram
#define reg_psram_wait RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x00)) #define reg_psram_wait RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x00))
#define reg_psram_chd RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x04)) #define reg_psram_chd RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x04))
#define reg_psram_init RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x08)) #define reg_psram_init RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x08))
// spisd // spisd
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x00)) #define reg_spisd_mode RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x04)) #define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x08)) #define reg_spisd_addr RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x0C)) #define reg_spisd_txdata RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x10)) #define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x14)) #define reg_spisd_status RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x18)) #define reg_spisd_sync RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x18))
// i2c0 // i2c0
#define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x00)) #define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x00))
#define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x04)) #define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x04))
#define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x08)) #define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x08))
#define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x0C)) #define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x0C))
#define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x10)) #define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x10))
#define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x14)) #define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x14))
#define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x18)) #define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x18))
#define reg_i2c0_status RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x1C)) #define reg_i2c0_status RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x1C))
// i2s // i2s
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x00)) #define reg_i2s_mode RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x04)) #define reg_i2s_format RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x08)) #define reg_i2s_upbound RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x0C)) #define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x10)) #define reg_i2s_recven RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x14)) #define reg_i2s_txdata RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x18)) #define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x1C)) #define reg_i2s_status RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x1C))
// onewire // onewire
#define reg_onewire_clkdiv RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x00)) #define reg_onewire_clkdiv RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x00))
#define reg_onewire_zerocnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x04)) #define reg_onewire_zerocnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x04))
#define reg_onewire_onecnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x08)) #define reg_onewire_onecnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x08))
#define reg_onewire_rstcnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x0C)) #define reg_onewire_rstcnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x0C))
#define reg_onewire_txdata RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x10)) #define reg_onewire_txdata RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x10))
#define reg_onewire_ctrl RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x14)) #define reg_onewire_ctrl RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x14))
#define reg_onewire_status RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x18)) #define reg_onewire_status RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x18))
// xpi // xpi
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x00)) #define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x04)) #define reg_xpi_accmd RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x08)) #define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x0C)) #define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x10)) #define reg_xpi_mode RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x14)) #define reg_xpi_nss RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x18)) #define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x1C)) #define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x20)) #define reg_xpi_revdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x24)) #define reg_xpi_txupb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x28)) #define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x2C)) #define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x30)) #define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x34)) #define reg_xpi_flush RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x38)) #define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x3C)) #define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x40)) #define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x44)) #define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x48)) #define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x4C)) #define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x50)) #define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x54)) #define reg_xpi_altlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x58)) #define reg_xpi_altdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x5C)) #define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x60)) #define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x64)) #define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x68)) #define reg_xpi_datlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x6C)) #define reg_xpi_datbit RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x70)) #define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x74)) #define reg_xpi_txdata RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x78)) #define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x7C)) #define reg_xpi_start RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x80)) #define reg_xpi_status RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x80))
// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo) // dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
#define reg_dma_mode RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x00)) #define reg_dma_mode RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x04)) #define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x08)) #define reg_dma_srcincr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x0C)) #define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x10)) #define reg_dma_dstincr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x14)) #define reg_dma_xferlen RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x18)) #define reg_dma_start RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x1C)) #define reg_dma_stop RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x20)) #define reg_dma_reset RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x24)) #define reg_dma_status RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x28)) #define reg_dma_fsm RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x28))
// sys ctrl // sys ctrl
#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, (offset)) #define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, (offset))
#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x00)) #define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x00))
#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x04)) #define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x04))
#define reg_sysctrl_pll_cfg RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CFG_OFFSET) #define reg_sysctrl_pll_cfg RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CFG_OFFSET)
#define reg_sysctrl_pll_cmd RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CMD_OFFSET) #define reg_sysctrl_pll_cmd RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CMD_OFFSET)
/* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */ /* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */
#define reg_sysctrl_bus_fault_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET) #define reg_sysctrl_bus_fault_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET)
#define reg_sysctrl_bus_fault_addr RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET) #define reg_sysctrl_bus_fault_addr RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET)
#define reg_sysctrl_bus_fault_count RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET) #define reg_sysctrl_bus_fault_count RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET)
#define reg_sysctrl_pll_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_STATUS_OFFSET) #define reg_sysctrl_pll_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_STATUS_OFFSET)
#define RS_SOC_BUS_FAULT_PENDING UINT32_C(0x00000001) #define RS_SOC_BUS_FAULT_PENDING UINT32_C(0x00000001)
#define RS_SOC_BUS_FAULT_WRITE UINT32_C(0x00000002) #define RS_SOC_BUS_FAULT_WRITE UINT32_C(0x00000002)
#define RS_SOC_BUS_FAULT_REASON_MASK UINT32_C(0x0000000C) #define RS_SOC_BUS_FAULT_REASON_MASK UINT32_C(0x0000000C)
#define RS_SOC_BUS_FAULT_REASON_UNMAPPED UINT32_C(0x00000004) #define RS_SOC_BUS_FAULT_REASON_UNMAPPED UINT32_C(0x00000004)
#define RS_SOC_BUS_FAULT_REASON_RESERVED UINT32_C(0x00000008) #define RS_SOC_BUS_FAULT_REASON_RESERVED UINT32_C(0x00000008)
// clint // clint
#define reg_clint_mtimel RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x00)) #define reg_clint_mtimel RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x00))
#define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x04)) #define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x04))
#define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x08)) #define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x08))
#define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x0C)) #define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x0C))
#define reg_clint_msip RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x10)) #define reg_clint_msip RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x10))
#define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x14)) #define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x14))
// sdram // sdram
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_NMI_SDRAM_BASE, UINT32_C(0x00)) #define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_NMI_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_NMI_SDRAM_BASE, UINT32_C(0x04)) #define reg_sdram_cfg RS_SOC_REG32(RS_SOC_NMI_SDRAM_BASE, UINT32_C(0x04))
// dvp // dvp
#define reg_dvp_recven RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x00)) #define reg_dvp_recven RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x00))
#define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x04)) #define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x04))
#define reg_dvp_status RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x08)) #define reg_dvp_status RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x08))
// i2c1 // i2c1
#define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x00)) #define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x00))
#define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x04)) #define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x04))
#define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x08)) #define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x08))
#define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x0C)) #define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x0C))
#define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x10)) #define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x10))
#define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x14)) #define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x14))
#define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x18)) #define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x18))
#define reg_i2c1_status RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x1C)) #define reg_i2c1_status RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x1C))
// archinfo // archinfo
#define reg_archinfo_sys RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x00)) #define reg_archinfo_sys RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x00))
#define reg_archinfo_idl RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x04)) #define reg_archinfo_idl RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x04))
#define reg_archinfo_idh RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x08)) #define reg_archinfo_idh RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x08))
// rng // rng
#define reg_rng_ctrl RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x00)) #define reg_rng_ctrl RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x00))
#define reg_rng_seed RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x04)) #define reg_rng_seed RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x04))
#define reg_rng_val RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x08)) #define reg_rng_val RS_SOC_REG32(RS_SOC_APB_RNG_BASE, UINT32_C(0x08))
// uart // uart
#define reg_uart1_lcr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x00)) #define reg_uart1_lcr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x00))
#define reg_uart1_div RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x04)) #define reg_uart1_div RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x04))
#define reg_uart1_trx RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x08)) #define reg_uart1_trx RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x08))
#define reg_uart1_fcr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x0C)) #define reg_uart1_fcr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x0C))
#define reg_uart1_lsr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x10)) #define reg_uart1_lsr RS_SOC_REG32(RS_SOC_APB_UART1_BASE, UINT32_C(0x10))
// pwm // pwm
#define reg_pwm_ctrl RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x00)) #define reg_pwm_ctrl RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x00))
#define reg_pwm_pscr RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x04)) #define reg_pwm_pscr RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x04))
#define reg_pwm_cnt RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x08)) #define reg_pwm_cnt RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x08))
#define reg_pwm_cmp RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x0C)) #define reg_pwm_cmp RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x0C))
#define reg_pwm_cr0 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x10)) #define reg_pwm_cr0 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x10))
#define reg_pwm_cr1 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x14)) #define reg_pwm_cr1 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x14))
#define reg_pwm_cr2 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x18)) #define reg_pwm_cr2 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x18))
#define reg_pwm_cr3 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x1C)) #define reg_pwm_cr3 RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x1C))
#define reg_pwm_stat RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x20)) #define reg_pwm_stat RS_SOC_REG32(RS_SOC_APB_PWM_BASE, UINT32_C(0x20))
// ps2 // ps2
#define reg_ps2_ctrl RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x00)) #define reg_ps2_ctrl RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x00))
#define reg_ps2_data RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x04)) #define reg_ps2_data RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x04))
#define reg_ps2_stat RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x08)) #define reg_ps2_stat RS_SOC_REG32(RS_SOC_APB_PS2_BASE, UINT32_C(0x08))
// rtc // rtc
#define reg_rtc_ctrl RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x00)) #define reg_rtc_ctrl RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x00))
#define reg_rtc_pscr RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x04)) #define reg_rtc_pscr RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x04))
#define reg_rtc_cnt RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x08)) #define reg_rtc_cnt RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x08))
#define reg_rtc_alrm RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x0C)) #define reg_rtc_alrm RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x0C))
#define reg_rtc_ista RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x10)) #define reg_rtc_ista RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x10))
#define reg_rtc_ssta RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x14)) #define reg_rtc_ssta RS_SOC_REG32(RS_SOC_APB_RTC_BASE, UINT32_C(0x14))
// wdg // wdg
#define reg_wdg_ctrl RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x00)) #define reg_wdg_ctrl RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x00))
#define reg_wdg_pscr RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x04)) #define reg_wdg_pscr RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x04))
#define reg_wdg_cnt RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x08)) #define reg_wdg_cnt RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x08))
#define reg_wdg_cmp RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x0C)) #define reg_wdg_cmp RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x0C))
#define reg_wdg_stat RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x10)) #define reg_wdg_stat RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x10))
#define reg_wdg_key RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x14)) #define reg_wdg_key RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x14))
#define reg_wdg_feed RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x18)) #define reg_wdg_feed RS_SOC_REG32(RS_SOC_APB_WDG_BASE, UINT32_C(0x18))
// crc // crc
#define reg_crc_ctrl RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x00)) #define reg_crc_ctrl RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x00))
#define reg_crc_init RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x04)) #define reg_crc_init RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x04))
#define reg_crc_xorv RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x08)) #define reg_crc_xorv RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x08))
#define reg_crc_data RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x0C)) #define reg_crc_data RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x0C))
#define reg_crc_stat RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x10)) #define reg_crc_stat RS_SOC_REG32(RS_SOC_APB_CRC_BASE, UINT32_C(0x10))
// tim3 // tim3
#define reg_tim3_ctrl RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x00)) #define reg_tim3_ctrl RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x00))
#define reg_tim3_pscr RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x04)) #define reg_tim3_pscr RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x04))
#define reg_tim3_cnt RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x08)) #define reg_tim3_cnt RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x08))
#define reg_tim3_cmp RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x0C)) #define reg_tim3_cmp RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x0C))
#define reg_tim3_stat RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x10)) #define reg_tim3_stat RS_SOC_REG32(RS_SOC_APB_TMR_BASE, UINT32_C(0x10))
#ifdef IP_MDD #ifdef IP_MDD
#define reg_user_ip_reg0 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00)) #define reg_user_ip_reg0 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00))
#define reg_user_ip_reg1 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04)) #define reg_user_ip_reg1 RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04))
crt/include/retrosoc/hal/i2c.h
+3 -3
View File
@@ -5,9 +5,9 @@
#include <retrosoc/core/status.h> #include <retrosoc/core/status.h>
#define RS_I2C_XFER_WRITE 0x2U #define RS_I2C_XFER_WRITE 0x2U
#define RS_I2C_XFER_READ 0x3U #define RS_I2C_XFER_READ 0x3U
#define RS_I2C_DEVICE_ADDRESS_8BIT 0U #define RS_I2C_DEVICE_ADDRESS_8BIT 0U
#define RS_I2C_DEVICE_ADDRESS_16BIT 1U #define RS_I2C_DEVICE_ADDRESS_16BIT 1U
rs_status_t rs_i2c0_init(uint8_t clock_divider); rs_status_t rs_i2c0_init(uint8_t clock_divider);
crt/include/retrosoc/hal/lcd.h
+2 -2
View File
@@ -3,8 +3,8 @@
#include <stdint.h> #include <stdint.h>
#define lcd_dc_clr (reg_gpio_do = (uint32_t)0b000) #define lcd_dc_clr (reg_gpio_do = (uint32_t)0b000)
#define lcd_dc_set (reg_gpio_do = (uint32_t)0b100) #define lcd_dc_set (reg_gpio_do = (uint32_t)0b100)
#define USE_HORIZONTAL 2 #define USE_HORIZONTAL 2
crt/include/retrosoc/service/shell.h
+5 -5
View File
@@ -6,12 +6,12 @@
#include <retrosoc/core/status.h> #include <retrosoc/core/status.h>
#define RS_SHELL_MAX_ARGC 16U #define RS_SHELL_MAX_ARGC 16U
#define RS_SHELL_MAX_COMMANDS 72U #define RS_SHELL_MAX_COMMANDS 72U
#define RS_SHELL_MAX_COMMAND_LENGTH 100U #define RS_SHELL_MAX_COMMAND_LENGTH 100U
#define RS_SHELL_MAX_HISTORY 100U #define RS_SHELL_MAX_HISTORY 100U
#define RS_SHELL_MAX_PATH 128U #define RS_SHELL_MAX_PATH 128U
#define RS_SHELL_MAX_BUFFER (512U * 1024U) #define RS_SHELL_MAX_BUFFER (512U * 1024U)
typedef void (*rs_shell_handler_t)(int argc, char **argv); typedef void (*rs_shell_handler_t)(int argc, char **argv);
crt/src/core/irq.c
+1 -1
View File
@@ -5,7 +5,7 @@
#include <retrosoc/hal/timer.h> #include <retrosoc/hal/timer.h>
#include <retrosoc/lib/printf.h> #include <retrosoc/lib/printf.h>
#define RS_TIMER_DELTA_VALUE 360000UL #define RS_TIMER_DELTA_VALUE 360000UL
#define RS_IRQ_TEST_TIMEOUT_MS 6000U #define RS_IRQ_TEST_TIMEOUT_MS 6000U
static volatile uint32_t timer_irq_count; static volatile uint32_t timer_irq_count;
crt/src/core/system_irq_handler.c
+2 -2
View File
@@ -5,8 +5,8 @@
#include <retrosoc/core/irq.h> #include <retrosoc/core/irq.h>
#include <retrosoc/lib/printf.h> #include <retrosoc/lib/printf.h>
#define RS_EXCEPTION_COUNT 16U #define RS_EXCEPTION_COUNT 16U
#define RS_CORE_IRQ_COUNT 12U #define RS_CORE_IRQ_COUNT 12U
#define RS_EXTERNAL_IRQ_COUNT 30U #define RS_EXTERNAL_IRQ_COUNT 30U
static rs_trap_handler_t exception_handlers[RS_EXCEPTION_COUNT]; static rs_trap_handler_t exception_handlers[RS_EXCEPTION_COUNT];
crt/src/hal/clock.c
+10 -10
View File
@@ -3,17 +3,17 @@
#include <retrosoc/core/soc.h> #include <retrosoc/core/soc.h>
#include <retrosoc/hal/clock.h> #include <retrosoc/hal/clock.h>
#define RS_CLOCK_CMD_APPLY UINT32_C(0x00000001) #define RS_CLOCK_CMD_APPLY UINT32_C(0x00000001)
#define RS_CLOCK_CMD_CLEAR_ERROR UINT32_C(0x00000002) #define RS_CLOCK_CMD_CLEAR_ERROR UINT32_C(0x00000002)
#define RS_CLOCK_STATUS_ACTIVE_MASK UINT32_C(0x00000007) #define RS_CLOCK_STATUS_ACTIVE_MASK UINT32_C(0x00000007)
#define RS_CLOCK_STATUS_ACTIVE_VALID UINT32_C(0x00000008) #define RS_CLOCK_STATUS_ACTIVE_VALID UINT32_C(0x00000008)
#define RS_CLOCK_STATUS_BUSY UINT32_C(0x00000010) #define RS_CLOCK_STATUS_BUSY UINT32_C(0x00000010)
#define RS_CLOCK_STATUS_ERROR_SHIFT 6U #define RS_CLOCK_STATUS_ERROR_SHIFT 6U
#define RS_CLOCK_STATUS_SAFE_CLOCK UINT32_C(0x00000100) #define RS_CLOCK_STATUS_SAFE_CLOCK UINT32_C(0x00000100)
#define RS_CLOCK_STATUS_PLL_LOCKED UINT32_C(0x00000200) #define RS_CLOCK_STATUS_PLL_LOCKED UINT32_C(0x00000200)
#define RS_CLOCK_STATUS_CAPABLE UINT32_C(0x00000400) #define RS_CLOCK_STATUS_CAPABLE UINT32_C(0x00000400)
#define RS_CLOCK_ERROR_UNSUPPORTED 1U #define RS_CLOCK_ERROR_UNSUPPORTED 1U
#define RS_CLOCK_ERROR_LOCK_TIMEOUT 2U #define RS_CLOCK_ERROR_LOCK_TIMEOUT 2U
static bool rs_clock_frequency_valid(rs_clock_frequency_t frequency) { static bool rs_clock_frequency_valid(rs_clock_frequency_t frequency) {
return (uint32_t)frequency <= (uint32_t)RS_CLOCK_FREQ_192MHZ; return (uint32_t)frequency <= (uint32_t)RS_CLOCK_FREQ_192MHZ;