feat: refactor UART implementation to support flow control and enhance functionality

- Removed UART files from clusterip and updated file lists accordingly.
- Added new UART flow control module and interface to manage RTS/CTS signals.
- Updated UART formal verification files to include new flow control signals.
- Modified UART testbench to validate flow control behavior and updated test cases.
- Adjusted top-level design to integrate new UART interface and signal connections.
- Enhanced GPIO pin mapping to accommodate new UART control signals.
- Updated linting and formal generation scripts to reflect changes in UART structure.

tests/test_uart.py

@@ -1,4 +1,4 @@
-"""UART V2 register, FIFO, framing, interrupt, and DMA request tests."""
+"""UART V3 register, FIFO, framing, flow-control, interrupt, and DMA tests."""
 
 from __future__ import annotations
 
@@ -11,7 +11,7 @@ from pathlib import Path
 ROOT = Path(__file__).resolve().parents[1]
 
 
-def test_uart_v2_register_fifo_loopback_and_errors(tmp_path: Path) -> None:
+def test_uart_v3_register_fifo_loopback_flow_control_and_errors(tmp_path: Path) -> None:
     iverilog = shutil.which("iverilog")
     vvp = shutil.which("vvp")
     if iverilog is None or vvp is None:
@@ -19,7 +19,6 @@ def test_uart_v2_register_fifo_loopback_and_errors(tmp_path: Path) -> None:
 
     common = ROOT / "rtl/managed/clusterip/common/rtl"
     serial = ROOT / "rtl/ip/ribp/serial"
-    cluster_uart = ROOT / "rtl/managed/clusterip/uart/rtl"
     source_list = tmp_path / "uart.fl"
     source_list.write_text(
         "\n".join(
@@ -27,15 +26,19 @@ def test_uart_v2_register_fifo_loopback_and_errors(tmp_path: Path) -> None:
                 "+define+SV_ASSRT_DISABLE",
                 f"+incdir+{common}",
                 f"+incdir+{common / 'interface'}",
+                f"+incdir+{common / 'cdc'}",
                 f"+incdir+{common / 'utils'}",
                 f"+incdir+{serial}",
                 str(common / "interface/ribp_if.sv"),
+                str(common / "cdc/cdc_sync.sv"),
                 str(common / "utils/register.sv"),
+                str(common / "utils/edge_det.sv"),
                 str(common / "utils/fifo.sv"),
-                str(cluster_uart / "uart_if.sv"),
+                str(serial / "uart_if.sv"),
                 str(serial / "uart_baudgen.sv"),
                 str(serial / "ribp_uart_tx.sv"),
                 str(serial / "ribp_uart_rx.sv"),
+                str(serial / "uart_flow_ctrl.sv"),
                 str(serial / "uart_core.sv"),
                 str(serial / "uart_reg.sv"),
                 str(serial / "ribp_uart.sv"),
@@ -63,4 +66,4 @@ def test_uart_v2_register_fifo_loopback_and_errors(tmp_path: Path) -> None:
         check=True,
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
-    assert "UART V2 register, FIFO, loopback, error, interrupt, and DMA test passed" in result.stdout
+    assert "UART V3 register, FIFO, loopback, flow-control, interrupt, and DMA test passed" in result.stdout