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feat: Add IHP130 support and enhance power pin handling
- Updated filelist to include sg13g2_udp.v for IHP130. - Modified sdram_axi4.sv to initialize read and write control signals. - Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad. - Updated iverilog.mk to support IHP130 in tech-cell-test. - Enhanced pin_map generation to include power pads for IHP130. - Updated tc_io modules to handle power pins for IHP130. - Added timing contract generation in package.py for commercial flow. - Enhanced test cases to validate new IHP130 features and configurations. - Added new tests for LibreLane flow specific to IHP130.
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@@ -1,6 +1,13 @@
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`timescale 1ns / 1ps
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module tc_pdk_cells_tb;
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`ifdef USE_POWER_PINS
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wire iovdd = 1'b1;
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wire iovss = 1'b0;
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wire vdd = 1'b1;
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wire vss = 1'b0;
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`endif
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logic in_drive;
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logic in_drive_en;
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tri in_pad;
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@@ -112,16 +119,34 @@ module tc_pdk_cells_tb;
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assign full_pad = full_drive_en ? full_drive : 1'bz;
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tc_io_in_pad u_tc_io_in_pad (
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.pad(in_pad),
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.p2c(in_p2c)
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`ifdef USE_POWER_PINS
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.iovdd(iovdd),
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.iovss(iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (in_pad),
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.p2c (in_p2c)
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);
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tc_io_out_pad u_tc_io_out_pad (
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.pad(out_pad),
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.c2p(out_c2p)
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`ifdef USE_POWER_PINS
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.iovdd(iovdd),
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.iovss(iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (out_pad),
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.c2p (out_c2p)
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);
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tc_io_tri_pad u_tc_io_tri_pad (
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`ifdef USE_POWER_PINS
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.iovdd (iovdd),
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.iovss (iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (tri_pad),
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.c2p (tri_c2p),
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.c2p_en(tri_c2p_en),
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@@ -129,6 +154,12 @@ module tc_pdk_cells_tb;
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);
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tc_io_tri_schmitt_pad u_tc_io_tri_schmitt_pad (
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`ifdef USE_POWER_PINS
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.iovdd (iovdd),
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.iovss (iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (schmitt_pad),
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.c2p (schmitt_c2p),
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.c2p_en(schmitt_c2p_en),
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@@ -136,6 +167,12 @@ module tc_pdk_cells_tb;
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);
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tc_io_tri_full_pad u_tc_io_tri_full_pad (
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`ifdef USE_POWER_PINS
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.iovdd (iovdd),
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.iovss (iovss),
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.vdd (vdd),
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.vss (vss),
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`endif
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.pad (full_pad),
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.c2p (full_c2p),
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.c2p_en(full_c2p_en),
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