feat: add RNG support and update related configurations

- Updated Makefile to include a check for the RNG metadata script and added a dependency for it.
- Modified memory_map.json to change the user access level of APB_RNG to 'none'.
- Updated clusterip filelist to include new RNG source files.
- Adjusted generate_soc_topology.py to replace the reserved IRQ with the RNG IRQ.
- Updated soc_topology.json to reflect the new RNG interrupt configuration.
- Added RNG source files to software.mk for compilation.
- Enhanced ip_apb_wrapper.sv to instantiate the RNG core and connect it to the APB interface.
- Updated test_memory_map.py to ensure SOC_ADDR_IS_APB_RNG is not defined.
- Modified test_script_tools.py to ensure dry runs do not write filelists.
- Updated test_soc_topology.py to verify the new RNG IRQ and adjust the user IRQ mask.

tests/test_memory_map.py

@@ -69,6 +69,10 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "SOC_SYSCTRL_TEST_STATUS_OFFSET  32'h00000084" in rtl
     assert "SOC_ADDR_IS_RIBP(addr)" in rtl
     assert "SOC_ADDR_IS_NMI" not in rtl
+    user_policy = rtl.split("`define SOC_USER_ADDR_READABLE", 1)[1].split(
+        "`define SOC_ADDR_INCR4_CAPABLE", 1
+    )[0]
+    assert "SOC_ADDR_IS_APB_RNG" not in user_policy
     assert "RS_SOC_SYSCTRL_PLL_CFG_OFFSET UINT32_C(0x00000008)" in header
     assert "RS_SOC_SYSCTRL_PLL_STATUS_OFFSET UINT32_C(0x0000001C)" in header
     assert "RS_SOC_SYSCTRL_TEST_STATUS_OFFSET UINT32_C(0x00000084)" in header

tests/test_script_tools.py

@@ -505,7 +505,7 @@ def test_dependency_helper_limits_recursive_submodules(monkeypatch, tmp_path: Pa
     )
 
 
-def test_make_dry_run_and_validation_do_not_write_filelists() -> None:
+def test_make_dry_run_and_validation_do_not_write_filelists(tmp_path: Path) -> None:
     def build_state() -> dict[str, tuple[int, int]]:
         build = ROOT / "build"
         if not build.exists():
@@ -518,7 +518,13 @@ def test_make_dry_run_and_validation_do_not_write_filelists() -> None:
 
     before = build_state()
     run("make", "-n", "help")
-    run("make", "-n", "SIMU=IVERILOG", "comp")
+    run(
+        "make",
+        "-n",
+        f"ARCHINFO_METADATA_SCRIPT={tmp_path / 'missing-generate-metadata.py'}",
+        "SIMU=IVERILOG",
+        "comp",
+    )
     run(
         "make",
         "-n",

tests/test_soc_topology.py

@@ -97,7 +97,7 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert ".apb_rib(u_apb_rib_if)" in bus_fabric
     assert ".rib(u_rib_if)" in bus_fabric
     assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
-    assert "`define SOC_USER_IRQ_MASK 32'h000FFFFC" in irq_config
+    assert "`define SOC_USER_IRQ_MASK 32'h000EFFFC" in irq_config
     assert "`define SOC_IRQ_RIBP_WIDTH 13" in irq_config
     assert "`define SOC_IRQ_APB_WIDTH 7" in irq_config
     assert "assign irq_o[0] = u_clint_if.software_irq_o[0];" in rib_irq
@@ -105,6 +105,7 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert "assign irq_o[11] = gpio.irq_o;" in rib_irq
     assert "assign irq_o[12] = i2c1.irq_o;" in rib_irq
     assert "assign irq_o[5] = u_tmr_if.irq_o;" in apb_irq
+    assert "assign irq_o[6] = s_rng_irq;" in apb_irq
     assert "s_irq[16] = s_apb_irq[6];" in irq_wiring
     assert "irq_i[31] == 1'b0" in irq_sva
     assert "bind retrosoc soc_irq_topology_sva" in irq_sva
@@ -141,7 +142,7 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
         ("rtc", "apb", 3, 13, "u_rtc_if.irq_o"),
         ("watchdog_reset", "apb", 4, 14, "u_wdg_if.rst_o"),
         ("advanced_timer", "apb", 5, 15, "u_tmr_if.irq_o"),
-        ("reserved", "apb", 6, 16, "1'b0"),
+        ("rng", "apb", 6, 16, "s_rng_irq"),
         ("ws2812", "ribp", 10, 17, "ws2812.irq_o"),
         ("gpio", "ribp", 11, 18, "gpio.irq_o"),
         ("i2c1", "ribp", 12, 19, "i2c1.irq_o"),