mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: refactor RIB interfaces and update test cases
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
This commit is contained in:
73 files changed
+673
-958
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+23
-24
@@ -11,10 +11,10 @@ module bus_fault_tb;
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logic [ 1:0] fault_master_o;
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logic [ 2:0] fault_code_o;
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logic user_bus_idle_o;
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soc_ribl_if mgmt_ribl ();
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soc_rib_if user_rib ();
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soc_rib_if dma_rib ();
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soc_rib_if rib ();
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ribp_if mgmt_ribp ();
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rib_if user_rib ();
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rib_if dma_rib ();
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rib_if rib ();
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ribp_if apb_ribp ();
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always #5 clk_i = ~clk_i;
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@@ -24,7 +24,7 @@ module bus_fault_tb;
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assign rib.rsp_valid = 1'b0;
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assign rib.rdata = 32'hCAFE_BABE;
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assign rib.resp_err = 1'b0;
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assign rib.resp_code = `SOC_RIB_RESP_OK;
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assign rib.resp_code = `RIB_RESP_OK;
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assign rib.rsp_beat = '0;
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assign rib.rsp_last = 1'b0;
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assign apb_ribp.ready = 1'b1;
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@@ -33,14 +33,13 @@ module bus_fault_tb;
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bus u_bus (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.mgmt_ribl (mgmt_ribl),
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.mgmt_ribp (mgmt_ribp),
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.user_rib (user_rib),
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.dma_rib (dma_rib),
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.user_bus_enable_i(1'b1),
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.user_bus_idle_o (user_bus_idle_o),
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.rib (rib),
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.apb_ribp (apb_ribp),
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.apb_resp_err_i (1'b0),
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.perf_enable_i (1'b0),
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.perf_clear_i (1'b0),
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.fault_valid_o (fault_valid_o),
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@@ -56,22 +55,22 @@ module bus_fault_tb;
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input logic reserved, input logic [2:0] expected_code);
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begin
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@(negedge clk_i);
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mgmt_ribl.addr = address;
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mgmt_ribl.wdata = 32'hA5A5_5A5A;
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mgmt_ribl.wstrb = write_strobes;
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mgmt_ribl.valid = 1'b1;
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mgmt_ribp.addr = address;
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mgmt_ribp.wdata = 32'hA5A5_5A5A;
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mgmt_ribp.wstrb = write_strobes;
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mgmt_ribp.valid = 1'b1;
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while (!fault_valid_o) @(posedge clk_i);
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if (fault_addr_o !== address || fault_wstrb_o !== write_strobes ||
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fault_reserved_o !== reserved || fault_access_o || fault_code_o !== expected_code ||
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rib.cmd_valid || apb_ribp.valid) begin
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$fatal(1, "unexpected fault response for address %h", address);
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end
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while (!mgmt_ribl.ready) @(posedge clk_i);
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if (mgmt_ribl.rdata !== 32'd0 || !mgmt_ribl.resp_err) begin
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while (!mgmt_ribp.ready) @(posedge clk_i);
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if (mgmt_ribp.rdata !== 32'd0 || !mgmt_ribp.resp_err) begin
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$fatal(1, "fault response data must be zero");
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end
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@(negedge clk_i);
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mgmt_ribl.valid = 1'b0;
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mgmt_ribp.valid = 1'b0;
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while (fault_valid_o) @(posedge clk_i);
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end
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endtask
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@@ -81,7 +80,7 @@ module bus_fault_tb;
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@(negedge clk_i);
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user_rib.cmd_addr = address;
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user_rib.cmd_write = |write_strobes;
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user_rib.cmd_len = `SOC_RIB_LEN_INCR1;
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user_rib.cmd_len = `RIB_LEN_INCR1;
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user_rib.cmd_valid = 1'b1;
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while (!user_rib.cmd_ready) @(posedge clk_i);
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@(negedge clk_i);
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@@ -100,7 +99,7 @@ module bus_fault_tb;
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$fatal(1, "user access was not denied locally");
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end
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if (user_rib.rdata !== 32'd0 || !user_rib.resp_err || !user_rib.rsp_last ||
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user_rib.resp_code !== `SOC_RIB_RESP_PROTERR) begin
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user_rib.resp_code !== `RIB_RESP_PROTERR) begin
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$fatal(1, "denied user response data must be zero");
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end
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while (fault_valid_o) @(posedge clk_i);
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@@ -108,14 +107,14 @@ module bus_fault_tb;
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endtask
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initial begin
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mgmt_ribl.valid = 1'b0;
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mgmt_ribl.addr = '0;
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mgmt_ribl.wdata = '0;
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mgmt_ribl.wstrb = '0;
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mgmt_ribp.valid = 1'b0;
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mgmt_ribp.addr = '0;
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mgmt_ribp.wdata = '0;
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mgmt_ribp.wstrb = '0;
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user_rib.cmd_valid = 1'b0;
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user_rib.cmd_addr = '0;
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user_rib.cmd_write = 1'b0;
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user_rib.cmd_len = `SOC_RIB_LEN_INCR1;
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user_rib.cmd_len = `RIB_LEN_INCR1;
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user_rib.w_valid = 1'b0;
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user_rib.wdata = '0;
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user_rib.wstrb = '0;
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@@ -124,7 +123,7 @@ module bus_fault_tb;
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dma_rib.cmd_valid = 1'b0;
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dma_rib.cmd_addr = '0;
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dma_rib.cmd_write = 1'b0;
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dma_rib.cmd_len = `SOC_RIB_LEN_INCR1;
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dma_rib.cmd_len = `RIB_LEN_INCR1;
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dma_rib.w_valid = 1'b0;
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dma_rib.wdata = '0;
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dma_rib.wstrb = '0;
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@@ -134,8 +133,8 @@ module bus_fault_tb;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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expect_fault(32'h1000_F000, 4'hF, 1'b1, `SOC_RIB_RESP_RESERVED);
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expect_fault(32'hA000_0000, 4'h0, 1'b0, `SOC_RIB_RESP_DECERR);
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expect_fault(32'h1000_F000, 4'hF, 1'b1, `RIB_RESP_RESERVED);
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expect_fault(32'hA000_0000, 4'h0, 1'b0, `RIB_RESP_DECERR);
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expect_user_denied(32'h1000_B000, 4'hF);
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$display("bus fault responder test passed");
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$finish;
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@@ -33,7 +33,7 @@ module dma_error_tb;
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logic model_write_q = 1'b0;
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logic model_error_q = 1'b0;
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dma_hw_trg_if hw_trg ();
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soc_rib_if rib ();
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rib_if rib ();
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always #5 clk_i = ~clk_i;
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@@ -42,7 +42,7 @@ module dma_error_tb;
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assign rib.rsp_valid = model_state_q == MODEL_RESP;
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assign rib.rdata = 32'hA5A5_5A5A + model_beat_q;
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assign rib.resp_err = model_error_q;
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assign rib.resp_code = model_error_q ? `SOC_RIB_RESP_DECERR : `SOC_RIB_RESP_OK;
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assign rib.resp_code = model_error_q ? `RIB_RESP_DECERR : `RIB_RESP_OK;
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assign rib.rsp_beat = model_beat_q;
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assign rib.rsp_last = model_write_q || model_error_q || (model_beat_q == model_len_q);
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@@ -63,10 +63,10 @@ module dma_error_tb;
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model_write_q <= rib.cmd_write;
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model_error_q <= error_mode && !rib.cmd_write;
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model_state_q <= rib.cmd_write ? MODEL_WDATA : MODEL_RESP;
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if (rib.cmd_len == `SOC_RIB_LEN_INCR4 && rib.cmd_write) begin
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if (rib.cmd_len == `RIB_LEN_INCR4 && rib.cmd_write) begin
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incr4_write_count <= incr4_write_count + 1;
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end
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if (rib.cmd_len == `SOC_RIB_LEN_INCR4 && !rib.cmd_write) begin
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if (rib.cmd_len == `RIB_LEN_INCR4 && !rib.cmd_write) begin
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incr4_read_count <= incr4_read_count + 1;
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end
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end
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@@ -157,7 +157,7 @@ module dma_error_tb;
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start_transfer();
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wait (error_o);
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@(negedge clk_i);
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if (error_code_o !== `SOC_RIB_RESP_DECERR || error_addr_o !== srcaddr_i) begin
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if (error_code_o !== `RIB_RESP_DECERR || error_addr_o !== srcaddr_i) begin
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$fatal(1, "DMA error response was not propagated");
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end
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if (write_count != 1) begin
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@@ -1,12 +1,12 @@
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`timescale 1ns / 1ps
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module soc_rib2ram_tb;
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module rib2ram_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [31:0] memory [0:31];
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logic [31:0] expected [ 0:3];
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integer index;
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soc_rib_if rib ();
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rib_if rib ();
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ram_if ram ();
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always #5 clk_i = ~clk_i;
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@@ -19,7 +19,7 @@ module soc_rib2ram_tb;
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if (ram.wstrb[3]) memory[ram.addr][31:24] <= ram.wdata[31:24];
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end
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soc_rib2ram u_dut (
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rib2ram u_dut (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.rib (rib),
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@@ -31,7 +31,7 @@ module soc_rib2ram_tb;
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@(negedge clk_i);
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rib.cmd_addr = 32'h3000_0000;
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rib.cmd_write = write;
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rib.cmd_len = `SOC_RIB_LEN_INCR4;
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rib.cmd_len = `RIB_LEN_INCR4;
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rib.cmd_valid = 1'b1;
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while (!rib.cmd_ready) @(posedge clk_i);
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@(negedge clk_i);
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+15
-16
@@ -16,10 +16,10 @@ module rib_bus_tb;
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logic fault_valid_o;
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logic [2:0] fault_code_o;
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logic user_bus_idle_o;
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soc_ribl_if mgmt_ribl ();
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soc_rib_if user_rib ();
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soc_rib_if dma_rib ();
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soc_rib_if rib ();
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ribp_if mgmt_ribp ();
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rib_if user_rib ();
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rib_if dma_rib ();
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rib_if rib ();
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ribp_if apb_ribp ();
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always #5 clk_i = ~clk_i;
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@@ -30,7 +30,7 @@ module rib_bus_tb;
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assign rib.rsp_valid = target_state_q == TARGET_RESP;
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assign rib.rdata = 32'hCAFE_0000 + target_beat_q;
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assign rib.resp_err = 1'b0;
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assign rib.resp_code = `SOC_RIB_RESP_OK;
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assign rib.resp_code = `RIB_RESP_OK;
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assign rib.rsp_beat = target_beat_q;
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assign rib.rsp_last = target_beat_q == target_len_q;
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@@ -63,14 +63,13 @@ module rib_bus_tb;
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bus u_bus (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.mgmt_ribl (mgmt_ribl),
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.mgmt_ribp (mgmt_ribp),
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.user_rib (user_rib),
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.dma_rib (dma_rib),
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.user_bus_enable_i(1'b1),
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.user_bus_idle_o (user_bus_idle_o),
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.rib (rib),
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.apb_ribp (apb_ribp),
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.apb_resp_err_i (1'b0),
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.perf_enable_i (1'b0),
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.perf_clear_i (1'b0),
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.fault_valid_o (fault_valid_o),
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@@ -109,7 +108,7 @@ module rib_bus_tb;
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$fatal(1, "unexpected response status for %h", address);
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end
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if (expect_error) begin
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if (dma_rib.resp_code !== `SOC_RIB_RESP_BURSTERR || !dma_rib.rsp_last) begin
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if (dma_rib.resp_code !== `RIB_RESP_BURSTERR || !dma_rib.rsp_last) begin
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$fatal(1, "illegal burst did not return terminal BURSTERR");
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end
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response_count = length + 1;
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@@ -130,10 +129,10 @@ module rib_bus_tb;
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endtask
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initial begin
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mgmt_ribl.valid = 1'b0;
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mgmt_ribl.addr = '0;
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mgmt_ribl.wdata = '0;
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mgmt_ribl.wstrb = '0;
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mgmt_ribp.valid = 1'b0;
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mgmt_ribp.addr = '0;
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mgmt_ribp.wdata = '0;
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mgmt_ribp.wstrb = '0;
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user_rib.cmd_valid = 1'b0;
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user_rib.cmd_addr = '0;
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user_rib.cmd_write = 1'b0;
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@@ -156,13 +155,13 @@ module rib_bus_tb;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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issue_read(32'h3800_1000, `SOC_RIB_LEN_INCR4, 1'b0);
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issue_read(32'h3800_1000, `RIB_LEN_INCR4, 1'b0);
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if (rib_command_count != 1) begin
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$fatal(1, "INCR4 was split before reaching the burst RIB target");
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end
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issue_read(32'h3800_1004, `SOC_RIB_LEN_INCR4, 1'b1);
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issue_read(32'h1000_0000, `SOC_RIB_LEN_INCR4, 1'b1);
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issue_read(32'h2000_0000, `SOC_RIB_LEN_INCR4, 1'b1);
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issue_read(32'h3800_1004, `RIB_LEN_INCR4, 1'b1);
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issue_read(32'h1000_0000, `RIB_LEN_INCR4, 1'b1);
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issue_read(32'h2000_0000, `RIB_LEN_INCR4, 1'b1);
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issue_read(32'h3800_1000, 2'd2, 1'b1);
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if (rib_command_count != 1 || apb_ribp.valid) begin
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$fatal(1, "illegal burst reached a downstream target");
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@@ -2,13 +2,13 @@
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`include "mmap_define.svh"
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module soc_topology_ribp_tb;
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module ribp_topology_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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ribp_if ribp ();
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`include "soc_ribp_interfaces.svh"
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`include "soc_ribp_routes.svh"
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`include "ribp_interfaces.svh"
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`include "ribp_routes.svh"
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always #5 clk_i = ~clk_i;
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@@ -53,6 +53,26 @@ module soc_topology_ribp_tb;
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end
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endtask
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task automatic expect_error_route(input logic [31:0] address, input integer slot);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.valid = 1'b1;
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#1;
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if (s_slv_sel_d !== (18'd1 << slot)) begin
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$fatal(1, "unexpected error target slot for %h", address);
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end
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@(posedge clk_i);
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#1;
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if (!ribp.ready || !ribp.resp_err) begin
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$fatal(1, "error response was not propagated for %h", address);
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end
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@(negedge clk_i);
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ribp.valid = 1'b0;
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@(posedge clk_i);
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end
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endtask
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initial begin
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ribp.valid = 1'b0;
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ribp.addr = '0;
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@@ -97,6 +117,25 @@ module soc_topology_ribp_tb;
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u_opipsram_ribp_if.rdata = 32'h0F0F_0F0F;
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u_i2c1_ribp_if.rdata = 32'h1234_5678;
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u_uart_ribp_if.resp_err = 1'b0;
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u_gpio_ribp_if.resp_err = 1'b0;
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u_tim0_ribp_if.resp_err = 1'b0;
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u_tim1_ribp_if.resp_err = 1'b0;
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u_psram_ribp_if.resp_err = 1'b0;
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u_spisd_ribp_if.resp_err = 1'b0;
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u_i2c0_ribp_if.resp_err = 1'b0;
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u_i2s_ribp_if.resp_err = 1'b0;
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u_onewire_ribp_if.resp_err = 1'b0;
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u_xpi_ribp_if.resp_err = 1'b0;
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u_dma_ribp_if.resp_err = 1'b0;
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u_sysctrl_ribp_if.resp_err = 1'b0;
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u_clint_ribp_if.resp_err = 1'b0;
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u_sdram_ribp_if.resp_err = 1'b0;
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u_dvp_ribp_if.resp_err = 1'b0;
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u_sdio_ribp_if.resp_err = 1'b0;
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u_opipsram_ribp_if.resp_err = 1'b0;
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u_i2c1_ribp_if.resp_err = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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@@ -105,6 +144,9 @@ module soc_topology_ribp_tb;
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expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
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expect_route(`SOC_ADDR_RIBP_I2C1_BASE, 17, 32'h1234_5678);
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expect_disabled(`SOC_ADDR_RIBP_SDIO_BASE);
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u_gpio_ribp_if.resp_err = 1'b1;
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expect_error_route(`SOC_ADDR_RIBP_GPIO_BASE, 1);
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u_gpio_ribp_if.resp_err = 1'b0;
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$display("SoC topology RIBP routing test passed");
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$finish;
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@@ -63,7 +63,7 @@ module sysctrl_fault_tb;
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sysctrl.user_bus_idle_i = 1'b1;
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sysctrl.fault_access_i = 1'b0;
|
||||
sysctrl.fault_master_i = '0;
|
||||
sysctrl.fault_code_i = `SOC_RIB_RESP_RESERVED;
|
||||
sysctrl.fault_code_i = `RIB_RESP_RESERVED;
|
||||
sysctrl.perf_mgmt_wait_i = 64'd11;
|
||||
sysctrl.perf_user_wait_i = 64'd12;
|
||||
sysctrl.perf_dma_wait_i = 64'd13;
|
||||
@@ -98,10 +98,10 @@ module sysctrl_fault_tb;
|
||||
read_register(32'h1000_B018, read_data);
|
||||
if (read_data !== 32'h0000_0001) $fatal(1, "fault count was not incremented");
|
||||
read_register(32'h1000_B02C, read_data);
|
||||
if (read_data !== `SOC_RIB_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
|
||||
if (read_data !== `RIB_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
|
||||
|
||||
@(negedge clk_i);
|
||||
sysctrl.fault_code_i = `SOC_RIB_RESP_DECERR;
|
||||
sysctrl.fault_code_i = `RIB_RESP_DECERR;
|
||||
fault_valid_i = 1'b1;
|
||||
fault_addr_i = 32'hA000_0000;
|
||||
fault_wstrb_i = 4'h0;
|
||||
@@ -113,7 +113,7 @@ module sysctrl_fault_tb;
|
||||
read_register(32'h1000_B018, read_data);
|
||||
if (read_data !== 32'h0000_0002) $fatal(1, "later fault did not increment count");
|
||||
read_register(32'h1000_B02C, read_data);
|
||||
if (read_data !== `SOC_RIB_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
|
||||
if (read_data !== `RIB_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
|
||||
|
||||
write_register(32'h1000_B010, 32'h0000_0001);
|
||||
read_register(32'h1000_B010, read_data);
|
||||
|
||||
+1
-2
@@ -40,8 +40,7 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
f"+incdir+{ROOT / 'rtl/mini/top'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"),
|
||||
str(ROOT / "rtl/ip/ribp/peripheral/dma.sv"),
|
||||
|
||||
@@ -114,14 +114,13 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
|
||||
str(ROOT / "rtl/mini/top/ribp2rib.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib2ribp.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib_error_slave.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib2ram.sv"),
|
||||
str(ROOT / "rtl/mini/top/bus.sv"),
|
||||
str(ROOT / "tests/rtl/bus_fault_tb.sv"),
|
||||
"",
|
||||
@@ -173,7 +172,6 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
|
||||
f"+incdir+{ROOT / 'rtl/mini/top'}",
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
|
||||
str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
|
||||
@@ -222,7 +220,6 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
|
||||
f"+incdir+{ROOT / 'rtl/mini/top'}",
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"),
|
||||
|
||||
+12
-13
@@ -41,14 +41,13 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
|
||||
str(ROOT / "rtl/mini/top/ribp2rib.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib2ribp.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib_error_slave.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib2ram.sv"),
|
||||
str(ROOT / "rtl/mini/top/bus.sv"),
|
||||
str(ROOT / "tests/rtl/rib_bus_tb.sv"),
|
||||
"",
|
||||
@@ -83,7 +82,7 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
|
||||
if iverilog is None or vvp is None:
|
||||
return
|
||||
|
||||
source_list = tmp_path / "soc_rib2ram.fl"
|
||||
source_list = tmp_path / "rib2ram.fl"
|
||||
source_list.write_text(
|
||||
"\n".join(
|
||||
[
|
||||
@@ -91,17 +90,17 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
|
||||
f"+incdir+{ROOT / 'rtl/mini/top'}",
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
|
||||
str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
|
||||
str(ROOT / "tests/rtl/soc_rib2ram_tb.sv"),
|
||||
str(ROOT / "rtl/mini/top/rib2ram.sv"),
|
||||
str(ROOT / "tests/rtl/rib2ram_tb.sv"),
|
||||
"",
|
||||
]
|
||||
),
|
||||
encoding="utf-8",
|
||||
)
|
||||
converted = tmp_path / "soc_rib2ram_tb.v"
|
||||
converted = tmp_path / "rib2ram_tb.v"
|
||||
subprocess.run(
|
||||
[
|
||||
sys.executable,
|
||||
@@ -113,9 +112,9 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
|
||||
],
|
||||
check=True,
|
||||
)
|
||||
simulation = tmp_path / "soc_rib2ram_tb"
|
||||
simulation = tmp_path / "rib2ram_tb"
|
||||
subprocess.run(
|
||||
[iverilog, "-g2012", "-s", "soc_rib2ram_tb", "-o", str(simulation), str(converted)],
|
||||
[iverilog, "-g2012", "-s", "rib2ram_tb", "-o", str(simulation), str(converted)],
|
||||
check=True,
|
||||
)
|
||||
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
|
||||
|
||||
@@ -210,11 +210,11 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
|
||||
gpio_user = parse_filelists([gpio_user_filelist], require_files=False)
|
||||
assert "+define+SV_ASSRT_DISABLE" in bus.defines
|
||||
assert ROOT / "rtl/mini/top/bus.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/soc_rib_if.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/soc_ribl2rib.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/soc_rib_error_slave.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/rib_if.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/ribp2rib.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/rib_error_slave.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/formal/bus_formal.sv" in bus.files
|
||||
assert ROOT / "rtl/mini/top/soc_rib2ribp.sv" in rib_adapter.files
|
||||
assert ROOT / "rtl/mini/top/rib2ribp.sv" in rib_adapter.files
|
||||
assert ROOT / "rtl/mini/formal/rib_adapter_formal.sv" in rib_adapter.files
|
||||
assert ROOT / "rtl/ip/ribp/interconnect/ribp2apb.sv" in ribp2apb.files
|
||||
assert ROOT / "rtl/mini/formal/ribp2apb_formal.sv" in ribp2apb.files
|
||||
@@ -654,7 +654,7 @@ def test_management_core_selection_is_limited_to_hazard3_and_picorv32() -> None:
|
||||
assert "DEF_LIST += +define+CORE_$(CORE)" in makefile
|
||||
assert "`ifdef CORE_PICORV32" in wrapper
|
||||
assert "`elsif CORE_HAZARD3" in wrapper
|
||||
assert "ahbl2soc_ribl u_ahbl2soc_rib" in wrapper
|
||||
assert "ahbl2ribp u_ahbl2ribp" in wrapper
|
||||
assert ".RESET_VECTOR (`SOC_CPU_RESET_ADDR)" in wrapper
|
||||
|
||||
|
||||
|
||||
+14
-13
@@ -57,8 +57,8 @@ def write_invalid_topology(tmp_path: Path, document: dict[str, object]) -> Path:
|
||||
def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -> None:
|
||||
generate(tmp_path)
|
||||
|
||||
interfaces = (tmp_path / "rtl/soc_ribp_interfaces.svh").read_text(encoding="utf-8")
|
||||
routes = (tmp_path / "rtl/soc_ribp_routes.svh").read_text(encoding="utf-8")
|
||||
interfaces = (tmp_path / "rtl/ribp_interfaces.svh").read_text(encoding="utf-8")
|
||||
routes = (tmp_path / "rtl/ribp_routes.svh").read_text(encoding="utf-8")
|
||||
gpio = (tmp_path / "rtl/soc_gpio_alt_bindings.svh").read_text(encoding="utf-8")
|
||||
apb_interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
|
||||
apb_declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
|
||||
@@ -67,7 +67,7 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
|
||||
fabric = (tmp_path / "rtl/soc_fabric_interfaces.svh").read_text(encoding="utf-8")
|
||||
bus_fabric = (tmp_path / "rtl/soc_bus_fabric.svh").read_text(encoding="utf-8")
|
||||
irq_config = (tmp_path / "rtl/soc_irq_config.svh").read_text(encoding="utf-8")
|
||||
rib_irq = (tmp_path / "rtl/soc_ribp_irq_bindings.svh").read_text(encoding="utf-8")
|
||||
rib_irq = (tmp_path / "rtl/ribp_irq_bindings.svh").read_text(encoding="utf-8")
|
||||
apb_irq = (tmp_path / "rtl/soc_apb_irq_bindings.svh").read_text(encoding="utf-8")
|
||||
irq_wiring = (tmp_path / "rtl/soc_irq_wiring.svh").read_text(encoding="utf-8")
|
||||
irq_sva = (tmp_path / "rtl/soc_irq_sva.svh").read_text(encoding="utf-8")
|
||||
@@ -77,6 +77,8 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
|
||||
assert "nmi_if" not in interfaces
|
||||
assert "soc_nmi" not in interfaces
|
||||
assert "assign s_slv_sel_d[17] = u_i2c1_ribp_if.valid;" in routes
|
||||
assert "assign s_slv_resp_err[17] = u_i2c1_ribp_if.resp_err;" in routes
|
||||
assert "assign ribp.resp_err = |(s_slv_sel_q & s_slv_ready & s_slv_resp_err);" in routes
|
||||
assert "assign s_xpi_region_sel[1] = (ribp.addr <= `SOC_ADDR_FLASH_END);" in routes
|
||||
assert "assign u_sdio_ribp_if.valid = 1'b0;" in routes
|
||||
assert gpio.count("// GPIO") == 64
|
||||
@@ -87,10 +89,9 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
|
||||
assert "assign tmr.paddr = ribp.addr;" in apb_routes
|
||||
assert "({32{s_psel_q[8]}} & tmr.prdata)" in apb_response
|
||||
assert "localparam int NSLV = 10;" in apb_declarations
|
||||
assert fabric.count("soc_ribl_if u_") == 1
|
||||
assert fabric.count("soc_rib_if u_") == 3
|
||||
assert fabric.count("ribp_if u_") == 1
|
||||
assert ".mgmt_ribl(u_mgmt_ribl_if)" in bus_fabric
|
||||
assert fabric.count("ribp_if u_") == 2
|
||||
assert fabric.count("rib_if u_") == 3
|
||||
assert ".mgmt_ribp(u_mgmt_ribp_if)" in bus_fabric
|
||||
assert ".user_rib(u_user_rib_if)" in bus_fabric
|
||||
assert ".apb_ribp(u_apb_ribp_if)" in bus_fabric
|
||||
assert ".rib(u_rib_if)" in bus_fabric
|
||||
@@ -157,7 +158,7 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
|
||||
assert "apb4_pure_if user_ip ();" in formal_design
|
||||
assert ".user_ip (user_ip)" in formal_design
|
||||
assert "logic [ 9:0] psel_comb" in formal_design
|
||||
assert "wire [ 9:0] psel_comb" in formal_properties
|
||||
assert "wire [9:0] psel_comb" in formal_properties
|
||||
|
||||
|
||||
def test_topology_rejects_unknown_or_non_rib_regions(tmp_path: Path) -> None:
|
||||
@@ -317,7 +318,7 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
|
||||
topology_output = tmp_path / "topology"
|
||||
generate(topology_output)
|
||||
|
||||
source_list = tmp_path / "soc_topology_ribp.fl"
|
||||
source_list = tmp_path / "ribp_topology.fl"
|
||||
source_list.write_text(
|
||||
"\n".join(
|
||||
[
|
||||
@@ -327,13 +328,13 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
|
||||
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
|
||||
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
|
||||
str(ROOT / "tests/rtl/soc_topology_ribp_tb.sv"),
|
||||
str(ROOT / "tests/rtl/ribp_topology_tb.sv"),
|
||||
"",
|
||||
]
|
||||
),
|
||||
encoding="utf-8",
|
||||
)
|
||||
converted = tmp_path / "soc_topology_ribp_tb.v"
|
||||
converted = tmp_path / "ribp_topology_tb.v"
|
||||
subprocess.run(
|
||||
[
|
||||
sys.executable,
|
||||
@@ -345,13 +346,13 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
|
||||
],
|
||||
check=True,
|
||||
)
|
||||
simulation = tmp_path / "soc_topology_ribp_tb"
|
||||
simulation = tmp_path / "ribp_topology_tb"
|
||||
subprocess.run(
|
||||
[
|
||||
iverilog,
|
||||
"-g2012",
|
||||
"-s",
|
||||
"soc_topology_ribp_tb",
|
||||
"ribp_topology_tb",
|
||||
"-o",
|
||||
str(simulation),
|
||||
str(converted),
|
||||
|
||||
@@ -48,7 +48,7 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
|
||||
ip = (tmp_path / "rtl/user_ip_bindings.svh").read_text(encoding="utf-8")
|
||||
filelist = (tmp_path / "user_extensions.fl").read_text(encoding="utf-8")
|
||||
|
||||
assert core.count("soc_rib_if u_user_") == 6
|
||||
assert core.count("rib_if u_user_") == 6
|
||||
assert core.count("ribp_if u_user_") == 6
|
||||
assert core.count("ribp2rib #(") == 6
|
||||
assert core.count(".SYNC_RESET(1'b1)") == 2
|
||||
|
||||
Reference in new issue
Block a user