feat: add support for XEZIM and CVC simulator backends

- Updated the testbench  to conditionally include pull-up resistors and reset hold time based on the selected simulator.
- Enhanced the filelist generation script to support both XEZIM and CVC formats, allowing for simulator-specific options and exclusions.
- Introduced new makefiles ( and ) to handle compilation and simulation for the respective backends.
- Added external memory models and SRAM models specifically for XEZIM simulations.
- Created a test suite to validate the integration of optional simulator backends and ensure they do not interfere with the default backend.

scripts/README.md

@@ -13,6 +13,11 @@ entry point. It installs only the checksum-verified open-source tool bundles and
 hash-pinned Python dependencies; project-local PDK and source setup remains under
 the existing Make targets.
 
+The optional `XEZIM` and `CVC` simulator backends are intentionally not part of
+that locked installer. `scripts/doctor.py` checks them when `SIMU=XEZIM` or
+`SIMU=CVC` is selected and resolves the executable from the corresponding
+`XEZIM` or `CVC` environment variable.
+
 `publish_fatfs_artifact.sh` is the manual release helper for the lock-pinned
 FatFs R0.16 archive. It verifies the archive, GitHub authentication, release
 absence, and the published asset checksum before reporting the checksum-pinned

scripts/doctor.py

@@ -4,6 +4,7 @@ from __future__ import annotations
 
 import argparse
 import json
+import os
 import shutil
 import subprocess
 import sys
@@ -35,13 +36,17 @@ def version(executable: str) -> str | None:
     path = shutil.which(executable)
     if path is None:
         return None
+    name = Path(executable).name
     options = {
         "iverilog": "-V",
         "vvp": "-V",
         "sta": "-version",
+        "xezim": "-V",
+        "cvc": "-h",
+        "cvc64": "-h",
     }
     result = subprocess.run(
-        [executable, options.get(executable, "--version")],
+        [executable, options.get(name, "--version")],
         text=True,
         capture_output=True,
         check=False,
@@ -61,6 +66,10 @@ def main() -> int:
         tools.extend(("verilator", "c++"))
     elif args.simu == "VCS":
         tools.extend(("bsub", "vcs"))
+    elif args.simu == "XEZIM":
+        tools.append(os.environ.get("XEZIM", "xezim"))
+    elif args.simu == "CVC":
+        tools.append(os.environ.get("CVC", "cvc"))
     if args.synth == "YOSYS":
         tools.append("yosys")
     if args.sta == "OPENSTA":