feat: enhance DMA and RIB functionality with burst support and performance tests

- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers.
- Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance.
- Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands.
- Created spill_register_tb to verify the functionality of the spill register under various conditions.
- Modified test_dma.py to reflect changes in DMA error handling and performance reporting.
- Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities.
- Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior.
- Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces.
- Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.

tests/test_user_extensions.py

@@ -48,12 +48,17 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
     ip = (tmp_path / "rtl/user_ip_bindings.svh").read_text(encoding="utf-8")
     filelist = (tmp_path / "user_extensions.fl").read_text(encoding="utf-8")
 
+    assert core.count("soc_rib_burst_if u_user_") == 6
     assert core.count("rib_if u_user_") == 6
-    assert "rib.valid = '0;" in core
+    assert core.count("rib_legacy_to_burst #(") == 6
+    assert core.count(".SYNC_RESET(1'b1)") == 2
+    assert core.count(".SYNC_RESET(1'b0)") == 4
+    assert "rib.cmd_valid = '0;" in core
     assert "5'd0: begin" in core
     assert "5'd5: begin" in core
     assert "core_reset_i[0]" in core
     assert "user_core_design_username1 #(" in core
+    assert "User core 0 uses the legacy RIB contract" in core
     assert ip.count("user_gpio_if #(`USER_GPIO_NUM)") == 2
     assert "gpio.do_o = '0;" in ip
     assert "8'd2: begin" in ip
@@ -73,3 +78,11 @@ def test_extensions_reject_noncontiguous_slots_and_invalid_modules(tmp_path: Pat
     result = validate(write_invalid_extensions(tmp_path, document))
     assert result.returncode != 0
     assert "must be a SystemVerilog identifier" in result.stderr
+
+
+def test_extensions_reject_invalid_core_reset_style(tmp_path: Path) -> None:
+    document = json.loads(EXTENSIONS.read_text(encoding="utf-8"))
+    document["core_targets"][0]["reset"] = "mixed"
+    result = validate(write_invalid_extensions(tmp_path, document))
+    assert result.returncode != 0
+    assert ".reset must be sync or async" in result.stderr