feat: add RTC wake functionality and related integration

- Introduced  signal in sysctrl interface and module to handle RTC wake events.
- Added RTC wake status register in memory map and updated related tests.
- Integrated RTC wake handling in the APB wrapper and core wrapper.
- Enhanced clock and reset domain configurations to include RTC signals.
- Updated software build configurations to include RTC source files and headers.
- Modified formal verification and testbench files to accommodate RTC wake functionality.
- Ensured proper synchronization and status recording for RTC wake events in the sysctrl module.

tests/rtl/pll_ctrl_tb.sv

@@ -106,6 +106,7 @@ module pll_ctrl_tb;
     sysctrl.user_bus_idle_i = 1'b1;
     sysctrl.fault_access_i  = 1'b0;
     sysctrl.fault_master_i  = '0;
+    sysctrl.rtc_wake_i      = 1'b0;
     #100;
     rst_n_i = 1'b1;
     repeat (12) @(posedge sys_clk_o);

tests/rtl/sysctrl_fault_tb.sv

@@ -72,6 +72,7 @@ module sysctrl_fault_tb;
     sysctrl.perf_sdram_wait_i   = 64'd16;
     sysctrl.perf_psram_wait_i   = 64'd17;
     sysctrl.perf_flash_wait_i   = 64'd18;
+    sysctrl.rtc_wake_i          = 1'b0;
     pll_ctrl.req_ready_i        = 1'b1;
     pll_ctrl.rsp_active_sel_i   = '0;
     pll_ctrl.rsp_active_valid_i = 1'b0;
@@ -163,7 +164,29 @@ module sysctrl_fault_tb;
       $fatal(1, "terminal test status was overwritten");
     end
 
-    $display("sysctrl fault and user core control test passed");
+    read_register(32'h1000_B088, read_data);
+    if (read_data !== 32'h0000_0000) begin
+      $fatal(1, "RTC wake status did not reset");
+    end
+    sysctrl.rtc_wake_i = 1'b1;
+    repeat (4) @(posedge clk_i);
+    read_register(32'h1000_B088, read_data);
+    if (read_data !== 32'h0000_0003) begin
+      $fatal(1, "RTC wake live and sticky status was not recorded");
+    end
+    sysctrl.rtc_wake_i = 1'b0;
+    repeat (4) @(posedge clk_i);
+    read_register(32'h1000_B088, read_data);
+    if (read_data !== 32'h0000_0002) begin
+      $fatal(1, "RTC wake sticky status was not retained");
+    end
+    write_register(32'h1000_B088, 32'h0000_0002);
+    read_register(32'h1000_B088, read_data);
+    if (read_data !== 32'h0000_0000) begin
+      $fatal(1, "RTC wake sticky status W1C failed");
+    end
+
+    $display("sysctrl fault, user core control, and RTC wake test passed");
     $finish;
   end
 endmodule

tests/test_clock_reset_domains.py

@@ -3,6 +3,7 @@
 from __future__ import annotations
 
 import json
+import math
 import subprocess
 import sys
 from pathlib import Path
@@ -50,6 +51,19 @@ def test_clock_reset_domain_inventory_matches_the_rcu() -> None:
         crossing for crossing in document["crossings"] if crossing["name"] == "clint_timebase"
     )
     assert clint["primitive"] == "edge_det"
+    assert {
+        "rtc_command",
+        "rtc_response",
+        "rtc_event",
+        "rtc_status",
+        "rtc_interrupt_enable",
+        "rtc_wake_enable",
+        "rtc_wake_status",
+    } <= {crossing["name"] for crossing in document["crossings"]}
+    audio = next(domain for domain in document["domains"] if domain["name"] == "audio")
+    assert math.isclose(audio["sta"]["period_ns"], 1_000_000_000 / 18_432_000)
+    for profile in (ROOT / "configs").rglob("*.mk"):
+        assert "AUD_CLK_HZ" in profile.read_text(encoding="utf-8")
 
 
 def test_clock_reset_domain_inventory_rejects_unknown_domain_and_instance(tmp_path: Path) -> None:

tests/test_memory_map.py

@@ -67,6 +67,7 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "SOC_SYSCTRL_PLL_CFG_OFFSET      32'h00000008" in rtl
     assert "SOC_SYSCTRL_PLL_STATUS_OFFSET   32'h0000001C" in rtl
     assert "SOC_SYSCTRL_TEST_STATUS_OFFSET  32'h00000084" in rtl
+    assert "SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET 32'h00000088" in rtl
     assert "SOC_ADDR_IS_RIBP(addr)" in rtl
     assert "SOC_ADDR_IS_NMI" not in rtl
     user_policy = rtl.split("`define SOC_USER_ADDR_READABLE", 1)[1].split(
@@ -76,6 +77,7 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "RS_SOC_SYSCTRL_PLL_CFG_OFFSET UINT32_C(0x00000008)" in header
     assert "RS_SOC_SYSCTRL_PLL_STATUS_OFFSET UINT32_C(0x0000001C)" in header
     assert "RS_SOC_SYSCTRL_TEST_STATUS_OFFSET UINT32_C(0x00000084)" in header
+    assert "RS_SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET UINT32_C(0x00000088)" in header
     assert "PSRAM (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 0x00800000" in linker
 
 
@@ -192,6 +194,7 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
                 f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
                 str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
+                str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
                 str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
                 str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
                 str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"),
@@ -218,7 +221,7 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
         check=True,
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
-    assert "sysctrl fault and user core control test passed" in result.stdout
+    assert "sysctrl fault, user core control, and RTC wake test passed" in result.stdout
 
 
 def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: Path) -> None: