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https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
feat: refactor RTL code for improved readability and style compliance
- Updated multiple modules to enhance code formatting and readability by breaking long lines and aligning conditions. - Improved comments for clarity in , , and . - Added checks in to reject forbidden constructs such as , non-ASCII characters, and lines exceeding 100 characters. - Introduced unit tests to validate style checks for forbidden constructs and non-ASCII characters.
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@@ -18,6 +18,21 @@ INSTANCE_RE = re.compile(
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)
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LEGACY_ALWAYS_RE = re.compile(r"\balways\s*@")
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DECL_RE = re.compile(r"\b(?:wire|tri|wand|wor)\b")
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FORBIDDEN_TOKEN_RE = {
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"wildcard instance connection": re.compile(r"\.\*\s*\)"),
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"defparam": re.compile(r"\bdefparam\b"),
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"casex": re.compile(r"\bcasex\b"),
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"full_case pragma": re.compile(r"\bfull_case\b"),
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"parallel_case pragma": re.compile(r"\bparallel_case\b"),
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"synthesizable delay": re.compile(r"#\s*\d"),
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"task declaration": re.compile(r"\btask(?:\s+automatic)?\s+[A-Za-z_]"),
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"hierarchical reference": re.compile(r"\b[A-Za-z_]\w*(?:\.[A-Za-z_]\w*){2,}\b"),
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}
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UNNAMED_GENERATE_RE = re.compile(
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r"\bgenerate\b(?:(?!\bendgenerate\b).)*?"
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r"\b(?:if|for)\b(?:(?!\bbegin\b).)*?\bbegin\s*(?!:)",
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re.DOTALL,
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)
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LONG_LOCAL_RE = re.compile(
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r"\b[sr]_[A-Za-z0-9_$]*(?:command|request|response|address|enable|error|status|"
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r"counter|configuration|select|length)(?:_|$)"
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@@ -96,13 +111,36 @@ def check_file(path: Path, source: str, profile: str) -> list[str]:
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issues: list[str] = []
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if profile == "owned":
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issues.extend(instance_issues(path, source))
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format_disabled = False
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for number, line in enumerate(source.splitlines(), start=1):
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if LEGACY_ALWAYS_RE.search(line):
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code = line.split("//", 1)[0]
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if "verilog_format: off" in line:
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format_disabled = True
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format_exception = format_disabled
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if LEGACY_ALWAYS_RE.search(code):
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issues.append(f"{path}:{number}: use always_ff/always_comb in owned RTL")
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if re.search(r"\bwire\b", line) and not re.search(r"\binout\s+wire\b", line):
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if re.search(r"\bwire\b", code) and not re.search(r"\binout\s+wire\b", code):
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issues.append(f"{path}:{number}: explicit wire in owned RTL; justify net semantics")
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if LONG_LOCAL_RE.search(line) and not line.lstrip().startswith("//"):
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if LONG_LOCAL_RE.search(code):
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issues.append(f"{path}:{number}: prefer the local short-name abbreviation")
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if not format_exception:
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if any(character == "\t" for character in line):
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issues.append(f"{path}:{number}: tabs are not permitted in owned RTL")
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if line.rstrip() != line:
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issues.append(f"{path}:{number}: trailing whitespace")
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if any(ord(character) > 127 for character in line):
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issues.append(f"{path}:{number}: non-ASCII character")
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if len(line) > 100:
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issues.append(f"{path}:{number}: line exceeds 100 characters")
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for description, pattern in FORBIDDEN_TOKEN_RE.items():
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if pattern.search(code):
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issues.append(f"{path}:{number}: {description} is not permitted")
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if "verilog_format: on" in line:
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format_disabled = False
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if source and not source.endswith("\n"):
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issues.append(f"{path}: missing final newline")
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if UNNAMED_GENERATE_RE.search(source):
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issues.append(f"{path}: generated if/for block must have a label")
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return issues
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