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feate: add fabric monitor and enhance AXI4 data crossbar tests
- Introduced and its corresponding testbench to monitor fabric interactions. - Updated to include additional checks for ACL and QoS, enhancing the test coverage. - Modified to include the new fabric monitor file. - Created a new test file to validate the functionality of the fabric monitor. - Updated to integrate the fabric monitor interface. - Adjusted to reflect changes in the AXI4 data crossbar test output. - Enhanced to ensure proper generation of connections for the fabric monitor. - Updated user extension tests to account for new local SRAM and stream definitions.
This commit is contained in:
46 files changed
+2443
-1375
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@@ -17,6 +17,8 @@ module axi4_data_crossbar_tb;
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logic [31:0] fault_addr_o;
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logic fault_write_o;
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logic [ 3:0] fault_reason_o;
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logic recovery_i = 1'b0;
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logic [ 7:0] monitor_master_promotion_o;
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axi4_if #(
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.ADDR_WIDTH(32),
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@@ -44,29 +46,36 @@ module axi4_data_crossbar_tb;
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$fatal(1, "AXI4 data crossbar test timed out");
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end
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axi4_data_crossbar u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.block_new_i (1'b0),
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.master_block_i (master_block_i),
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.recovery_i (1'b0),
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.mem_pad_mode_i (2'd1),
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.ext_h_read_base_i (32'h3000_0000),
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.ext_h_read_limit_i (32'h4FFF_FFFF),
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.ext_h_write_base_i (32'h3000_0000),
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.ext_h_write_limit_i(32'h4FFF_FFFF),
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.masters (masters),
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.targets (targets),
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.idle_o (idle_o),
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.master_idle_o (master_idle_o),
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.outstanding_read_o (outstanding_read_o),
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.outstanding_write_o(outstanding_write_o),
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.fault_valid_o (fault_valid_o),
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.fault_master_o (fault_master_o),
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.fault_target_o (fault_target_o),
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.fault_addr_o (fault_addr_o),
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.fault_write_o (fault_write_o),
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.fault_reason_o (fault_reason_o)
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axi4_data_crossbar #(
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.StarvationCycles (4),
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.ReadTargetMask (40'b1111100000111111111111111111111111111111),
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.WriteTargetMask (40'b0111100000011110111101111011110111100000),
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.AllowInstruction (8'b00000001),
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.RequireNoncacheable(8'b11111100)
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) u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.block_new_i (1'b0),
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.master_block_i (master_block_i),
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.recovery_i (recovery_i),
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.mem_pad_mode_i (2'd1),
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.ext_h_read_base_i (32'h3000_0000),
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.ext_h_read_limit_i (32'h4FFF_FFFF),
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.ext_h_write_base_i (32'h3000_0000),
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.ext_h_write_limit_i (32'h4FFF_FFFF),
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.masters (masters),
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.targets (targets),
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.idle_o (idle_o),
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.master_idle_o (master_idle_o),
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.outstanding_read_o (outstanding_read_o),
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.outstanding_write_o (outstanding_write_o),
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.fault_valid_o (fault_valid_o),
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.fault_master_o (fault_master_o),
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.fault_target_o (fault_target_o),
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.fault_addr_o (fault_addr_o),
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.fault_write_o (fault_write_o),
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.fault_reason_o (fault_reason_o),
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.monitor_master_promotion_o(monitor_master_promotion_o)
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);
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task automatic issue_master1_read(input logic [5:0] id, input logic [31:0] addr);
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@@ -109,6 +118,19 @@ module axi4_data_crossbar_tb;
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end
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endtask
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task automatic return_target5_read(input logic [5:0] id);
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begin
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@(negedge clk_i);
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targets[5].rid = id;
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targets[5].rresp = 2'b10;
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targets[5].rlast = 1'b1;
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targets[5].rvalid = 1'b1;
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do @(posedge clk_i); while (!targets[5].rready);
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@(negedge clk_i);
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targets[5].rvalid = 1'b0;
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end
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endtask
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`define INIT_MASTER(index) \
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masters[index].awid = '0; \
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masters[index].awaddr = '0; \
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@@ -266,7 +288,123 @@ module axi4_data_crossbar_tb;
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@(negedge clk_i);
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targets[5].rvalid = 1'b0;
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$display("AXI4 data crossbar concurrency and ACL test passed");
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@(negedge clk_i);
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masters[2].arid = 6'b010_001;
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masters[2].araddr = 32'h3000_0000;
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masters[2].arcache = 4'b0011;
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masters[2].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[2].arready);
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#1;
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if (!fault_valid_o || (fault_master_o != 3'd2) || (fault_reason_o != 4'd3)) begin
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$fatal(1, "cache-attribute ACL fault attribution mismatch");
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end
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@(negedge clk_i);
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masters[2].arvalid = 1'b0;
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masters[2].arcache = 4'd0;
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return_target5_read(6'b010_001);
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@(negedge clk_i);
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masters[1].arid = 6'b001_100;
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masters[1].araddr = 32'h3000_0000;
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masters[1].arprot = 3'b100;
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masters[1].arvalid = 1'b1;
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do @(posedge clk_i); while (!masters[1].arready);
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#1;
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if (!fault_valid_o || (fault_master_o != 3'd1) || (fault_reason_o != 4'd3)) begin
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$fatal(1, "instruction ACL fault attribution mismatch");
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end
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@(negedge clk_i);
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masters[1].arvalid = 1'b0;
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masters[1].arprot = 3'd0;
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return_target5_read(6'b001_100);
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@(negedge clk_i);
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masters[1].awid = 6'b001_101;
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masters[1].awaddr = 32'h5000_0000;
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masters[1].awvalid = 1'b1;
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do @(posedge clk_i); while (!masters[1].awready);
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#1;
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if (!fault_valid_o || (fault_master_o != 3'd1) || (fault_reason_o != 4'd3) ||
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!fault_write_o) begin
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$fatal(1, "write-target ACL fault attribution mismatch");
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end
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@(negedge clk_i);
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masters[1].awvalid = 1'b0;
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masters[1].wdata = 64'hA5A5_5A5A_1122_3344;
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masters[1].wstrb = 8'hFF;
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masters[1].wvalid = 1'b1;
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do @(posedge clk_i); while (!masters[1].wready);
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@(negedge clk_i);
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masters[1].wvalid = 1'b0;
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targets[5].bid = 6'b001_101;
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targets[5].bresp = 2'b10;
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targets[5].bvalid = 1'b1;
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do @(posedge clk_i); while (!targets[5].bready);
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@(negedge clk_i);
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targets[5].bvalid = 1'b0;
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target0_recovery_priority : begin
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@(negedge clk_i);
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recovery_i = 1'b1;
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targets[0].arready = 1'b0;
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masters[0].arid = 6'b000_100;
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masters[0].araddr = 32'h3000_0100;
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masters[0].arvalid = 1'b1;
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masters[5].arid = 6'b101_000;
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masters[5].araddr = 32'h3000_0180;
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masters[5].arvalid = 1'b1;
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#1;
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if (!targets[0].arvalid || (targets[0].arid != 6'b101_000)) begin
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$fatal(1, "recovery master did not receive emergency priority");
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end
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targets[0].arready = 1'b1;
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do @(posedge clk_i); while (!masters[5].arready);
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@(negedge clk_i);
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masters[5].arvalid = 1'b0;
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do @(posedge clk_i); while (!masters[0].arready);
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@(negedge clk_i);
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masters[0].arvalid = 1'b0;
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recovery_i = 1'b0;
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return_target0_read(6'b101_000, 64'h5555_5555_5555_5555);
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return_target0_read(6'b000_100, 64'h0000_0000_0000_0100);
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end
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target0_starvation_bound : begin
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@(negedge clk_i);
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targets[0].arready = 1'b0;
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masters[5].arid = 6'b101_001;
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masters[5].araddr = 32'h3000_0200;
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masters[5].arvalid = 1'b1;
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repeat (4) @(posedge clk_i);
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@(negedge clk_i);
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masters[0].arid = 6'b000_101;
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masters[0].araddr = 32'h3000_0280;
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masters[0].arvalid = 1'b1;
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#1;
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if (!targets[0].arvalid || (targets[0].arid != 6'b101_001)) begin
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$fatal(1, "aged LP request did not override a newer latency request");
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end
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targets[0].arready = 1'b1;
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#1;
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if (!monitor_master_promotion_o[5]) begin
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$fatal(1, "aged LP service was not reported as a promotion");
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end
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do @(posedge clk_i); while (!masters[5].arready);
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@(negedge clk_i);
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masters[5].arvalid = 1'b0;
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do @(posedge clk_i); while (!masters[0].arready);
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@(negedge clk_i);
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masters[0].arvalid = 1'b0;
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return_target0_read(6'b101_001, 64'h5555_5555_0000_0200);
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return_target0_read(6'b000_101, 64'h0000_0000_0000_0280);
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end
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@(negedge clk_i);
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if (!idle_o || (outstanding_read_o != 8'd0) || (outstanding_write_o != 8'd0)) begin
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$fatal(1, "ACL and QoS transactions did not drain the crossbar");
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end
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$display("AXI4 data crossbar concurrency, ACL, and QoS test passed");
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$finish;
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end
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@@ -0,0 +1,189 @@
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`timescale 1ns / 1ps
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module fabric_monitor_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [ 7:0] master_read_accept_i = '0;
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logic [ 7:0] master_write_accept_i = '0;
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logic [ 7:0] master_read_beat_i = '0;
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logic [ 7:0] master_write_beat_i = '0;
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logic [ 7:0] master_wait_i = '0;
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logic [ 7:0] master_promotion_i = '0;
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logic [ 7:0][2:0] master_read_outstanding_i = '0;
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logic [ 7:0][2:0] master_write_outstanding_i = '0;
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logic [ 5:0] target_read_accept_i = '0;
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logic [ 5:0] target_write_accept_i = '0;
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logic [ 5:0] target_read_beat_i = '0;
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logic [ 5:0] target_write_beat_i = '0;
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logic [ 5:0] target_wait_i = '0;
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logic [ 5:0] target_timeout_i = '0;
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logic [ 5:0] target_isolated_i = '0;
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logic [ 5:0][2:0] target_read_outstanding_i = '0;
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logic [ 5:0][2:0] target_write_outstanding_i = '0;
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logic fault_valid_i = 1'b0;
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logic [31:0] read_data;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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fabric_monitor u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.idle_i (1'b0),
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.recovery_i (1'b1),
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.flush_busy_i (1'b0),
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.flush_i (target_timeout_i[5]),
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.outstanding_read_i (8'd2),
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.outstanding_write_i (8'd1),
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.fault_valid_i (fault_valid_i),
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.fault_master_i (3'd5),
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.fault_target_i (3'd2),
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.fault_addr_i (32'h4000_0040),
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.fault_write_i (1'b1),
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.fault_reason_i (4'd5),
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.master_read_accept_i (master_read_accept_i),
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.master_write_accept_i (master_write_accept_i),
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.master_read_beat_i (master_read_beat_i),
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.master_write_beat_i (master_write_beat_i),
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.master_wait_i (master_wait_i),
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.master_promotion_i (master_promotion_i),
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.master_read_outstanding_i (master_read_outstanding_i),
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.master_write_outstanding_i(master_write_outstanding_i),
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.target_read_accept_i (target_read_accept_i),
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.target_write_accept_i (target_write_accept_i),
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.target_read_beat_i (target_read_beat_i),
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.target_write_beat_i (target_write_beat_i),
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.target_wait_i (target_wait_i),
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.target_timeout_i (target_timeout_i),
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.target_isolated_i (target_isolated_i),
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.target_read_outstanding_i (target_read_outstanding_i),
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.target_write_outstanding_i(target_write_outstanding_i),
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.apb4 (apb4)
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);
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task automatic apb_write(input logic [11:0] offset, input logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = {20'd0, offset};
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apb4.pwrite = 1'b1;
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apb4.pwdata = data;
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apb4.pstrb = 4'hF;
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apb4.psel = 1'b1;
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apb4.penable = 1'b1;
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do @(posedge clk_i); while (!apb4.pready);
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if (apb4.pslverr) $fatal(1, "fabric monitor write failed at %h", offset);
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@(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic apb_read(input logic [11:0] offset, output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = {20'd0, offset};
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b1;
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do @(posedge clk_i); while (!apb4.pready);
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if (apb4.pslverr) $fatal(1, "fabric monitor read failed at %h", offset);
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data = apb4.prdata;
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@(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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initial begin
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apb4.paddr = '0;
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apb4.pprot = '0;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb_write(12'h00C, 32'h0000_0001);
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@(negedge clk_i);
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master_read_accept_i[0] = 1'b1;
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master_read_beat_i[0] = 1'b1;
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master_promotion_i[0] = 1'b1;
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master_read_outstanding_i[0] = 3'd3;
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target_read_accept_i[2] = 1'b1;
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target_read_beat_i[2] = 1'b1;
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target_read_outstanding_i[2] = 3'd2;
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@(negedge clk_i);
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master_read_accept_i = '0;
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master_read_beat_i = '0;
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master_promotion_i = '0;
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target_read_accept_i = '0;
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target_read_beat_i = '0;
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repeat (3) begin
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master_wait_i[0] = 1'b1;
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target_wait_i[2] = 1'b1;
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@(negedge clk_i);
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end
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master_wait_i = '0;
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target_wait_i = '0;
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target_timeout_i[2] = 1'b1;
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target_isolated_i[2] = 1'b1;
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fault_valid_i = 1'b1;
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@(negedge clk_i);
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target_timeout_i[2] = 1'b0;
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fault_valid_i = 1'b0;
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target_timeout_i[5] = 1'b1;
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@(negedge clk_i);
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target_timeout_i[5] = 1'b0;
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apb_write(12'h00C, 32'h0000_0009);
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apb_read(12'h100, read_data);
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if (read_data != 32'd1) $fatal(1, "master read request count mismatch");
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apb_read(12'h110, read_data);
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if (read_data != 32'd3) $fatal(1, "master wait count mismatch");
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apb_read(12'h114, read_data);
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if (read_data != 32'd3) $fatal(1, "master max wait mismatch");
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apb_read(12'h118, read_data);
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if (read_data != 32'd1) $fatal(1, "master promotion count mismatch");
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apb_read(12'h11C, read_data);
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if (read_data[2:0] != 3'd3) $fatal(1, "master high-water mismatch");
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apb_read(12'h340, read_data);
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if (read_data != 32'd1) $fatal(1, "target read request count mismatch");
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apb_read(12'h350, read_data);
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if (read_data != 32'd3) $fatal(1, "target wait count mismatch");
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apb_read(12'h354, read_data);
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if (read_data != 32'd1) $fatal(1, "target timeout count mismatch");
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||||
apb_read(12'h358, read_data);
|
||||
if (read_data != 32'd1) $fatal(1, "target isolation mismatch");
|
||||
apb_read(12'h01C, read_data);
|
||||
if (read_data != 32'd1) $fatal(1, "flush count mismatch");
|
||||
apb_read(12'h018, read_data);
|
||||
if (read_data != 32'h4000_0040) $fatal(1, "fault address mismatch");
|
||||
apb_read(12'h014, read_data);
|
||||
if (read_data != 32'h0000_0557) $fatal(1, "sticky fault attribution mismatch");
|
||||
apb_read(12'h020, read_data);
|
||||
if (read_data != 32'd1) $fatal(1, "fault count mismatch");
|
||||
|
||||
apb_write(12'h00C, 32'h0000_0005);
|
||||
apb_read(12'h100, read_data);
|
||||
if (read_data != 32'd0) $fatal(1, "snapshot did not clear");
|
||||
apb_read(12'h014, read_data);
|
||||
if (read_data != 32'd0) $fatal(1, "sticky fault did not clear");
|
||||
|
||||
$display("Fabric Monitor counter, snapshot, and clear test passed");
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
repeat (400) @(posedge clk_i);
|
||||
$fatal(1, "Fabric Monitor test timed out");
|
||||
end
|
||||
endmodule
|
||||
+52
-47
@@ -21,58 +21,63 @@ module rib2apb_tb;
|
||||
apb4_pure_if ext_l ();
|
||||
apb4_pure_if ext_h ();
|
||||
apb4_pure_if resource_ctrl ();
|
||||
apb4_pure_if fabric_monitor ();
|
||||
|
||||
always #5 clk_i = ~clk_i;
|
||||
|
||||
assign archinfo.pready = 1'b0;
|
||||
assign archinfo.prdata = '0;
|
||||
assign archinfo.pslverr = 1'b0;
|
||||
assign rng.pready = rng_ready;
|
||||
assign rng.prdata = rng_rdata;
|
||||
assign rng.pslverr = rng_slverr;
|
||||
assign pwm.pready = 1'b0;
|
||||
assign pwm.prdata = '0;
|
||||
assign pwm.pslverr = 1'b0;
|
||||
assign ps2.pready = 1'b0;
|
||||
assign ps2.prdata = '0;
|
||||
assign ps2.pslverr = 1'b0;
|
||||
assign rtc.pready = 1'b0;
|
||||
assign rtc.prdata = '0;
|
||||
assign rtc.pslverr = 1'b0;
|
||||
assign wdg.pready = 1'b0;
|
||||
assign wdg.prdata = '0;
|
||||
assign wdg.pslverr = 1'b0;
|
||||
assign crc.pready = 1'b0;
|
||||
assign crc.prdata = '0;
|
||||
assign crc.pslverr = 1'b0;
|
||||
assign user_ip.pready = 1'b0;
|
||||
assign user_ip.prdata = '0;
|
||||
assign user_ip.pslverr = 1'b0;
|
||||
assign ext_l.pready = 1'b0;
|
||||
assign ext_l.prdata = '0;
|
||||
assign ext_l.pslverr = 1'b0;
|
||||
assign ext_h.pready = 1'b0;
|
||||
assign ext_h.prdata = '0;
|
||||
assign ext_h.pslverr = 1'b0;
|
||||
assign resource_ctrl.pready = 1'b0;
|
||||
assign resource_ctrl.prdata = '0;
|
||||
assign resource_ctrl.pslverr = 1'b0;
|
||||
assign archinfo.pready = 1'b0;
|
||||
assign archinfo.prdata = '0;
|
||||
assign archinfo.pslverr = 1'b0;
|
||||
assign rng.pready = rng_ready;
|
||||
assign rng.prdata = rng_rdata;
|
||||
assign rng.pslverr = rng_slverr;
|
||||
assign pwm.pready = 1'b0;
|
||||
assign pwm.prdata = '0;
|
||||
assign pwm.pslverr = 1'b0;
|
||||
assign ps2.pready = 1'b0;
|
||||
assign ps2.prdata = '0;
|
||||
assign ps2.pslverr = 1'b0;
|
||||
assign rtc.pready = 1'b0;
|
||||
assign rtc.prdata = '0;
|
||||
assign rtc.pslverr = 1'b0;
|
||||
assign wdg.pready = 1'b0;
|
||||
assign wdg.prdata = '0;
|
||||
assign wdg.pslverr = 1'b0;
|
||||
assign crc.pready = 1'b0;
|
||||
assign crc.prdata = '0;
|
||||
assign crc.pslverr = 1'b0;
|
||||
assign user_ip.pready = 1'b0;
|
||||
assign user_ip.prdata = '0;
|
||||
assign user_ip.pslverr = 1'b0;
|
||||
assign ext_l.pready = 1'b0;
|
||||
assign ext_l.prdata = '0;
|
||||
assign ext_l.pslverr = 1'b0;
|
||||
assign ext_h.pready = 1'b0;
|
||||
assign ext_h.prdata = '0;
|
||||
assign ext_h.pslverr = 1'b0;
|
||||
assign resource_ctrl.pready = 1'b0;
|
||||
assign resource_ctrl.prdata = '0;
|
||||
assign resource_ctrl.pslverr = 1'b0;
|
||||
assign fabric_monitor.pready = 1'b0;
|
||||
assign fabric_monitor.prdata = '0;
|
||||
assign fabric_monitor.pslverr = 1'b0;
|
||||
|
||||
rib2apb u_rib2apb (
|
||||
.clk_i (clk_i),
|
||||
.rst_n_i (rst_n_i),
|
||||
.rib (rib),
|
||||
.archinfo (archinfo),
|
||||
.rng (rng),
|
||||
.pwm (pwm),
|
||||
.ps2 (ps2),
|
||||
.rtc (rtc),
|
||||
.wdg (wdg),
|
||||
.crc (crc),
|
||||
.user_ip (user_ip),
|
||||
.ext_l (ext_l),
|
||||
.ext_h (ext_h),
|
||||
.resource_ctrl(resource_ctrl)
|
||||
.clk_i (clk_i),
|
||||
.rst_n_i (rst_n_i),
|
||||
.rib (rib),
|
||||
.archinfo (archinfo),
|
||||
.rng (rng),
|
||||
.pwm (pwm),
|
||||
.ps2 (ps2),
|
||||
.rtc (rtc),
|
||||
.wdg (wdg),
|
||||
.crc (crc),
|
||||
.user_ip (user_ip),
|
||||
.ext_l (ext_l),
|
||||
.ext_h (ext_h),
|
||||
.resource_ctrl (resource_ctrl),
|
||||
.fabric_monitor(fabric_monitor)
|
||||
);
|
||||
|
||||
task automatic send_command(input logic [31:0] address, input logic write,
|
||||
|
||||
Reference in new issue
Block a user