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feat: add GPIO V2 support and related tests
- Updated to include for testing. - Modified to include GPIO header and added tests for GPIO functionality. - Created a new testbench for GPIO V2, covering register and pad-control contracts. - Removed obsolete and its associated test. - Updated to include GPIO admin base routing. - Added a new Python test for GPIO V2 register and pad-control contract. - Removed as its functionality is now covered in . - Updated memory map tests to ensure GPIO admin base is correctly referenced. - Adjusted formal filelist generation to reflect changes in GPIO handling. - Enhanced SOC topology tests to include GPIO interrupt handling.
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@@ -58,6 +58,8 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
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assert "RS_SOC_PSRAM_SIZE UINT32_C(0x00800000)" in header
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assert "RS_SOC_SDRAM_SIZE UINT32_C(0x02000000)" in header
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assert "RS_SOC_SPISD_SIZE UINT32_C(0x40000000)" in header
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assert "#ifdef __ASSEMBLER__" in header
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assert "#define UINT32_C(value) value" in header
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assert "RS_SOC_RIBP_SDIO_BASE" not in header
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assert "RS_SOC_NMI_" not in header
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assert "RS_SOC_OPIPSRAM_BASE" not in header
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@@ -83,6 +85,17 @@ def test_user_ip_is_always_emitted_for_the_fixed_platform(tmp_path: Path) -> Non
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assert "RS_SOC_APB_USER_IP_BASE" in header
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def test_bootstrap_assembly_uses_the_generated_gpio_admin_base() -> None:
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for source in (ROOT / "crt/arch/riscv/startup.S", ROOT / "app/asm/hello.s"):
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text = source.read_text(encoding="utf-8")
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assert '#include "retrosoc/generated/memory_map.h"' in text
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assert "RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x34" in text
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assert "RS_SOC_RIBP_GPIO_ADMIN_BASE + 0x38" in text
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assert "RS_SOC_RIBP_PSRAM_BASE + 0x08" in text
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assert "0x10000028" not in text
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assert "0x1000002c" not in text
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def test_map_validation_rejects_overlaps(tmp_path: Path) -> None:
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document = json.loads(MEMORY_MAP.read_text(encoding="utf-8"))
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document["regions"][1]["base"] = document["regions"][0]["base"]
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