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https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: enhance booter output, add reset hold time, and implement patching for serv state
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+132
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@@ -41,6 +41,7 @@ from scripts.development_environment import ( # noqa: E402
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from scripts.generate_mpw import render_active_manifest, validate_extension_bindings # noqa: E402
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from scripts.install_toolchain import safe_extract # noqa: E402
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from scripts.package import make_sbom # noqa: E402
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from scripts.prepare_mpw import patch_serv # noqa: E402
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from scripts import regress # noqa: E402
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from scripts import run_flow # noqa: E402
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from scripts.regress import ( # noqa: E402
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@@ -399,6 +400,34 @@ def test_mpw_generator_uses_only_the_native_v2_contract() -> None:
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assert '"generate"' in source
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def test_serv_setup_patch_is_idempotent(tmp_path: Path) -> None:
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state = tmp_path / "serv_state.v"
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state.write_text(
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"module serv_state;\n"
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" wire misalign_trap_sync;\n"
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" assign use_trap = !trap_pending;\n"
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" wire trap_pending = WITH_CSR & trap_condition;\n"
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"endmodule\n",
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encoding="utf-8",
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)
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patch_serv(tmp_path)
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first = state.read_text(encoding="utf-8")
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patch_serv(tmp_path)
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assert state.read_text(encoding="utf-8") == first
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assert first.index("wire trap_pending;") < first.index("!trap_pending")
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assert "assign trap_pending = WITH_CSR & trap_condition;" in first
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def test_serv_setup_patch_rejects_unknown_source(tmp_path: Path) -> None:
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state = tmp_path / "serv_state.v"
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state.write_text("module serv_state; endmodule\n", encoding="utf-8")
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with pytest.raises(RuntimeError, match="patch markers missing"):
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patch_serv(tmp_path)
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def test_mpw_active_manifest_uses_self_owned_design_selection(tmp_path: Path) -> None:
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manifest = tmp_path / "mpw.toml"
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manifest.write_text(
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@@ -830,6 +859,18 @@ def test_verilator_has_no_external_core_selection() -> None:
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assert "core_sel_i" not in testbench
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def test_systemverilog_testbench_starts_in_reset_with_known_clocks() -> None:
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testbench = (ROOT / "rtl/mini/dv/tb/retrosoc_tb.sv").read_text(encoding="utf-8")
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assert "localparam time ResetHoldTime = 170744ns;" in testbench
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for clock in ("r_ext_clk", "r_aud_clk", "r_xtal_clk"):
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assert f"{clock} = 1'b0;" in testbench
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assert f"{clock} = ~{clock};" in testbench
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assert testbench.index("r_rst_n = 1'b0;") < testbench.index("#ResetHoldTime;")
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assert testbench.index("#ResetHoldTime;") < testbench.index("r_rst_n = 1'b1;")
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assert "#43;" not in testbench
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def test_management_core_is_fixed_to_hazard3_with_debug() -> None:
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wrapper = (ROOT / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8")
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makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
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