feat: add watchdog (wdg) module integration and update related components

- Updated file lists to include new watchdog RTL files in clusterip.
- Replaced async_reqack source in commonip file list with top-level CDC file.
- Modified clock and reset domain configurations to incorporate watchdog reset signals.
- Updated the SoC topology generation script and JSON to reflect changes in watchdog interrupt handling.
- Added watchdog source files to software makefile for compilation.
- Enhanced APB wrapper to connect watchdog reset request signal.
- Updated RCU module to handle watchdog reset requests.
- Modified testbench to validate watchdog reset functionality.
- Updated test cases to reflect changes in interrupt naming conventions for the watchdog.

tests/rtl/pll_ctrl_tb.sv

@@ -5,6 +5,7 @@ module pll_ctrl_tb;
   logic        xtal_clk_i = 1'b0;
   logic        aud_clk_i = 1'b0;
   logic        rst_n_i = 1'b0;
+  logic        wdg_reset_req_i = 1'b0;
   logic        fault_valid_i = 1'b0;
   logic [31:0] fault_addr_i = '0;
   logic [ 3:0] fault_wstrb_i = '0;
@@ -28,6 +29,7 @@ module pll_ctrl_tb;
       .ext_clk_i      (ext_clk_i),
       .aud_clk_i      (aud_clk_i),
       .ext_rst_n_i    (rst_n_i),
+      .wdg_reset_req_i(wdg_reset_req_i),
 `ifdef HAVE_PLL
       .xtal_clk_i     (xtal_clk_i),
 `endif
@@ -109,8 +111,20 @@ module pll_ctrl_tb;
     sysctrl.rtc_wake_i      = 1'b0;
     #100;
     rst_n_i = 1'b1;
+    wait (aud_rst_n_o);
     repeat (12) @(posedge sys_clk_o);
 
+    wdg_reset_req_i = 1'b1;
+    #1;
+    if (sys_rst_n_o || !aud_rst_n_o) begin
+      $fatal(1, "watchdog reset did not isolate system and audio reset domains");
+    end
+    wdg_reset_req_i = 1'b0;
+    repeat (8) @(posedge sys_clk_o);
+    if (!sys_rst_n_o || !aud_rst_n_o) begin
+      $fatal(1, "watchdog system reset did not deassert synchronously");
+    end
+
     read_register(32'h1000_B01C, read_data);
 `ifdef HAVE_PLL
     if (read_data !== 32'h0000_0500) begin