feat: add formal verification properties for DMA design and corresponding testbench

- Introduced  to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created  as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added  to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.

docs/axi4-stream.md

@@ -8,8 +8,10 @@ to DMA. UART, I2C, and WS2812 retain their existing APB4 FIFO data registers.
 ## Interface Contract
 
 All three links use `DATA_WIDTH=32`, one-bit ID, destination, and user fields,
-and the system clock/reset. `TKEEP` and `TSTRB` are `4'hF`; the current I2S and
-DVP data paths always transfer complete words. DMA holds `TDATA`, `TKEEP`,
+and the system clock/reset. I2S uses `TKEEP/TSTRB=4'hF`; DVP can mark an
+odd-pixel line's final partial word. The DMA MVP accepts only full
+`TKEEP=4'hF` words and reports a stream error for a partial DVP beat. DMA holds
+`TDATA`, `TKEEP`,
 `TSTRB`, and `TLAST` stable while `TVALID` is high and `TREADY` is low. A word
 is consumed only on a `TVALID && TREADY` clock edge.
 
@@ -30,16 +32,17 @@ DVP register offset `0x0C` is `STREAM_CTRL`: bit 0 selects AXI4-Stream as the
 RX FIFO consumer. When clear, reads of `RXDATA` retain the existing pop
 behavior. When set, `RXDATA` reads do not pop the FIFO.
 
-DMA modes 1 and 2 use the I2S TX and RX stream links. Mode 11 uses DVP RX. The
-source address is unused for stream RX modes, and the destination address is
-unused for I2S TX, but the current software API still requires valid nonzero
-addresses for a uniform descriptor contract. DMA writes received stream words
-to AXI4 memory and reads I2S TX words from AXI4 memory.
+The DMA direct-mode request selectors `I2S_TX`, `I2S_RX`, and `DVP_RX` use the
+I2S TX/RX and DVP RX stream links. The source address is unused for stream RX
+and the destination address is unused for I2S TX. The channel-aware SDK uses
+zero for these unused fields rather than inventing a fake MMIO address. DMA
+writes received stream words to AXI4 memory and reads I2S TX words from AXI4
+memory.
 
 ## Verification Boundary
 
-The DMA directed test covers stream TX backpressure, two-word stream RX to
-memory, exact transfer length, bus errors, and retained RIB burst behavior. The
-I2S and DVP FIFO tests continue to cover PIO mode. Physical audio and camera
-clock-domain behavior remains controller-specific and must be verified with
-board-level timing and device models.
+The DMA directed test covers native-AXI4 stream TX backpressure, two-word
+stream RX to memory, exact transfer length, and bus errors. The I2S and DVP
+FIFO tests continue to cover PIO mode. Physical audio and camera clock-domain
+behavior remains controller-specific and must be verified with board-level
+timing and device models.