feat: add formal verification properties for DMA design and corresponding testbench

- Introduced  to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created  as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added  to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.

scripts/run_c_tests.py

@@ -28,6 +28,7 @@ TEST_SOURCES = (
     "crt/src/hal/psram_math.c",
     "crt/src/hal/sdram_math.c",
     "crt/src/hal/i2s_math.c",
+    "crt/src/hal/dma_math.c",
     "crt/src/hal/sysctrl.c",
     "rtl/managed/clusterip/ps2/sw/src/ps2.c",
     "rtl/managed/clusterip/ps2/sw/src/ps2_keyboard.c",