feat: add formal verification properties for DMA design and corresponding testbench

- Introduced  to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created  as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added  to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.

tests/test_dma.py

@@ -11,7 +11,7 @@ from pathlib import Path
 ROOT = Path(__file__).resolve().parents[1]
 
 
-def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -> None:
+def test_dma_reports_native_axi4_errors_bursts_and_streams(tmp_path: Path) -> None:
     iverilog = shutil.which("iverilog")
     vvp = shutil.which("vvp")
     if iverilog is None or vvp is None:
@@ -38,13 +38,18 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
                 "+define+SV_ASSRT_DISABLE",
                 f"+incdir+{memory_map / 'rtl'}",
                 f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
+                f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/interface'}",
+                f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/stream'}",
+                f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/utils'}",
                 f"+incdir+{ROOT / 'rtl/mini/top'}",
-                str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
+                f"+incdir+{ROOT / 'rtl/ip/peripheral'}",
+                str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv"),
-                str(ROOT / "rtl/mini/top/rib_if.sv"),
-                str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"),
-                str(ROOT / "rtl/ip/peripheral/apb4_dma.sv"),
+                str(ROOT / "rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_pkg.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_req_if.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv"),
                 str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
                 str(ROOT / "tests/rtl/dma_error_tb.sv"),
                 "",
@@ -70,4 +75,73 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
         check=True,
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
-    assert "dma error, burst performance, and AXI4-Stream test passed" in result.stdout
+    assert "DMA native AXI4 burst, backpressure, stream, and error test passed" in result.stdout
+
+
+def test_dma_apb_registers_and_irq(tmp_path: Path) -> None:
+    iverilog = shutil.which("iverilog")
+    vvp = shutil.which("vvp")
+    if iverilog is None or vvp is None:
+        return
+
+    memory_map = tmp_path / "memory_map"
+    subprocess.run(
+        [
+            sys.executable,
+            str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
+            "--map",
+            str(ROOT / "rtl/mini/address_map/memory_map.json"),
+            "--output-dir",
+            str(memory_map),
+            "--have-sram-if",
+            "NO",
+        ],
+        check=True,
+    )
+    common = ROOT / "rtl/managed/clusterip/common/rtl"
+    source_list = tmp_path / "dma_reg.fl"
+    source_list.write_text(
+        "\n".join(
+            [
+                "+define+SV_ASSRT_DISABLE",
+                f"+incdir+{memory_map / 'rtl'}",
+                f"+incdir+{common / 'interface'}",
+                f"+incdir+{common / 'stream'}",
+                f"+incdir+{common / 'utils'}",
+                f"+incdir+{ROOT / 'rtl/ip/peripheral'}",
+                str(common / "interface/apb4_if.sv"),
+                str(common / "interface/axi4_if.sv"),
+                str(common / "interface/axi4_stream_if.sv"),
+                str(common / "utils/fifo.sv"),
+                str(common / "stream/round_robin_arbiter.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_pkg.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_req_if.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_reg.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
+                str(ROOT / "rtl/ip/peripheral/apb4_dma.sv"),
+                str(ROOT / "tests/rtl/dma_reg_tb.sv"),
+                "",
+            ]
+        ),
+        encoding="utf-8",
+    )
+    converted = tmp_path / "dma_reg_tb.v"
+    subprocess.run(
+        [
+            sys.executable,
+            str(ROOT / "rtl/mini/script/convt_sv2v.py"),
+            "-f",
+            str(source_list),
+            "--output",
+            str(converted),
+        ],
+        check=True,
+    )
+    simulation = tmp_path / "dma_reg_tb"
+    subprocess.run(
+        [iverilog, "-g2012", "-s", "dma_reg_tb", "-o", str(simulation), str(converted)],
+        check=True,
+    )
+    result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
+    assert "DMA APB register and aggregate IRQ test passed" in result.stdout