feat: add AXI4 interconnect testbench and enhance existing tests

- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors.
- Updated  and  to reflect changes in bus naming conventions.
- Enhanced  to include AXI4-Stream interface checks and validate stream data transfers.
- Modified  to integrate AXI4-Stream interfaces for improved DMA testing.
- Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification.
- Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation.
- Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.

tests/test_script_tools.py

@@ -737,7 +737,7 @@ def test_management_core_is_fixed_to_hazard3_with_debug() -> None:
     assert "CORE_$(CORE)" not in makefile
     assert "`ifdef CORE_" not in wrapper
     assert "`ifdef HAVE_DEBUG" not in wrapper
-    assert "ahbl2ribp u_ahbl2ribp" in wrapper
+    assert "ahbl2axi4 u_ahbl2axi4" in wrapper
     assert ".RESET_VECTOR       (`SOC_CPU_RESET_ADDR)" in wrapper
     assert ".DEBUG_SUPPORT      (1)" in wrapper