feat: add USB2 support and related tests

- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.

scripts/check_clock_reset_domains.py

@@ -15,6 +15,7 @@ CDC_PRIMITIVES = {
     "async_fifo",
     "async_reqack",
     "cdc_2phase",
+    "cdc_fifo",
     "cdc_sync",
     "cdc_fifo_warm_flush",
     "edge_det",

scripts/run_c_tests.py

@@ -28,6 +28,7 @@ TEST_SOURCES = (
     "crt/src/hal/psram_math.c",
     "crt/src/hal/sdram_math.c",
     "crt/src/hal/sdio_math.c",
+    "crt/src/hal/usb2_math.c",
     "crt/src/hal/spisd_math.c",
     "crt/src/hal/i2s_math.c",
     "crt/src/hal/dma_math.c",