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https://github.com/retroSoC/retroSoC.git
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feat: add USB2 support and related tests
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
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@@ -39,6 +39,7 @@ def test_clock_reset_domain_inventory_matches_the_rcu() -> None:
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"audio",
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"jtag",
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"dvp",
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"usb2_ulpi",
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}
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assert {
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(crossing["name"], crossing["source"], crossing["destination"])
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@@ -51,6 +52,32 @@ def test_clock_reset_domain_inventory_matches_the_rcu() -> None:
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crossing for crossing in document["crossings"] if crossing["name"] == "clint_timebase"
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)
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assert clint["primitive"] == "edge_det"
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assert {
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"usb2_work",
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"usb2_result",
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"usb2_setup",
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"usb2_fill_command",
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"usb2_drain_command",
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"usb2_buffer_event",
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"usb2_view_request",
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"usb2_view_response",
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"usb2_fill_stream",
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"usb2_drain_stream",
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"usb2_role",
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"usb2_role_reset",
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"usb2_phy_reset",
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"usb2_high_speed",
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"usb2_enable",
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"usb2_device_addr",
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"usb2_endpoint_config",
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"usb2_timeout",
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"usb2_phy_status",
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"usb2_transaction_busy",
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"usb2_frame",
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"usb2_ecc_counts",
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"usb2_retry_event",
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"usb2_protocol_event",
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} <= {crossing["name"] for crossing in document["crossings"]}
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assert {
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"rtc_command",
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"rtc_response",
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