feat: add USB2 support and related tests

- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.

tests/test_memory_map.py

@@ -65,6 +65,7 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "RS_SOC_APB4_SDIO_BASE" not in header
     assert "RS_SOC_APB4_SDIO0_BASE UINT32_C(0x1000F000)" in header
     assert "RS_SOC_APB4_SDIO1_BASE UINT32_C(0x10015000)" in header
+    assert "RS_SOC_APB4_USB2_BASE UINT32_C(0x10016000)" in header
     assert "RS_SOC_NMI_" not in header
     assert "RS_SOC_OPIPSRAM_BASE UINT32_C(0x48000000)" in header
     assert "RS_SOC_HAS_SRAM 1U" in header
@@ -76,6 +77,8 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "SOC_SYSCTRL_PERF_SDIO0_WAIT_HI_OFFSET 32'h00000090" in rtl
     assert "SOC_SYSCTRL_PERF_SDIO1_WAIT_LO_OFFSET 32'h00000094" in rtl
     assert "SOC_SYSCTRL_PERF_SDIO1_WAIT_HI_OFFSET 32'h00000098" in rtl
+    assert "SOC_SYSCTRL_PERF_USB2_WAIT_LO_OFFSET 32'h0000009C" in rtl
+    assert "SOC_SYSCTRL_PERF_USB2_WAIT_HI_OFFSET 32'h000000A0" in rtl
     assert "SOC_ADDR_IS_APB4_PERIPH(addr)" in rtl
     assert "SOC_ADDR_IS_NMI" not in rtl
     user_policy = rtl.split("`define SOC_USER_ADDR_READABLE", 1)[1].split(
@@ -92,6 +95,8 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "RS_SOC_SYSCTRL_PERF_SDIO0_WAIT_HI_OFFSET UINT32_C(0x00000090)" in header
     assert "RS_SOC_SYSCTRL_PERF_SDIO1_WAIT_LO_OFFSET UINT32_C(0x00000094)" in header
     assert "RS_SOC_SYSCTRL_PERF_SDIO1_WAIT_HI_OFFSET UINT32_C(0x00000098)" in header
+    assert "RS_SOC_SYSCTRL_PERF_USB2_WAIT_LO_OFFSET UINT32_C(0x0000009C)" in header
+    assert "RS_SOC_SYSCTRL_PERF_USB2_WAIT_HI_OFFSET UINT32_C(0x000000A0)" in header
     assert "PSRAM (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 0x02000000" in linker
     assert "OPIPSRAM (wxa!ri) : ORIGIN = 0x48000000, LENGTH = 0x08000000" in linker
 
@@ -124,8 +129,10 @@ def test_user_ip_is_always_emitted_for_the_fixed_platform(tmp_path: Path) -> Non
     assert "#define RS_SOC_APB4_OPIPSRAM_BASE UINT32_C(0x10010000)" in header
     assert "`define SOC_ADDR_APB4_SDIO0_BASE 32'h1000F000" in rtl
     assert "`define SOC_ADDR_APB4_SDIO1_BASE 32'h10015000" in rtl
+    assert "`define SOC_ADDR_APB4_USB2_BASE 32'h10016000" in rtl
     assert "`define SOC_ADDR_APB4_CRYPTO_BASE 32'h1000C000" in rtl
     assert "#define RS_SOC_APB4_CRYPTO_BASE UINT32_C(0x1000C000)" in header
+    assert "#define RS_SOC_APB4_USB2_BASE UINT32_C(0x10016000)" in header
 
 
 def test_bootstrap_assembly_uses_the_generated_gpio_admin_base() -> None: