feat: add USB2 support and related tests

- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.

tests/test_sta_constraints.py

@@ -17,6 +17,7 @@ DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
 PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
 GENERATOR = ROOT / "physical/smoke/sta/opensta/generate_sdc.py"
 OPENSTA_MAKEFILE = ROOT / "physical/smoke/sta/opensta/opensta.mk"
+PDK_TIMING_MAKEFILE = ROOT / "physical/smoke/sta/opensta/pdk_timing.mk"
 RCU = ROOT / "rtl/mini/top/rcu.sv"
 RETROSOC_ASIC = ROOT / "rtl/mini/top/retrosoc_asic.sv"
 GF180_GENERATOR = ROOT / "physical/pdk/generate_gf180_liberty.py"
@@ -52,9 +53,14 @@ def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
     assert "create_clock -name clk_audio -period 54.253472222" in sdc
     assert "create_clock -name clk_jtag -period 100" in sdc
     assert "create_clock -name clk_dvp -period 41.666666667" in sdc
+    assert "create_clock -name clk_usb2_ulpi -period 16.666666667" in sdc
     assert "get_pins -quiet" in sdc
     assert "get_ports -quiet" in sdc
     assert "set clk_jtag_port [require_ports \"clock jtag\" {jtag_tck_i_pad}]" in sdc
+    assert (
+        "set clk_usb2_ulpi_port [require_ports \"clock usb2_ulpi\" "
+        "{usb2_ulpi_clk_i_pad}]"
+    ) in sdc
     assert "u_retrosoc.u_apb4_periph.u_axi4_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
     assert "-group [get_clocks {clk_external clk_system}]" in sdc
     assert "set_clock_transition 0.1 [get_clocks {clk_dvp}]" in sdc
@@ -79,6 +85,14 @@ def test_opensta_invocation_exits_after_a_tcl_error() -> None:
     assert "$(OPENSTA) -no_init -exit -threads $(OPENSTA_THREADS)" in makefile
 
 
+def test_ihp130_core_sta_loads_usb2_packet_ram_liberties() -> None:
+    makefile = PDK_TIMING_MAKEFILE.read_text(encoding="utf-8")
+
+    assert "RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib" in makefile
+    assert "RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib" in makefile
+    assert "OPENSTA_SRAM_LIBS := $(IHP130_USB2_SRAM_LIBS)" in makefile
+
+
 def test_core_sdc_rejects_pads_missing_from_the_pin_map(tmp_path: Path) -> None:
     document = json.loads(DOMAINS.read_text(encoding="utf-8"))
     document["domains"][3]["sta"]["source_port"] = "missing_pad"