feat: refactor UART and Timer Interfaces; Remove Unused Components

- Deleted the UART interface and related components from the RTL design, including the UART TX/RX signals and instances.
- Removed the timer interface and its associated files from the project, including the timer definitions and references in the integration files.
- Updated the APB target configurations to reflect the removal of the UART and timer components, ensuring the IRQ and memory map configurations are consistent.
- Adjusted the formal verification properties and testbenches to exclude references to the removed components.
- Cleaned up the integration documentation to accurately describe the current state of the system without the UART and timer interfaces.

tests/rtl/rib2apb_tb.sv

@@ -12,13 +12,11 @@ module rib2apb_tb;
   rib_if rib ();
   apb4_pure_if archinfo ();
   apb4_pure_if rng ();
-  apb4_pure_if uart ();
   apb4_pure_if pwm ();
   apb4_pure_if ps2 ();
   apb4_pure_if rtc ();
   apb4_pure_if wdg ();
   apb4_pure_if crc ();
-  apb4_pure_if tmr ();
   apb4_pure_if user_ip ();
 
   always #5 clk_i = ~clk_i;
@@ -29,9 +27,6 @@ module rib2apb_tb;
   assign rng.pready       = rng_ready;
   assign rng.prdata       = rng_rdata;
   assign rng.pslverr      = rng_slverr;
-  assign uart.pready      = 1'b0;
-  assign uart.prdata      = '0;
-  assign uart.pslverr     = 1'b0;
   assign pwm.pready       = 1'b0;
   assign pwm.prdata       = '0;
   assign pwm.pslverr      = 1'b0;
@@ -47,9 +42,6 @@ module rib2apb_tb;
   assign crc.pready       = 1'b0;
   assign crc.prdata       = '0;
   assign crc.pslverr      = 1'b0;
-  assign tmr.pready       = 1'b0;
-  assign tmr.prdata       = '0;
-  assign tmr.pslverr      = 1'b0;
   assign user_ip.pready   = 1'b0;
   assign user_ip.prdata   = '0;
   assign user_ip.pslverr  = 1'b0;
@@ -60,13 +52,11 @@ module rib2apb_tb;
       .rib     (rib),
       .archinfo(archinfo),
       .rng     (rng),
-      .uart    (uart),
       .pwm     (pwm),
       .ps2     (ps2),
       .rtc     (rtc),
       .wdg     (wdg),
       .crc     (crc),
-      .tmr     (tmr),
       .user_ip (user_ip)
   );
 

tests/rtl/soc_irq_topology_tb.sv

@@ -30,17 +30,31 @@ module soc_irq_topology_tb;
       expect_irq(32'd1 << bit_index);
     end
 
-    s_ribp_irq     = '0;
-    s_ribp_irq[10] = 1'b1;
-    expect_irq(32'd1 << 17);
+    for (int bit_index = 10; bit_index < `SOC_IRQ_RIBP_WIDTH; bit_index++) begin
+      s_ribp_irq            = '0;
+      s_ribp_irq[bit_index] = 1'b1;
+      expect_irq(32'd1 << (bit_index + 7));
+    end
 
     for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
       s_ribp_irq           = '0;
       s_apb_irq            = '0;
       s_apb_irq[bit_index] = 1'b1;
-      expect_irq(32'd1 << (10 + bit_index));
+      case (bit_index)
+        0:       expect_irq(32'd1 << 11);
+        1:       expect_irq(32'd1 << 12);
+        2:       expect_irq(32'd1 << 13);
+        3:       expect_irq(32'd1 << 14);
+        4:       expect_irq(32'd1 << 16);
+        default: $fatal(1, "unexpected APB IRQ bit %0d", bit_index);
+      endcase
     end
 
+    s_apb_irq = '0;
+    expect_irq('0);
+    if (s_irq[10] !== 1'b0 || s_irq[15] !== 1'b0) begin
+      $fatal(1, "removed core IRQ bits are not low: IRQ10=%b IRQ15=%b", s_irq[10], s_irq[15]);
+    end
     if (s_irq[31:18] !== '0) begin
       $fatal(1, "unallocated core IRQ bits are not low: %h", s_irq[31:18]);
     end