feat: enhance DMA functionality with TCD and CRC support

- Added TCD head and count registers to DMA definition and register files.
- Introduced CRC expected and result registers for enhanced error checking.
- Updated DMA version to 2.0 to reflect new features.
- Modified DMA testbench to validate new TCD and CRC functionalities.
- Enhanced README and filelists to include new dependencies and configurations.
- Updated formal verification and runtime tests to accommodate new DMA features.

tests/test_script_tools.py

@@ -137,6 +137,15 @@ def test_generate_all_is_stable_and_expands_paths(tmp_path: Path) -> None:
     }.issubset({path.name for path in generated})
 
 
+def test_netlist_support_filelist_is_an_explicit_testbench_allowlist(tmp_path: Path) -> None:
+    generate_all(tmp_path, ["+define+PDK_IHP130"])
+
+    support = parse_filelists([tmp_path / "netlist_support.fl"])
+    source_names = {path.name for path in support.files}
+
+    assert source_names == {"register.sv", "rst_sync.sv"}
+
+
 def test_filelist_round_trips_verilog_define_values(tmp_path: Path) -> None:
     generate_all(tmp_path, ["+define+SOC_JTAG_IDCODE=32'hDEADBEEF"])