feat: add support for ICS55 PDK in various components and tools

- Introduced Verilator and Yosys warning configurations for ICS55.
- Updated RTL filelists to include functional models for ICS55.
- Modified memory modules to use wire instead of logic for clock and reset signals.
- Enhanced Makefile and Iverilog configurations to support ICS55.
- Implemented new simulation cells for ICS55 in the tech library.
- Updated regression scripts and tests to include ICS55 support.
- Added functionality to prepare ICS55 liberty and simulation models.
- Enhanced testbench to validate ICS55 specific components and behaviors.

configs/ci/ics55.mk

@@ -0,0 +1,10 @@
+SOC             := MINI
+PDK             := ICS55
+HAVE_PLL        := NO
+HAVE_SRAM_IF    := NO
+HAVE_SRAM_MACRO := NO
+HAVE_SVA        := NO
+ISA             := RV32IM
+HAVE_CSR        := NO
+APP             := bringup
+LINK_TYPE       := ld2_psram