feat: add support for ICS55 PDK in various components and tools

- Introduced Verilator and Yosys warning configurations for ICS55.
- Updated RTL filelists to include functional models for ICS55.
- Modified memory modules to use wire instead of logic for clock and reset signals.
- Enhanced Makefile and Iverilog configurations to support ICS55.
- Implemented new simulation cells for ICS55 in the tech library.
- Updated regression scripts and tests to include ICS55 support.
- Added functionality to prepare ICS55 liberty and simulation models.
- Enhanced testbench to validate ICS55 specific components and behaviors.

scripts/regress.py

@@ -58,6 +58,7 @@ NIGHTLY_PROFILES = PR_PROFILES
 PDK_PR_PROFILES = {
     "GF180": "configs/ci/gf180.mk",
     "IHP130": "configs/ci/ihp130.mk",
+    "ICS55": "configs/ci/ics55.mk",
     "SKY130": "configs/ci/sky130.mk",
 }