Add the frozen display path on top of the committed SPI-P3 integration:
the project-owned ST7789VI four-wire adapter in app/board (held-CS
command/data chains, D/C at clean boundaries with readback, bounded
workspaces), the TINY_SPI_P4_ACCEPTANCE ci_smoke image (discovery, panel
init ordering, color bars, gradient, odd rectangles, rotation variant,
abort/recover/release/reacquire case, measurements), the pin-independent
panel oracle rtl/tiny/dv/tiny_st7789_panel.sv, the golden geometry/pixel
checker scripts/spi_p4.py, pytest contracts tests/test_spi_p4.py and the
st7789vi host tests. The runbook is docs/ip/spi-p4.md.
Validation: Verilator acceptance passes on both Tiny profiles at
SIM_TEST_PASS Tiny cycles=43019427 (build/ics55-tiny-2026-10-23-01-37-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-38-616e0604657d/) and Icarus behavioral
passes on both profiles with the documented QUICK delay/geometry variant at
cycles=2710932 (build/ics55-tiny-2026-10-23-01-34-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-39-616e0604657d/); the independent golden
checker reports zero problems on all four logs (8/8 windows, pixel counts
and FNV-1a checksums, violations=0); full Pytest 2102 passed, 0 failed,
1 skipped; C format/policy/host and RTL format gates clean.
Sub-stage B (PSRAM-source display, sequential capture/verify/SD save,
SRAM-vs-PSRAM performance) remains gated on R2-P8/R2-P9 human acceptance.
SPI-P5 remains deferred; phase_accepted stays false. Recorded in
docs/ip/spi-verification.md.
