- Added interface to and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in to reflect new domain names.
- Modified expected outputs in to include new clock domains.
- Adjusted chip configuration assertions in to account for additional power pads.
- Enhanced memory map tests in with new definitions and includes.
- Updated pin mapping tests in to include new reference clock pads.
- Improved script tools tests in to ensure correct validation of extension bindings.
- Refined system control tests in to include new clock control interface.
- Updated USB2 packet RAM tests in to include new SRAM definitions.
- Enhanced user extensions tests in to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
- Updated README.md to clarify the status of KianV RV32IMA and PicoRV32 in the user-extension map.
- Modified Makefile to include USER_EXTENSIONS_SOURCE in MPW variant stamp dependencies.
- Enhanced integration README.md to better describe the relationship between user_extensions.json and mpw.toml.
- Updated generate_user_extensions.py to include design_id in ExtensionTarget and enforce unique design IDs.
- Changed user_extensions.json schema version to 2 and added design_id fields for core and IP targets.
- Refactored generate_mpw.py to support the new manifest structure and validate design selections.
- Adjusted sysctrl_tb.sv test cases to reflect changes in user core reset states.
- Enhanced test_opipsram.py to utilize ccache for improved compilation performance.
- Updated test_script_tools.py to include new tests for active manifest generation.
- Modified test_user_extensions.py to validate isolated scalar bindings and reject duplicate design selections.
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors.
- Updated and to reflect changes in bus naming conventions.
- Enhanced to include AXI4-Stream interface checks and validate stream data transfers.
- Modified to integrate AXI4-Stream interfaces for improved DMA testing.
- Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification.
- Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation.
- Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
- Eliminated the HAVE_DEBUG preprocessor directive and all associated code from the RTL and test files.
- Updated the Emulator class to remove JTAG-related debug signals and configurations.
- Adjusted the pin map and JSON configurations to exclude debug-related entries.
- Modified the management core wrapper to only support the HAZARD3 core, removing references to the PICORV32 core.
- Updated tests to reflect the removal of the HAVE_DEBUG feature, ensuring they no longer check for debug-related conditions.
- Cleaned up various scripts and makefiles to remove dependencies on the HAVE_DEBUG flag, streamlining the build process.
- Implemented module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge.
- Created to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure.
- Updated and modules to include JTAG interface signals.
- Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB.
- Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios.
- Updated SDC generation to include JTAG clock domain and port requirements.
- Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
maksyuki